Abstract: A semiconductor structure includes an upper semiconductor build having an upper crackstop structure along its periphery, an upper semiconductor build insulator layer, and a plurality of upper semiconductor build electrical contact bonding pads within the insulator layer. The upper semiconductor build crackstop structure includes first and second upper semiconductor build crackstop portions ending in first and second upper semiconductor build non electrical contact bonding pads within the insulator layer. A lower semiconductor build is generally similar to the upper semiconductor build, and the two builds are connected by a hybrid bond joining interface including metal-to-metal bonding of the bonding pads, and dielectric bonding of the insulator layers.

Abstract: A method is presented forming a fully-aligned via (FAV) and airgaps within a semiconductor device. The method includes forming a plurality of copper (Cu) trenches within an insulating layer, forming a plurality of ILD regions over exposed portions of the insulating layer, selectively removing a first section of the ILD regions in an airgap region, and maintaining a second section of the ILD regions in a non-airgap region. The method further includes forming airgaps in the airgap region and forming a via in the non-airgap region contacting a Cu trench of the plurality of Cu trenches.

Abstract: An antenna structure is electrically fixed and connected to a main board of an electronic apparatus and includes a circuit board, a high-frequency radiation layer, and a low-frequency radiation layer. The circuit board is a square body with a front surface, a back surface, a top surface, a bottom surface, and two side surfaces. The high-frequency radiation layer is arranged on the front surface of the circuit board and includes a high-frequency coupling edge thereon. The low-frequency radiation layer is arranged on the back surface of the circuit board and includes a low-frequency coupling edge thereon. Moreover, the high-frequency radiation layer and the low-frequency radiation layer fail to overlap with each other. The high-frequency coupling edge and the low-frequency coupling edge couple together to generate a bandwidth of a transmitting-and-receiving frequency of the antenna structure.

Abstract: A semiconductor structure comprising a substrate, a first metal layer on top of the substrate, a second metal layer on top of the first metal layer and a dielectric layer adjacent to the second metal layer and at least part of the first metal layer and on top of at least part of the first metal layer. The first metal layer includes a via. The width of the second metal layer is the same as the width of the via of the first metal layer.

Abstract: A vertical antenna structure is electrically fixed and connected to a main board of an electronic apparatus. The vertical antenna structure includes a circuit board, an electrode layer, and a semi-hole electrode layer. The circuit board is a square body with a front surface, a back surface, a top surface, a bottom surface and two side surfaces. The electrode layer is arranged on the front surface and the back surface of the circuit board. The semi-hole electrode layer is arranged on the bottom surface of the circuit board. The semi-hole electrode layer is electrically fixed and connected to the electrode layer. Moreover, the electrode layer and the semi-hole electrode layer are electrically fixed and connected to the main board.

Abstract: A semiconductor integrated circuit (IC) device includes a backside fuse structure and a backside contact. The backside fuse structure is located within the backside of the semiconductor IC device vertically between a transistor there above and a backside back end of the line (BEOL) network. The backside fuse structure includes a fuse wire and a deep via contact that is connected to both the fuse wire and to a frontside BEOL network. The backside contact is connected to the transistor, to the backside BEOL network, and to the fuse wire. The backside fuse structure may be in a non-programmed state or a programmed state. When in a non-programmed state, an open circuit exists that prevents current flow through the fuse wire or through the backside contact.

Abstract: A method for selectively depositing graphene on cobalt caps on copper interconnects for dual damascene structures in a back-end-of-line substrate is provided. The method comprises providing a semiconductor substrate comprising a first dielectric layer, the copper interconnect in the first dielectric layer, and the cobalt cap on the copper interconnect, the cobalt cap having an exposed metal surface, wherein the exposed metal surface comprises cobalt, and selectively depositing carbon layer on the exposed metal surface.

Abstract: The present invention discloses a receptor inhibitor of formula (I), a pharmaceutical composition comprising the same and the use thereof.

Abstract: A method is presented forming a fully-aligned via (FAV) and airgaps within a semiconductor device. The method includes forming a plurality of copper (Cu) trenches within an insulating layer, forming a plurality of ILD regions over exposed portions of the insulating layer, selectively removing a first section of the ILD regions in an airgap region, and maintaining a second section of the ILD regions in a non-airgap region. The method further includes forming airgaps in the airgap region and forming a via in the non-airgap region contacting a Cu trench of the plurality of Cu trenches.

Abstract: An antenna structure electrically fixed on a main board of an electronic apparatus includes a high-frequency-radiation layer, a low-frequency-radiation layer, an electrode layer and a circuit board including a front surface, a back surface, and a notch. The notch allows a left pin and a right pin formed on a lower side of the circuit board. The high-frequency-radiation layer is arranged on the front surface. The low-frequency-radiation layer is arranged on the front surface or the back surface. A coupling gap is formed between the low-frequency-radiation layer and the high-frequency-radiation layer. The electrode layer is arranged on the left pin and the right pin, and electrically connected to the high-frequency-radiation layer and the low-frequency-radiation layer. The antenna structure belongs to the monopole-feed-in-coupling-loop-grounding design. When used in the main boards of different sizes, variation in grounding has a very little effect on the efficiency attenuation of the antenna structure.

Abstract: The present disclosure provides a distance detection device. The distance detection device includes a light source configured to emit pulse light beams sequentially; and a scanning module including a first optical module, a second optical module, and drivers. The first optical module and the second optical module are sequentially positioned on an optical path of the light beams emitted by the light source, the drivers drive the first optical module and the second optical module to move to sequentially project the light beams emitted by the light source to different directions and form a strip-shaped scanning range after being emitted from the scanning module.

Abstract: The present invention discloses a receptor inhibitor of formula (I), a pharmaceutical composition comprising the same and the use thereof.

Abstract: A microelectronic structure including a backside-power-distribution-network (BSDPN) connected to a backside of a device region. The BSPDN includes a plurality of first type power rails and a plurality of second type power rails located on the same level. A first power plane located on a level above the plurality of first type power rails and the plurality of second type power rails. The first power plane extends across the plurality of first type power rails and the plurality of second type power rails and the first power plane is connected to a plurality of first type power rails, but not connected to the plurality of second type power rails.

Abstract: Embodiments of the invention are directed to a computer system having a processor communicatively coupled to a memory. The processor performs processor operations that include accessing an electronic file that includes an electronic integrated circuit (IC) design. The electronic file is operable to control a fabrication system to fabricate an IC according to the electronic IC design. The processor operations further includes applying a bulging predication analysis to the electronic IC design; and making one or more changes to the electronic IC design based at least in part on a result of the bulging prediction analysis.

Abstract: A semiconductor device includes a porous dielectric layer including a recessed portion, a conductive layer formed in the recessed portion, and a cap layer formed on the porous dielectric layer and on the conductive layer in the recessed portion, an upper surface of the porous dielectric layer being exposed through a gap in the cap layer.

Abstract: A flexible antenna structure includes a soft board, a first hard board, a soft antenna circuit and an antenna substructure. Moreover, the first hard board is arranged on the soft board. The soft antenna circuit is arranged on the soft board. The antenna substructure is arranged on the first hard board or is defined in the first hard board.

Abstract: A semiconductor interconnect structure and formation thereof. The semiconductor interconnect structure includes a plurality of metal lines of a first metal level. The semiconductor interconnect structure further includes a via formed substantially offset from a centerline of a first metal line and at least partially through a first portion of the first metal line located beneath the via.

Abstract: Embodiments of the invention include a method for fabricating a semiconductor device and the resulting structure. First and second FETs are formed. A top surface of the semiconductor structure is bonded to a carrier wafer. The semiconductor structure is flipped. A MIM capacitor plane comprising first and second metal layers is formed. An ILD layer is formed on the MIM capacitor plane. A first trench is formed within the MIM capacitor plane and the ILD layer. Exposed portions of the first metal layer are recessed within the first trench. A second trench is formed within the MIM capacitor plane and the ILD layer. Exposed portions of the second metal layer are recessed. Dielectric spacers are formed in the recesses. A first backside contact is formed in the first trench and a second backside contact is formed in the second trench.

Abstract: A semiconductor structure including first metal lines embedded in a first dielectric layer, second metal lines embedded in a second dielectric layer, where the second metal lines arranged above the first metal lines, a top via extending between one of the first metal lines and one of the second metal lines, where the top via is self-aligned to the one of the first metal lines, and at least one air gap located adjacent to the top via between the first metal lines and the second metal lines.

Abstract: This application discloses distance detection apparatuses. The distance detection apparatus includes a light source, a transmitting and receiving lens, a detector, and an optical path change element. The light source is to emit a beam. The transmitting and receiving lens is to collimate the beam emitted by the light source, and converge at least a part of return light of the beam reflected by a to-be-detected object. The detector is placed with the light source on a same side of the transmitting and receiving lens, to convert at least a part of return light that passes through the transmitting and receiving lens into an electrical signal. The optical path change element is to change an optical path of the beam emitted by the light source or the return light that passes through the transmitting and receiving lens.