Abstract: A method for forming chamferless vias comprises receiving a substrate stack comprising a hard mask layer, a porous dielectric layer underlying the hard mask layer, a cap layer underlying the dielectric layer, and a conductive layer underlying the cap layer. The hard mask layer is opened to reveal a portion of the dielectric layer. A plurality of vias are opened to extend through the dielectric layer and the cap layer. A pore filling material comprising a thermally decomposable polymer is deposited into the vias. The pore filling material in the vias is hardened and driven into the pores of the dielectric layer adjacent to the vias by an annealing process. The hard mask layer is removed. A trench is patterned and etched coincident with the vias. A dissipation process is conducted to remove the pore filling material.

Abstract: A reel assembly includes first and second reel plates each having a central hole, a plurality of radial openings angularly spaced apart around the central hole, and a plurality of hub plate sections each extending radially into a respective opening and being bendable from a respective one of first and second reel plates to project substantially in an axial direction. The hub plate sections of the first and second reel plates form a hub body when they bend and extend between the first and second reel plates in an overlapping manner so that the hub plate sections of the first and second reel plates alternate with each other. A method of making the reel assembly is also disclosed.

Abstract: A method for preparing a Metal-Oxide-Semiconductor (MOS) transistor comprises the steps of forming a gate oxide layer on a substrate, forming a gate and a first dielectric layer on the gate oxide layer, forming a second dielectric layer on the sidewall of the gate, forming a third dielectric layer covering the first and the second dielectric layers, performing a first etching process to remove a portion of the third dielectric layer and performing a second etching process to form a spacer on the sidewall of the gate. The etching selectivity of the first etching process to the third dielectric layer and to the second dielectric layer is different from that of the second etching process such that the thickness of the second dielectric layer at the center of the substrate is smaller than the thickness of the second dielectric layer at the edge of the substrate.