Abstract: A method of forming a semiconductor device, includes forming a conductive layer in a recessed portion of a porous dielectric layer, partially removing a top portion of the conductive layer while maintaining a height of the porous dielectric layer, forming a conformal cap layer on the porous dielectric layer and the conductive layer in the recessed portion, polishing the conformal cap layer to form a gap in the conformal cap layer, such that an upper surface of the porous dielectric layer is exposed through the gap and an upper surface of the conductive layer is protected by the cap layer, and performing a heat treatment to burn out a pore filler of the porous dielectric layer through the exposed upper surface of the porous dielectric layer.

Abstract: A semiconductor device includes a porous dielectric layer formed on an interconnect layer and including a recessed portion, a conductive layer formed in the recessed portion, and a conformal cap layer formed on the porous dielectric layer and on the conductive layer in the recessed portion, an upper surface of the porous dielectric layer being exposed through a gap in the conformal cap layer. Porous dielectric material is protected by back-filled pore fillers or leave-in porogens from process integration such as chemical mechanical polishing (CMP). The pore fillers or porogens are removed after CMP and Cap process to achieve low capacitance. A self-aligned cap protects the conductor metal from exposing the severe conditions during the pore filler or porogen removal process.

Abstract: A wafer is provided. The wafer includes a dielectric layer, first and second metallization layer interconnects arrayed across the dielectric layer with the second metallization layer interconnects adjacent one another and surrounded by the first metallization layer interconnects and a cap. The first and second metallization layer interconnects have respective upper surfaces defining a first plane and a second plane recessed from the first plane, respectively. The cap is disposed on exposed surfaces of the second metallization layer interconnects and portions of the dielectric layer adjacent to the second metallization layer interconnects.

Abstract: A method for forming conductive structures for a semiconductor device includes depositing a reflow liner on walls of trenches formed in a dielectric layer and depositing a reflow material on the reflow liner. The reflow material is reflowed to collect in a lower portion of the trenches. The depositing and the reflowing steps are repeated until the trenches are aggregately filled with the reflow material. The reflow material is planarized to form conductive structures in the trenches.

Abstract: A method of forming a skip-via, including, forming a first dielectric layer on a first metallization layer, forming a second metallization layer on the first dielectric layer and a second dielectric layer on the second metallization layer, removing a section of the second dielectric layer to form a via to the second metallization layer, removing a portion of the second metallization layer to form an aperture, and removing an additional portion of the second metallization layer to form an exclusion zone.

Abstract: A method for forming trenches of an interconnect network in a substrate. The method includes forming a first trench in the substrate, which has a first width. The method also includes forming a second trench in the substrate, which has a second width that is greater than the first width. The method also includes depositing a metal layer into the trenches, applying a dielectric over the metal, and diffusing metal atoms from the trenches to the dielectric. The dielectric absorbs a majority of the metal atoms from the first trench while simultaneously absorbing only a minority of metal atoms from the second trench.

Abstract: A conductive line structure comprises a first conductive line arranged in a first dielectric layer, a second conductive line arranged in the first dielectric layer, a cap layer arranged on the first conductive line and the second conductive line, and an airgap arranged between the first conductive line and the second conductive line, the airgap defined by the first dielectric layer and the cap layer.

Abstract: A method of forming a skip-via, including, forming a first dielectric layer on a first metallization layer, forming a second metallization layer on the first dielectric layer and a second dielectric layer on the second metallization layer, removing a section of the second dielectric layer to form a via to the second metallization layer, removing a portion of the second metallization layer to form an aperture, and removing an additional portion of the second metallization layer to form an exclusion zone.

Abstract: Methods for enhancing mechanical strength of back-end-of-line (BEOL) dielectrics to prevent crack propagation within interconnect stacks are provided. After forming interconnect structures in a dielectric material layer, a pore filling material is introduced into pores of a portion of the dielectric material layer that is located in a crack stop region present around a periphery of a chip region. By filling the pores of the portion of the dielectric material layer located in the crack stop region, the mechanical strength of the dielectric material layer is selectively enhanced in the crack stop region.

Abstract: A conductive line structure comprises a first conductive line arranged in a first dielectric layer, a second conductive line arranged in the first dielectric layer, a cap layer arranged on the first conductive line and the second conductive line, and an airgap arranged between the first conductive line and the second conductive line, the airgap defined by the first dielectric layer and the cap layer.

Abstract: Methods for enhancing mechanical strength of back-end-of-line (BEOL) dielectrics to prevent crack propagation within interconnect stacks are provided. After forming interconnect structures in a dielectric material layer, a pore filling material is introduced into pores of a portion of the dielectric material layer that is located in a crack stop region present around a periphery of a chip region. By filling the pores of the portion of the dielectric material layer located in the crack stop region, the mechanical strength of the dielectric material layer is selectively enhanced in the crack stop region.

Abstract: A semiconductor device includes a porous dielectric layer formed on an interconnect layer and including a recessed portion, a conductive layer formed in the recessed portion, and a conformal cap layer formed on the porous dielectric layer and on the conductive layer in the recessed portion, an upper surface of the porous dielectric layer being exposed through a gap in the conformal cap layer. Porous dielectric material is protected by back-filled pore fillers or leave-in porogens from process integration such as chemical mechanical polishing (CMP). The pore fillers or porogens are removed after CMP and Cap process to achieve low capacitance. A self-aligned cap protects the conductor metal from exposing the severe conditions during the pore filler or porogen removal process.

Abstract: A conductive line structure comprises a first conductive line arranged in a first dielectric layer, a second conductive line arranged in the first dielectric layer, a cap layer arranged on the first conductive line and the second conductive line, and an airgap arranged between the first conductive line and the second conductive line, the airgap defined by the first dielectric layer and the cap layer.

Abstract: Capacitors and methods of forming the same include forming a gap in a dielectric layer underneath one or more conducting lines, such that the one or more conducting lines are suspended over the gap. A capacitor stack is deposited in the gap and on the conducting lines. Respective contacts are deposited on the conducting lines and on the capacitor stack.

Abstract: A semiconductor structure that includes: a semiconductor substrate having a semiconductor base and back end of the line (BEOL) wiring layers; a dielectric cap layer on the semiconductor base; trenches on the dielectric cap layer, each of the trenches including dielectric walls, a dielectric bottom in contact with the dielectric cap layer and a metal filling a space between the dielectric walls; air gap openings on the dielectric cap layer and interspersed with the trenches, each air gap opening between the dielectric wall from one metal trench and adjacent to the dielectric wall of a second metal, the dielectric cap layer forming a bottom of the air gap openings; and a second dielectric cap layer formed over the trenches and over the air gap openings, the second dielectric cap layer pinching off each air gap opening.

Abstract: The present invention is a variable-ratio line gear mechanism. The mechanism forms a transmission pair consisting of a driving line gear and a driven line gear, of which axes intersect at an arbitrary angle. Transmission is generated by point contact meshing movement of line teeth between the driving line gear and the driven line gear. A contact curve of the line tooth is designed in accordance with space conjugate curve meshing theory, and the designing equation is divided into an equal transmission ratio part and a variable transmission ratio part. The equal transmission ratio part provides a uniform transmission, and the variable transmission ratio part makes the transmission ratio smoothly transit. The line gear mechanism is able to provide periodically transmission with variable transmission ratio, to provide a plurality of transmission ratios during a movement period of the driven line gear, and to enable smooth transitions between respective transmission ratios in accordance with movement rules.

Abstract: Methods for enhancing mechanical strength of back-end-of-line (BEOL) dielectrics to prevent crack propagation within interconnect stacks are provided. After forming interconnect structures in a dielectric material layer, a pore filling material is introduced into pores of a portion of the dielectric material layer that is located in a crack stop region present around a periphery of a chip region. By filling the pores of the portion of the dielectric material layer located in the crack stop region, the mechanical strength of the dielectric material layer is selectively enhanced in the crack stop region.

Abstract: Capacitors and methods of forming the same include forming a gap in a dielectric layer underneath one or more conducting lines, such that the one or more conducting lines are suspended over the gap. A capacitor stack is deposited in the gap and on the conducting lines. Respective contacts are deposited on the conducting lines and on the capacitor stack.

Abstract: A method for forming trenches of an interconnect network in a substrate. The method includes forming a first trench in the substrate, which has a first width. The method also includes forming a second trench in the substrate, which has a second width that is greater than the first width. The method also includes depositing a metal layer into the trenches, applying a dielectric over the metal, and diffusing metal atoms from the trenches to the dielectric. The dielectric absorbs a majority of the metal atoms from the first trench while simultaneously absorbing only a minority of metal atoms from the second trench.

Abstract: Capacitors and methods of forming the same include forming a gap in a dielectric layer underneath one or more conducting lines, such that the one or more conducting lines are suspended over the gap. A capacitor stack is deposited in the gap and on the conducting lines. Respective contacts are deposited on the conducting lines and on the capacitor stack.