Patents by Inventor Huan Chen

Huan Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220271146
    Abstract: In some embodiments, a semiconductor device is provided. The semiconductor device includes a pair of source/drain regions disposed in a semiconductor substrate, where the source/drain regions are laterally spaced. A gate electrode is disposed over the semiconductor substrate between the source/drain regions. Sidewall spacers are disposed over the semiconductor substrate on opposite sides of the gate electrode. A silicide blocking structure is disposed over the sidewalls spacers, where respective sides of the source/drain regions facing the gate electrode are spaced apart from outer sides of the sidewall spacers and are substantially aligned with outer sidewalls of the silicide blocking structure.
    Type: Application
    Filed: February 9, 2022
    Publication date: August 25, 2022
    Inventors: Kong-Beng Thei, Chien-Chih Chou, Hsiao-Chin Tuan, Yi-Huan Chen, Alexander Kalnitsky
  • Patent number: 11417649
    Abstract: A semiconductor device includes a transistor. The transistor includes an active region in a substrate, a patterned conductive layer being a portion of an interconnection layer for routing, and an insulating layer extending over the substrate and configured to insulate the active region from the patterned conductive layer. The patterned conductive layer and the insulating layer serve as a gate of the transistor.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: August 16, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yi-Sheng Chen, Kong-Beng Thei, Fu-Jier Fan, Jung-Hui Kao, Yi-Huan Chen, Kau-Chu Lin
  • Patent number: 11410999
    Abstract: The present disclosure relates to an integrated circuit (IC) that includes a boundary region defined between a low voltage region and a high voltage region, and a method of formation. In some embodiments, the integrated circuit comprises an isolation structure disposed in the boundary region of the substrate. A first polysilicon component is disposed over the substrate alongside the isolation structure. A boundary dielectric layer is disposed on the isolation structure. A second polysilicon component is disposed on the sacrifice dielectric layer.
    Type: Grant
    Filed: February 21, 2020
    Date of Patent: August 9, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Huan Chen, Chien-Chih Chou, Alexander Kalnitsky, Kong-Beng Thei, Ming Chyi Liu, Shih-Chung Hsiao, Jhih-Bin Chen
  • Patent number: 11403017
    Abstract: A data compression technique involves: selecting, from a data block, a plurality of bit strings as sample data. The technique further involves: determining a set of characters included in the sample data. Each character in the set of characters is represented by at least one bit string among the plurality of bit strings. The technique further involves: compressing the data block if statistical characteristics of the set of characters match predetermined statistical characteristics. Accordingly, incompressible data can be filtered out efficiently and accurately, so as to utilize computing resources more efficiently.
    Type: Grant
    Filed: September 22, 2020
    Date of Patent: August 2, 2022
    Assignee: EMC IP Holding Company LLC
    Inventors: Shuo Lv, Huan Chen, Chen Gong, Ming Zhang, Leihu Zhang
  • Publication number: 20220238352
    Abstract: A chip package structure is provided. The chip package structure includes a wiring substrate including a substrate, a first pad, and a second pad. The first pad and the second pad are respectively over a first surface and a second surface of the substrate, and the first pad is narrower than the second pad. The chip package structure includes a conductive adhesive layer over the first pad. The conductive adhesive layer is in direct contact with the first pad. The chip package structure includes a nickel layer over the conductive adhesive layer. The chip package structure includes a chip over the wiring substrate. The chip package structure includes a conductive bump between the nickel layer and the chip. The conductive bump includes gold.
    Type: Application
    Filed: April 11, 2022
    Publication date: July 28, 2022
    Inventors: Kuo-Ching HSU, Yu-Huan CHEN, Chen-Shien CHEN
  • Publication number: 20220214876
    Abstract: Techniques for managing threads involve acquiring respective runtime addresses and call information of a plurality of lock objects in a plurality of threads, and determining, from the plurality of lock objects, a first group of lock objects associated with first call information and a second group of lock objects associated with second call information different from the first call information. The techniques further involve providing an indication that a deadlock exists in the plurality of threads if it is determined that a first group of runtime addresses of the first group of lock objects overlaps with a second group of runtime addresses of the second group of lock objects. Accordingly, potential deadlocks in a plurality of threads can be analyzed, thereby avoiding the inability of the threads to proceed normally due to the deadlocks.
    Type: Application
    Filed: March 22, 2021
    Publication date: July 7, 2022
    Inventors: Ming Zhang, Huan Chen, Shuo Lv
  • Publication number: 20220213363
    Abstract: A two-component adhesive composition is provided. The two-component adhesive composition comprises an isocyanate component, an isocyanate-reactive component and an polyether amine-epoxy silane adduct, and can achieve superior adhesion strength between the adhesive and a substrate like metal alloy substrate. A laminated article prepared with said composition, a method for preparing the article and the use of the polyether amine-epoxy silane adduct as adhesion promoter in a two-component polyurethane adhesive composition are also provided.
    Type: Application
    Filed: May 15, 2019
    Publication date: July 7, 2022
    Inventors: Qingwei Meng, Yu Chen, Shaoguang Feng, Huan Chen, Xuemei Zhai
  • Patent number: 11366163
    Abstract: The present invention relates to a solid testing platform and method for function testing of an intelligent phase-change switch. The testing platform includes a primary controller, a first module, a second module, a capacitor C, an intelligent phase-change switch, and a transformer. The primary controller is respectively connected to the first module and the second module, and is configured to control the operation of the first module and the second module. The first module and the second module are connected in parallel to the capacitor C. the first module is configured to feed back excess energy of the capacitor C to a distribution network. The second module is configured to control magnitude and direction of a current that flows through the intelligent phase-change switch. The capacitor C is configured to perform energy support, filtering, and smoothing.
    Type: Grant
    Filed: November 13, 2020
    Date of Patent: June 21, 2022
    Assignee: LINCANG POWER SUPPLY BUREAU YUNNAN POWER GRID CO., LTD.
    Inventors: Wen Li, Huan Chen, Hongwen Liu, Jisheng Huang, Jindong Yang, Kang Yao
  • Publication number: 20220177753
    Abstract: A two-component adhesive composition is provided. The two-component adhesive composition comprises an isocyanate component, an isocyanate-reactive component and an amine-epoxy adduct, and can achieve superior adhesion strength between the adhesive and a substrate like metal alloy substrate. A laminated article prepared with said composition, a method for preparing the article and the use of the amine-epoxy adduct as adhesion promoter in a two-component polyurethane adhesive composition are also provided.
    Type: Application
    Filed: May 15, 2019
    Publication date: June 9, 2022
    Inventors: Yu Chen, Shaoguang Feng, Qingwei Meng, Yanli Feng, Huan Chen, Xuemei Zhai
  • Publication number: 20220180090
    Abstract: The present disclosure provides a neural network-based visual detection and tracking method of an inspection robot, which includes the following steps of: 1) acquiring environmental images of a dynamic background a movement process of the robot; 2) preprocessing the acquired images; 3) detecting human targets and specific behaviors in the images in the robot body, and saving the sizes, position information and features of the human targets with the specific behaviors; 4) controlling the orientation of a robot gimbal by using a target tracking algorithm to make sure that a specific target is always located at the central positions of the images; and 5) controlling the robot to move along with a tracked object. The neural network-based visual detection and tracking method of an inspection robot in the present disclosure has a quite high adaptive ability, achieves better detection and tracking effects on targets in a dynamic background scene.
    Type: Application
    Filed: June 16, 2021
    Publication date: June 9, 2022
    Inventors: Yongduan Song, Li Huang, Shilei Tan, Junfeng Lai, Huan Liu, Ziqiang Jiang, Jie Zhang, Huan Chen, Jiangyu Wu, Hong Long, Fang Hu, Qin Hu
  • Publication number: 20220177635
    Abstract: A waterborne polyurethane dispersion is provided. The waterborne polyurethane dispersion comprises residual moiety of a hydroxy-terminated siloxane compound in the main chain and exhibits good anti-stickiness while retaining superior mechanical properties. A laminated synthetic leather article prepared with said waterborne polyurethane dispersion as well the method for preparing the synthetic leather article are also provided.
    Type: Application
    Filed: March 15, 2019
    Publication date: June 9, 2022
    Inventors: Yanli Feng, Hongyu Chen, Shaoguang Feng, Huan Chen, Lili Shi, Xiuyuan Ni, Lingyun Pang, Ming Bao
  • Publication number: 20220171395
    Abstract: A method for obstacle detection and recognition for an intelligent snow sweeping robot is disclosed, comprising: 1) disposing ultrasonic sensors at a front end of the snow sweeping robot to detect distance information from an obstacle ahead; and disposing radar sensors at the front and rear of the snow sweeping robot to detect whether a creature suddenly approaches; 2) processing signals detected by each of the ultrasonic sensors and radar sensors, and calculating a forward distance of the snow sweeping robot; and 3) determining a snow cover extent of a working road, detecting a change of the distance from the obstacles, and recognizing the obstacles for conditions of an ultrasonic ranging variation ratio and a variation of the forward distance of the snow sweeping robot, a change of the signal detected by radar sensors, and a descriptive statistic of the snow cover extent within a specific time period.
    Type: Application
    Filed: July 22, 2021
    Publication date: June 2, 2022
    Applicant: Chongqing University
    Inventors: Yongduan Song, Ziqiang Jiang, Shilei Tan, Junfeng Lai, Huan Liu, Li Huang, Jie Zhang, Huan Chen, Hong Long, Fang Hu, Jiangyu Wu, Qin Hu, Wenqi Li
  • Patent number: 11341049
    Abstract: Techniques involve managing a storage system. A target storage device is selected from multiple storage devices associated with the storage system in response to respective wear degrees of the multiple storage devices being higher than a first predetermined threshold. Regarding multiple extents in the multiple storage devices, respective access loads of the multiple extents are determined. A source extent is selected from multiple extents residing on storage devices other than the target storage device, on the basis of the respective access loads of the multiple extents. Data in the source extent are moved to the target storage device. Various storage devices in a resource pool may be prevented from reaching the end of life at close times, and further data loss may be avoided.
    Type: Grant
    Filed: October 16, 2019
    Date of Patent: May 24, 2022
    Assignee: EMC IP Holding Company LLC
    Inventors: Shuo Lv, Ming Zhang, Huan Chen
  • Publication number: 20220152817
    Abstract: The present disclosure discloses a neural network adaptive tracking control method for joint robots, which proposes two schemes: robust adaptive control and neural adaptive control, comprising the following steps: 1) establishing a joint robot system model; 2) establishing a state space expression and an error definition when taking into consideration both the drive failure and actuator saturation of the joint robot system; 3) designing a PID controller and updating algorithms of the joint robot system; and 4) using the designed PID controller and updating algorithms to realize the control of the trajectory motion of the joint robot. The present disclosure may solve the following technical problems at the same time: the drive saturation and coupling effect in the joint system, processing parameter uncertainty and non-parametric uncertainty, execution failure handling during the system operation, compensation for non-vanishing interference, and the like.
    Type: Application
    Filed: March 24, 2021
    Publication date: May 19, 2022
    Inventors: Yongduan SONG, Huan LIU, Junfeng LAI, Ziqiang JIANG, Jie ZHANG, Huan CHEN, Li HUANG, Congyi ZHANG, Yingrui CHEN, Yating YANG, Chunxu REN, Han BAO, Kuilong YANG, Ge SONG, Bowen ZHANG, Hong LONG
  • Publication number: 20220154055
    Abstract: A two-component adhesive composition is provided. The two-component adhesive composition comprises an isocyanate component, an isocyanate-reactive component and an epoxy-aromatic diisocyanate adduct, and can achieve superior adhesion strength between the adhesive and a substrate like metal alloy substrate. A laminated article prepared with said composition, a method for preparing the article and the use of the epoxy-aromatic diisocyanate adduct as adhesion promoter in a two-component polyurethane adhesive composition are also provided.
    Type: Application
    Filed: May 15, 2019
    Publication date: May 19, 2022
    Inventors: Qingwei Meng, Yu Chen, Shaoguang Feng, Jing Liu, Huan Chen, Xuemei Zhai
  • Patent number: 11335634
    Abstract: A method for forming a chip package structure is provided. The method includes providing a wiring substrate. The method includes sequentially forming a nickel-containing layer and a gold-containing layer over the first pad. The method includes forming a conductive protection layer covering the gold-containing layer over the nickel-containing layer. The method includes bonding a chip to the wiring substrate through a conductive bump and a flux layer surrounding the conductive bump. The conductive bump is between the second pad and the chip. The method includes removing the flux layer while the conductive protection layer covers the nickel-containing layer.
    Type: Grant
    Filed: June 5, 2020
    Date of Patent: May 17, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Huan Chen, Kuo-Ching Hsu, Chen-Shien Chen
  • Publication number: 20220147155
    Abstract: Examples of keyboards with touch-sensitive pads are described herein.
    Type: Application
    Filed: July 26, 2019
    Publication date: May 12, 2022
    Applicant: Hewlett-Packard Development Company, L.P.
    Inventor: Huan-Chen Liu
  • Patent number: 11324336
    Abstract: The present disclosure provides an air cushion bed, which includes an upper air cushion, a lower air cushion, and a pull belt body. The pull belt body is disposed between the upper air cushion and the lower air cushion, and is supported by the pull belt body. The pull belt body includes an annular belt body and longitudinal belt bodies, the annular belt body is disposed along four sides of the upper air cushion and the lower air cushion, and the annular belt body is further connected to the upper air cushion and the lower air cushion, the longitudinal belt bodies are disposed between the upper air cushion and the lower air cushion, and two ends of the longitudinal belt bodies are connected to the upper air cushion and the lower air cushion, the annular belt body includes a first sealed bag body structure spaced from the longitudinal belt bodies.
    Type: Grant
    Filed: November 29, 2021
    Date of Patent: May 10, 2022
    Assignee: FUZHOU NIANYUE INVESTMENT CONSULTING CO., LTD
    Inventor: Huan Chen
  • Patent number: 11302691
    Abstract: The present disclosure relates to an integrated circuit (IC) and a method of formation. In some embodiments, a low voltage region and a high voltage region are integrated in a substrate. A low voltage transistor device is disposed in the low voltage region and comprises a low voltage gate electrode and a low voltage gate dielectric separating the low voltage gate electrode from the substrate. A first interlayer dielectric layer is disposed over the substrate surrounding the low voltage gate electrode and the low voltage gate dielectric. A high voltage transistor device is disposed in the high voltage region and comprises a high voltage gate electrode disposed on the first interlayer dielectric layer.
    Type: Grant
    Filed: September 2, 2020
    Date of Patent: April 12, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kong-Beng Thei, Chien-Chih Chou, Fu-Jier Fan, Hsiao-Chin Tuan, Yi-Huan Chen, Alexander Kalnitsky, Yi-Sheng Chen
  • Patent number: 11302537
    Abstract: A method for forming a chip package structure is provided. The method includes providing a wiring substrate including a substrate, a pad, and a polymer layer. The polymer layer is over the substrate and the pad, and the polymer layer has a first opening exposing the pad. The method includes forming a conductive adhesive layer over the polymer layer and the pad. The conductive adhesive layer is in direct contact with and conformally covers the polymer layer and the pad. The method includes forming a nickel layer over the conductive adhesive layer. The nickel layer is thicker than the conductive adhesive layer, and the nickel layer and the conductive adhesive layer are made of different materials. The method includes bonding a chip to the wiring substrate through a conductive bump. The conductive bump is between the nickel layer and the chip.
    Type: Grant
    Filed: April 1, 2020
    Date of Patent: April 12, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Ching Hsu, Yu-Huan Chen, Chen-Shien Chen