Abstract: A semiconductor device includes a channel structure, a first gate structure straddling the channel structure, and an epitaxial structure. The epitaxial structure is adjacent to the first gate structure and is coupled to an end of the channel structure. The semiconductor device further includes a first contact structure disposed over and in contact with the epitaxial structure and a nitride-based conformal layer extending at least over the first contact structure. The semiconductor device further includes an oxide-based layer disposed over the nitride-based conformal layer. A portion of the nitride-based conformal layer, disposed over the first contact structure, has a dip that is filled with a first portion of the oxide-based layer.

Abstract: An improved work function layer and a method of forming the same are disclosed. In an embodiment, the method includes forming a semiconductor fin extending from a substrate; depositing a dielectric layer over the semiconductor fin; depositing a first work function layer over the dielectric layer; and exposing the first work function layer to a metastable plasma of a first reaction gas, a metastable plasma of a generation gas, and a metastable plasma of a second reaction gas, the first reaction gas being different from the second reaction gas.

Abstract: Semiconductor structures and methods are provided. An exemplary method includes receiving a structure comprising a metal feature, a first passivation structure over the metal feature, and a first opening extending through the first passivation structure and exposing the metal feature. The exemplary method also includes forming a conductive layer in the first opening; forming a second passivation structure over the conductive layer, performing a first etching process to form a second opening extending through the second passivation structure and exposing the conductive layer, performing a second etching process to selectively remove an upper portion of the second passivation structure to enlarge an upper portion of the second opening, and after the performing of the second etching process, forming a conductive feature in the second opening.

Abstract: A magnetic tunnel junction (MTJ) memory cell comprising a connection via structure, a bottom electrode disposed on the connection via structure, a memory material stack disposed on the bottom electrode, and a conductive contact structure disposed on the memory material stack, in which a bottom surface of the conductive contact structure is in direct contact with a memory material layer of the memory material stack.

Abstract: A method of forming a semiconductor device includes: forming a first conductive feature in a first dielectric layer disposed over a substrate; forming a second dielectric layer over the first dielectric layer; etching the second dielectric layer using a patterned mask layer to form an opening in the second dielectric layer, where the opening exposes the first conductive feature; performing an ashing process to remove the patterned mask layer after the etching; wet cleaning the opening after the ashing process, where the wet cleaning enlarges a bottom portion of the opening; and filling the opening with a first electrically conductive material.

Abstract: A semiconductor device includes a channel structure, a first gate structure straddling the channel structure, and an epitaxial structure. The epitaxial structure is adjacent to the first gate structure and is coupled to an end of the channel structure. The semiconductor device further includes a first contact structure disposed over and in contact with the epitaxial structure and a nitride-based conformal layer extending at least over the first contact structure. The semiconductor device further includes an oxide-based layer disposed over the nitride-based conformal layer. A portion of the nitride-based conformal layer, disposed over the first contact structure, has a dip that is filled with a first portion of the oxide-based layer.

Abstract: A semiconductor device includes source/drain contacts, a gate structure, a gate dielectric cap, an etch stop layer, and a gate contact. The source/drain contacts are over a substrate. The gate structure is laterally between the source/drain contacts. The gate dielectric cap is over the gate structure and in contact with the source/drain contacts. The etch stop layer is over the source/drain contacts and the gate dielectric cap. The etch stop layer has an oxidized region directly above the gate dielectric cap. The gate contact extends through the etch stop layer and the gate dielectric cap to the gate structure. The gate contact and the oxidized region of the etch stop layer form an interface perpendicular to the substrate.

Abstract: Semiconductor devices and methods of manufacturing the semiconductor devices are described herein. A method includes forming a first opening through a dielectric layer, the first opening exposing a conductive region. A wet cleaning is used after the forming the first opening, and the first opening is treated after the wet cleaning the first opening, the treating the first opening comprising turning a sidewall treatment precursor and a bottom treatment precursor into a first plasma mixture, the sidewall treatment precursor being different from the bottom treatment precursor. The first opening is filled with a conductive material after the treating the first opening.

Abstract: Semiconductor devices and methods of manufacturing the semiconductor devices are described herein. A method includes forming a first opening through a dielectric layer, the first opening exposing a conductive region. A wet cleaning is used after the forming the first opening, and the first opening is treated after the wet cleaning the first opening, the treating the first opening comprising turning a sidewall treatment precursor and a bottom treatment precursor into a first plasma mixture, the sidewall treatment precursor being different from the bottom treatment precursor. The first opening is filled with a conductive material after the treating the first opening.

Abstract: A semiconductor device includes a semiconductor substrate, a gate structure, a silicon oxycarbonitride spacer, a silicon oxycarbide spacer, a silicon nitride spacer, and a source/drain structure. The gate structure is on the semiconductor substrate. The silicon oxycarbonitride spacer is on a sidewall of the gate structure. The silicon oxycarbide spacer is on a sidewall of the silicon oxycarbonitride spacer. The silicon nitride spacer is on a sidewall of the silicon oxycarbide spacer, in which an upper portion of the silicon nitride spacer has a lower density than a lower portion of the silicon nitride spacer. The source/drain structure is on the semiconductor substrate and adjacent to the gate structure.

Abstract: A semiconductor device includes a first source/drain structure coupled to an end of a first conduction channel that extends along a first direction; a second source/drain structure coupled to an end of a second conduction channel that extends along the first direction; a first isolation structure extending into the interlayer dielectric, disposed between the first and second source/drain structures, and disposed next to a gate structure along the first direction; and a second isolation structure below the first and second conduction channels. The second isolation structure includes a shallow trench isolation structure.

Abstract: A method includes forming a first high-k dielectric layer over a first semiconductor region, forming a second high-k dielectric layer over a second semiconductor region, forming a first metal layer comprising a first portion over the first high-k dielectric layer and a second portion over the second high-k dielectric layer, forming an etching mask over the second portion of the first metal layer, and etching the first portion of the first metal layer. The etching mask protects the second portion of the first metal layer. The etching mask is ashed using meta stable plasma. A second metal layer is then formed over the first high-k dielectric layer.

Abstract: Semiconductor devices and methods of manufacturing the semiconductor devices are described herein. A method includes forming a gate electrode, a gate electrode contact layer over the gate electrode, forming a dielectric layer over the gate electrode contact layer, and performing an etch through the dielectric layer, the etch forming an opening that exposes the gate electrode contact layer. The method further includes performing a post-etch treatment on the opening formed by the etch process by exposing the opening to a plasma. The method further includes forming gate electrode contacts in the openings after the post-etch treatment by a bottom-up deposition process.

Abstract: A method includes forming a first high-k dielectric layer over a first semiconductor region, forming a second high-k dielectric layer over a second semiconductor region, forming a first metal layer comprising a first portion over the first high-k dielectric layer and a second portion over the second high-k dielectric layer, forming an etching mask over the second portion of the first metal layer, and etching the first portion of the first metal layer. The etching mask protects the second portion of the first metal layer. The etching mask is ashed using meta stable plasma. A second metal layer is then formed over the first high-k dielectric layer.

Abstract: A method of forming a semiconductor device includes: forming a first conductive feature in a first dielectric layer disposed over a substrate; forming a second dielectric layer over the first dielectric layer; etching the second dielectric layer using a patterned mask layer to form an opening in the second dielectric layer, where the opening exposes the first conductive feature; performing an ashing process to remove the patterned mask layer after the etching; wet cleaning the opening after the ashing process, where the wet cleaning enlarges a bottom portion of the opening; and filling the opening with a first electrically conductive material.

Abstract: A semiconductor structure includes a gate, a self-aligned contact (SAC) layer that is disposed on the gate and that has a seam at a top surface of the SAC layer, a gate spacer that is formed on a sidewall of the gate, and a metal contact that is disposed adjacent to the gate spacer and that is spaced apart from the gate by the gate spacer. The SAC layer includes a filler that seals the seam in the SAC layer, and a top surface of the filler is coplanar with a top surface of the gate spacer and a top surface of the metal contact.

Abstract: A semiconductor device includes a first source/drain structure coupled to an end of a first conduction channel that extends along a first direction. The semiconductor device includes a second source/drain structure coupled to an end of a second conduction channel that extends along the first direction. The semiconductor device includes a first interconnect structure extending through an interlayer dielectric and electrically coupled to the first source/drain structure. The semiconductor device includes a second interconnect structure extending through the interlayer dielectric and electrically coupled to the second source/drain structure. The semiconductor device includes a first isolation structure disposed between the first and second source/drain structures and extending into the interlayer dielectric.

Abstract: Semiconductor devices and methods of manufacturing the semiconductor devices are described herein. A method includes forming a first etch stop layer from a portion of a gate mask, the gate mask extending between spacers adjacent a gate electrode, the gate electrode overlying a semiconductor fin. The method further includes forming a second etch stop layer adjacent the first etch stop layer, forming an opening through the second etch stop layer, and exposing the first etch stop layer by performing a first etching process. The method further includes extending the opening through the first etch stop layer and exposing the gate electrode by performing a second etching process. Once the gate electrode has been exposed, the method further includes forming a gate contact in the opening.

Abstract: A method includes forming a gate structure on a semiconductor substrate; depositing a carbon-containing seal layer over the gate structure; depositing a nitrogen-containing seal layer over the carbon-containing seal layer; introducing an oxygen-containing precursor on the nitrogen-containing seal layer; heating the substrate to dissociate the oxygen-containing precursor into an oxygen radical to dope into the nitrogen-containing seal layer; after heating the substrate, etching the nitrogen-containing seal layer and the carbon-containing seal layer, such that a remainder of the nitrogen-containing seal layer and the carbon-containing seal layer remains on a sidewall of the gate structure as a gate spacer.

Abstract: A device includes a source region and a drain region over a substrate. The device further includes a gate structure at least partially between the source region and the drain region, and a gate contact over the gate structure. The gate contact has an upper portion and a lower portion below the upper portion. The lower portion is more tapered than the upper portion.