Patents by Inventor Huan-Just Lin

Huan-Just Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11916131
    Abstract: According to an exemplary embodiment, a method of forming a vertical device is provided. The method includes: providing a protrusion over a substrate; forming an etch stop layer over the protrusion; laterally etching a sidewall of the etch stop layer; forming an insulating layer over the etch stop layer; forming a film layer over the insulating layer and the etch stop layer; performing chemical mechanical polishing on the film layer and exposing the etch stop layer; etching a portion of the etch stop layer to expose a top surface of the protrusion; forming an oxide layer over the protrusion and the film layer; and performing chemical mechanical polishing on the oxide layer and exposing the film layer.
    Type: Grant
    Filed: November 4, 2020
    Date of Patent: February 27, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: De-Fang Chen, Teng-Chun Tsai, Cheng-Tung Lin, Li-Ting Wang, Chun-Hung Lee, Ming-Ching Chang, Huan-Just Lin
  • Publication number: 20240030070
    Abstract: A device includes source/drain epitaxial structures over a substrate, source/drain contacts over the source/drain epitaxial structures, respectively, a gate structure laterally between the source/drain contacts, a gate dielectric cap over the gate structure, an oxide-based etch-resistant layer over the gate dielectric cap, a nitride-based etch stop layer over the oxide-based etch-resistant layer, and an interlayer dielectric (ILD) layer over the nitride-based etch stop layer. The device further includes a via structure extending through the ILD layer, the nitride-based etch stop layer, and the oxide-based etch-resistant layer to electrically connect with the one of the source/drain contacts.
    Type: Application
    Filed: October 4, 2023
    Publication date: January 25, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Te-Chih HSIUNG, Jyun-De WU, Peng WANG, Huan-Just LIN
  • Patent number: 11842930
    Abstract: A method may include forming a mask layer on top of a first dielectric layer formed on a first source/drain and a second source/drain, and creating an opening in the mask layer and the first dielectric layer that exposes portions of the first source/drain and the second source/drain. The method may include filling the opening with a metal layer that covers the exposed portions of the first source/drain and the second source/drain, and forming a gap in the metal layer to create a first metal contact and a second metal contact. The first metal contact may electrically couple to the first source/drain and the second metal contact may electrically couple to the second source/drain. The gap may separate the first metal contact from the second metal contact by less than nineteen nanometers.
    Type: Grant
    Filed: May 10, 2022
    Date of Patent: December 12, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Lien Huang, Ching-Feng Fu, Huan-Just Lin, Fu-Sheng Li, Tsai-Jung Ho, Bor Chiuan Hsieh, Guan-Xuan Chen, Guan-Ren Wang
  • Publication number: 20230386821
    Abstract: A method of forming a semiconductor device includes: forming a first conductive feature in a first dielectric layer disposed over a substrate; forming a second dielectric layer over the first dielectric layer; etching the second dielectric layer using a patterned mask layer to form an opening in the second dielectric layer, where the opening exposes the first conductive feature; performing an ashing process to remove the patterned mask layer after the etching; wet cleaning the opening after the ashing process, where the wet cleaning enlarges a bottom portion of the opening; and filling the opening with a first electrically conductive material.
    Type: Application
    Filed: July 26, 2023
    Publication date: November 30, 2023
    Inventors: Po-Chuan Wang, Guan-Xuan Chen, Chia-Yang Hung, Sheng-Liang Pan, Huan-Just Lin
  • Publication number: 20230387125
    Abstract: A semiconductor device includes a substrate, a semiconductor fin, a shallow trench isolation (STI) structure, an air spacer, and a gate structure. The semiconductor fin extends upwardly from the substrate. The STI structure laterally surrounds a lower portion of the semiconductor fin. The air spacer is interposed the STI structure and the semiconductor fin. The gate structure extends across the semiconductor fin.
    Type: Application
    Filed: July 31, 2023
    Publication date: November 30, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Lien HUANG, Che-Ming HSU, Ching-Feng FU, Huan-Just LIN
  • Publication number: 20230380293
    Abstract: A method for fabricating magnetic tunnel junction (MTJ) pillars is provided. The method includes following operations. A MTJ stack of layers including a first magnetic layer, a tunnel barrier layer overlying the first magnetic layer, and a second magnetic layer overlying the tunnel barrier layer is provided. A first patterning step is carried out by using a reactive ion etching. In the first patterning step, the second magnetic layer and the tunnel barrier layer are etched to form one or more pillar structures and a protection layer is formed and covers sidewalls of the pillar structures.
    Type: Application
    Filed: July 25, 2023
    Publication date: November 23, 2023
    Inventors: JIANN-HORNG LIN, KUN-YI LI, HAN-TING LIN, HUAN-JUST LIN, CHEN-JUNG WANG, SIN-YI YANG
  • Publication number: 20230378291
    Abstract: In some embodiments, the present disclosure relates to an integrated circuit device. A transistor structure is disposed over a substrate and includes a pair of source/drain regions and a gate electrode between the pair of source/drain regions. A lower inter-layer dielectric (ILD) layer is disposed over the pair of source/drain regions and surrounds the gate electrode. The gate electrode is recessed from top of the lower ILD layer. A gate capping layer is disposed on the gate electrode. The gate capping layer has a top surface aligned or coplanar with that of the lower ILD layer.
    Type: Application
    Filed: August 4, 2023
    Publication date: November 23, 2023
    Inventors: Yu-Lien Huang, Ching-Feng Fu, Huan-Just Lin
  • Publication number: 20230369325
    Abstract: In an embodiment, a method includes: depositing a protective layer on a source/drain region and a gate mask, the gate mask disposed on a gate structure, the gate structure disposed on a channel region of a substrate, the channel region adjoining the source/drain region; etching an opening through the protective layer, the opening exposing the source/drain region; depositing a metal in the opening and on the protective layer; annealing the metal to form a metal-semiconductor alloy region on the source/drain region; and removing residue of the metal from the opening with a cleaning process, the protective layer covering the gate mask during the cleaning process.
    Type: Application
    Filed: July 26, 2023
    Publication date: November 16, 2023
    Inventors: Yang-Cheng Wu, Yun-Hua Chen, Wen-Kuo Hsieh, Huan-Just Lin
  • Publication number: 20230361185
    Abstract: A device comprises a source/drain contact over a source/drain region of a transistor, an etch stop layer above the source/drain contact, an interlayer dielectric (ILD) layer above the etch stop layer, and a source/drain via extending through the ILD layer and the etch stop layer to the source/drain contact. The etch stop layer has an oxidized region in contact with the source/drain via and separated from the source/drain contact.
    Type: Application
    Filed: July 14, 2023
    Publication date: November 9, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Te-Chih HSIUNG, Yi-Chun CHANG, Yi-Chen WANG, Yuan-Tien TU, Huan-Just LIN, Jyun-De WU
  • Patent number: 11810919
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a first fin structure. The semiconductor device structure includes a first source/drain structure over the first fin structure. The semiconductor device structure includes a first dielectric layer over the first source/drain structure and the substrate. The semiconductor device structure includes a first conductive contact structure in the first dielectric layer and over the first source/drain structure. The semiconductor device structure includes a second dielectric layer over the first dielectric layer and the first conductive contact structure. The semiconductor device structure includes a first conductive via structure passing through the second dielectric layer and connected to the first conductive contact structure. The first conductive via structure has a first substantially strip shape in a top view of the first conductive via structure.
    Type: Grant
    Filed: June 17, 2021
    Date of Patent: November 7, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jyun-De Wu, Te-Chih Hsiung, Yi-Chun Chang, Yi-Chen Wang, Yuan-Tien Tu, Peng Wang, Huan-Just Lin
  • Publication number: 20230352344
    Abstract: A method includes forming a first inter-layer dielectric (ILD) layer over source and drain regions of a semiconductor structure; forming a first mask material over the first ILD layer; etching first openings in the first mask material; filling the first openings with a fill material; etching second openings in the fill material; filling the second openings with a second mask material; removing the fill material; and etching the first ILD layer using the first mask material and the second mask material as an etching mask to form openings in the first ILD layer that expose portions of the source and drain regions of the semiconductor structure.
    Type: Application
    Filed: June 29, 2023
    Publication date: November 2, 2023
    Inventors: Ching-Feng Fu, Yu-Lien Huang, Tsai-Jung Ho, Huan-Just Lin
  • Publication number: 20230343648
    Abstract: An improved work function layer and a method of forming the same are disclosed. In an embodiment, the method includes forming a semiconductor fin extending from a substrate; depositing a dielectric layer over the semiconductor fin; depositing a first work function layer over the dielectric layer; and exposing the first work function layer to a metastable plasma of a first reaction gas, a metastable plasma of a generation gas, and a metastable plasma of a second reaction gas, the first reaction gas being different from the second reaction gas.
    Type: Application
    Filed: June 30, 2023
    Publication date: October 26, 2023
    Inventors: Shao-Jyun Wu, Hung-Chi Wu, Chia-Ching Lee, Pin-Hsuan Yeh, Hung-Chin Chung, Hsien-Ming Lee, Chien-Hao Chen, Sheng-Liang Pan, Huan-Just Lin
  • Patent number: 11798943
    Abstract: In an embodiment, a method includes: depositing a protective layer on a source/drain region and a gate mask, the gate mask disposed on a gate structure, the gate structure disposed on a channel region of a substrate, the channel region adjoining the source/drain region; etching an opening through the protective layer, the opening exposing the source/drain region; depositing a metal in the opening and on the protective layer; annealing the metal to form a metal-semiconductor alloy region on the source/drain region; and removing residue of the metal from the opening with a cleaning process, the protective layer covering the gate mask during the cleaning process.
    Type: Grant
    Filed: June 4, 2021
    Date of Patent: October 24, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yang-Cheng Wu, Yun-Hua Chen, Wen-Kuo Hsieh, Huan-Just Lin
  • Publication number: 20230335435
    Abstract: A method includes forming a source/drain contact over a source/drain region. An ion implantation process is performed to form a doped region in a top of the source/drain contact. After the ion implantation process is performed, an interlayer dielectric (ILD) layer is deposited to cover the doped region of the source/drain contact. The ILD layer is etched to form a via opening exposing the source/drain contact. A source/drain via is filled in the via opening.
    Type: Application
    Filed: June 21, 2023
    Publication date: October 19, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Te-Chih HSIUNG, Jyun-De WU, Peng WANG, Huan-Just LIN
  • Publication number: 20230326978
    Abstract: A device comprises source/drain epitaxial structures over a substrate; source/drain contacts over the source/drain epitaxial structures, respectively; a gate structure laterally between the source/drain contacts; a gate dielectric cap over the gate structure and having a bottom surface below top surfaces of the source/drain contacts; an oxide-based etch-resistant layer over the gate dielectric cap; a nitride-based etch stop layer over the oxide-based etch-resistant layer; an interlayer dielectric (ILD) layer over the nitride-based etch stop layer; and a gate contact extending through the ILD layer, the nitride-based etch stop layer, the oxide-based etch-resistant layer, and the gate dielectric cap to electrically connect with the gate structure.
    Type: Application
    Filed: June 5, 2023
    Publication date: October 12, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Te-Chih HSIUNG, Peng WANG, Huan-Just LIN, Jyun-De WU
  • Patent number: 11770977
    Abstract: A method for fabricating magnetic tunnel junction (MTJ) pillars is provided. The method includes following operations. A MTJ stack of layers including a first magnetic layer, a tunnel barrier layer overlying the first magnetic layer, and a second magnetic layer overlying the tunnel barrier layer is provided. A first patterning step is carried out by using a reactive ion etching. In the first patterning step, the second magnetic layer and the tunnel barrier layer are etched to form one or more pillar structures and a protection layer is formed and covers sidewalk of the pillar structures.
    Type: Grant
    Filed: October 27, 2020
    Date of Patent: September 26, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Jiann-Horng Lin, Kun-Yi Li, Han-Ting Lin, Huan-Just Lin, Chen-Jung Wang, Sin-Yi Yang
  • Patent number: 11769770
    Abstract: A semiconductor device includes a substrate, a semiconductor fin, a shallow trench isolation (STI) structure, an air spacer, and a gate structure. The semiconductor fin extends upwardly from the substrate. The STI structure laterally surrounds a lower portion of the semiconductor fin. The air spacer is interposed the STI structure and the semiconductor fin. The gate structure extends across the semiconductor fin.
    Type: Grant
    Filed: May 6, 2021
    Date of Patent: September 26, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Lien Huang, Che-Ming Hsu, Ching-Feng Fu, Huan-Just Lin
  • Publication number: 20230298934
    Abstract: A semiconductor device includes a gate structure, source/drain regions, source/drain contacts, a gate dielectric cap, an etch stop layer, and a gate contact. The gate structure is over a substrate. The source/drain regions are at opposite sides of the gate structure. The source/drain contacts are over the source/drain regions, respectively. The gate dielectric cap is over the gate structure and has opposite sidewalls interfacing the source/drain contacts.
    Type: Application
    Filed: April 20, 2023
    Publication date: September 21, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Te-Chih HSIUNG, Yi-Chun CHANG, Jyun-De WU, Yi-Chen WANG, Yuan-Tien TU, Huan-Just LIN
  • Publication number: 20230282484
    Abstract: A method includes forming a first high-k dielectric layer over a first semiconductor region, forming a second high-k dielectric layer over a second semiconductor region, forming a first metal layer comprising a first portion over the first high-k dielectric layer and a second portion over the second high-k dielectric layer, forming an etching mask over the second portion of the first metal layer, and etching the first portion of the first metal layer. The etching mask protects the second portion of the first metal layer. The etching mask is ashed using meta stable plasma. A second metal layer is then formed over the first high-k dielectric layer.
    Type: Application
    Filed: May 12, 2023
    Publication date: September 7, 2023
    Inventors: Shao-Jyun Wu, Sheng-Liang Pan, Huan-Just Lin
  • Patent number: 11749732
    Abstract: A method comprises forming a source/drain contact over a source/drain region; forming an etch stop layer over the source/drain contact and an interlayer dielectric (ILD) layer over the etch stop layer; performing a first etching process to form a via opening extending through the ILD layer and a recess in the etch stop layer; oxidizing a sidewall of the recess in the etch stop layer; after oxidizing the sidewall of the recess in the etch stop layer, performing a second etching process to extend the via opening down to the source/drain contact; and after performing the second etching process, forming a source/drain via in the via opening.
    Type: Grant
    Filed: February 6, 2021
    Date of Patent: September 5, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Te-Chih Hsiung, Yi-Chun Chang, Yi-Chen Wang, Yuan-Tien Tu, Huan-Just Lin, Jyun-De Wu