Abstract: An integrated circuit includes a semiconductor substrate, a gate dielectric over the substrate, a metal gate structure over the semiconductor substrate and the gate dielectric, a dielectric film on the metal gate structure, the dielectric film comprising oxynitride combined with metal from the metal gate, and an interlayer dielectric (ILD) on either side of the metal gate structure.

Abstract: A method comprises depositing a sacrificial layer on a first dielectric layer over a substrate, applying a first patterning process, a second patterning process, a third patterning process and a fourth patterning process to the sacrificial layer to form a first group of openings, a second group of openings, a third group of openings and a fourth group of openings, respectively, in the sacrificial layer, wherein openings from different patterning processes are arranged in an alternating manner and four openings of the opening from the different patterning processes form a diamond shape and forming nanowires based on the first group of openings, the second group of openings, the third group of openings and the fourth group of openings.

Abstract: A method includes forming a pattern-reservation layer over a semiconductor substrate. The semiconductor substrate has a major surface. A first self-aligned multi-patterning process is performed to pattern a pattern-reservation layer. The remaining portions of the pattern-reservation layer include pattern-reservation strips extending in a first direction that is parallel to the major surface of the semiconductor substrate. A second self-aligned multi-patterning process is performed to pattern the pattern-reservation layer in a second direction parallel to the major surface of the semiconductor substrate. The remaining portions of the pattern-reservation layer include patterned features. The patterned features are used as an etching mask to form semiconductor nanowires by etching the semiconductor substrate.

Abstract: An integrated circuit having an improved gate contact and a method of making the circuit are provided. In an exemplary embodiment, the method includes receiving a substrate. The substrate includes a gate stack disposed on the substrate and an interlayer dielectric disposed on the gate stack. The interlayer dielectric is first etched to expose a portion of the gate electrode, and then the exposed portion of the gate electrode is etched to form a cavity. The cavity is shaped such that a portion of the gate electrode overhangs the electrode. A conductive material is deposited within the cavity and in electrical contact with the gate electrode. In some such embodiments, the etching of the gate electrode forms a curvilinear surface of the gate electrode that defines the cavity.

Abstract: According to an exemplary embodiment, a method of forming a vertical device is provided. The method includes: providing a protrusion over a substrate; forming an etch stop layer over the protrusion; laterally etching a sidewall of the etch stop layer; forming an insulating layer over the etch stop layer; forming a film layer over the insulating layer and the etch stop layer; performing chemical mechanical polishing on the film layer and exposing the etch stop layer; etching a portion of the etch stop layer to expose a top surface of the protrusion; forming an oxide layer over the protrusion and the film layer; and performing chemical mechanical polishing on the oxide layer and exposing the film layer.

Abstract: A method for self-aligned patterning includes providing a substrate, forming a patterned mandrel layer that includes a plurality of mandrel features, the patterned mandrel layer being formed on the substrate, depositing a first spacer layer over the mandrel layer, the first spacer layer comprising a first type of material, anisotropically etching the first spacer layer to leave a first set of spacers on sidewalls of the mandrel features, removing the mandrel layer, depositing a second spacer layer over remaining portions of the first set of spacers, and anisotropically etching the second spacer layer to form a second set of spacers on sidewalls of the first set of spacers.

Abstract: A method of forming a channel of a gate structure is provided. A first epitaxial channel layer is formed within a first trench of the gate structure. A dry etching process is performed on the first epitaxial channel layer to form a second trench. A second epitaxial channel layer is formed within the second trench.

Abstract: A method comprises depositing a sacrificial layer on a first dielectric layer over a substrate, applying a first patterning process, a second patterning process, a third patterning process and a fourth patterning process to the sacrificial layer to form a first group of openings, a second group of openings, a third group of openings and a fourth group of openings, respectively, in the sacrificial layer, wherein openings from different patterning processes are arranged in an alternating manner and four openings of the opening from the different patterning processes form a diamond shape and forming nanowires based on the first group of openings, the second group of openings, the third group of openings and the fourth group of openings.

Abstract: According to an exemplary embodiment, a method of forming a semiconductor device is provided. The method includes: providing a vertical structure over a substrate; forming an etch stop layer over the vertical structure; forming an oxide layer over the etch stop layer; performing chemical mechanical polishing on the oxide layer and stopping on the etch stop layer; etching back the oxide layer and the etch stop layer to expose a sidewall of the vertical structure and to form an isolation layer; oxidizing the sidewall of the vertical structure and doping oxygen into the isolation layer by using a cluster oxygen doping treatment.

Abstract: A method includes forming a pattern-reservation layer over a semiconductor substrate. The semiconductor substrate has a major surface. A first self-aligned multi-patterning process is performed to pattern a pattern-reservation layer. The remaining portions of the pattern-reservation layer include pattern-reservation strips extending in a first direction that is parallel to the major surface of the semiconductor substrate. A second self-aligned multi-patterning process is performed to pattern the pattern-reservation layer in a second direction parallel to the major surface of the semiconductor substrate. The remaining portions of the pattern-reservation layer include patterned features. The patterned features are used as an etching mask to form semiconductor nanowires by etching the semiconductor substrate.

Abstract: According to an exemplary embodiment, a method of forming a vertical device is provided. The method includes: providing a protrusion over a substrate; forming an etch stop layer over the protrusion; laterally etching a sidewall of the etch stop layer; forming an insulating layer over the etch stop layer; forming a film layer over the insulating layer and the etch stop layer; performing chemical mechanical polishing on the film layer and exposing the etch stop layer; etching a portion of the etch stop layer to expose a top surface of the protrusion; forming an oxide layer over the protrusion and the film layer; and performing chemical mechanical polishing on the oxide layer and exposing the film layer.

Abstract: A method of forming a channel of a gate structure is provided. A first epitaxial channel layer is formed within a first trench of the gate structure. A dry etching process is performed on the first epitaxial channel layer to form a second trench. A second epitaxial channel layer is formed within the second trench.

Abstract: According to an exemplary embodiment, a method of forming a semiconductor device is provided. The method includes: providing a vertical structure over a substrate; forming an etch stop layer over the vertical structure; forming an oxide layer over the etch stop layer; performing chemical mechanical polishing on the oxide layer and stopping on the etch stop layer; etching back the oxide layer and the etch stop layer to expose a sidewall of the vertical structure and to form an isolation layer; oxidizing the sidewall of the vertical structure and doping oxygen into the isolation layer by using a cluster oxygen doping treatment.

Abstract: A method comprises applying a first patterning process to a first photoresist layer to form a first opening, a second opening, a third opening and a fourth opening in the sacrificial layer, applying a second patterning process to a second photoresist layer to form a fifth opening, a sixth opening, a seventh opening and an eighth opening in the sacrificial layer, wherein distances between two adjacent openings formed from the first and second patterning processes are substantially equal to each other, applying a third patterning process to a third photoresist layer to form a ninth opening, a tenth opening, an eleventh opening and a twelfth opening in the sacrificial layer, wherein distances between two adjacent openings formed from the second and third patterning processes are substantially equal to each other and forming a plurality of nanowires based on the openings.

Abstract: A semiconductor structure, a semiconductor device, and a method for forming the semiconductor device are provided. In various embodiments, the method for forming the semiconductor device includes forming transistors on a substrate. Forming each transistor includes forming a doped region on the substrate. A nanowire is formed protruding from the doped region. An interlayer dielectric layer is deposited over the doped region. A dielectric layer is deposited over the interlayer dielectric layer and surrounding each of the nanowires. A first gate layer is deposited over the dielectric layer. The dielectric layer and first gate layer are etched to expose portions of the nanowires and the interlayer dielectric layer. A second gate layer is formed over the exposed interlayer dielectric layer and surrounding the first gate layer. Then, the second gate layer was patterned to remove the second gate layer on the interlayer dielectric layer between the transistors.

Abstract: A method comprises applying a first patterning process to a first photoresist layer to form a first opening, a second opening, a third opening and a fourth opening in the sacrificial layer, applying a second patterning process to a second photoresist layer to form a fifth opening, a sixth opening, a seventh opening and an eighth opening in the sacrificial layer, wherein distances between two adjacent openings formed from the first and second patterning processes are substantially equal to each other, applying a third patterning process to a third photoresist layer to form a ninth opening, a tenth opening, an eleventh opening and a twelfth opening in the sacrificial layer, wherein distances between two adjacent openings formed from the second and third patterning processes are substantially equal to each other and forming a plurality of nanowires based on the openings.

Abstract: An integrated circuit having an improved gate contact and a method of making the circuit are provided. In an exemplary embodiment, the method includes receiving a substrate. The substrate includes a gate stack disposed on the substrate and an interlayer dielectric disposed on the gate stack. The interlayer dielectric is first etched to expose a portion of the gate electrode, and then the exposed portion of the gate electrode is etched to form a cavity. The cavity is shaped such that a portion of the gate electrode overhangs the electrode. A conductive material is deposited within the cavity and in electrical contact with the gate electrode. In some such embodiments, the etching of the gate electrode forms a curvilinear surface of the gate electrode that defines the cavity.

Abstract: A method for fabricating a semiconductor device includes forming a plurality of first spacers over a substrate. A second spacer of a plurality of second spacers is deposited on sidewalls of each first spacer. In some embodiments, a spacing between adjacent first spacers is configured such that second spacers formed on sidewalls of the adjacent first spacers physically merge to form a merged second spacer. A second spacer cut process may be performed to selectively remove at least one second spacer. In some embodiments, a third spacer of a plurality of third spacers is formed on sidewalls of each second spacer. A third spacer cut process may be performed to selectively remove at least one third spacer. A first etch process is performed on the substrate to form fin regions. The plurality of third spacers mask portions of the substrate during the first etch process.

Abstract: A method for fabricating a semiconductor device includes forming a plurality of first spacers over a substrate. A second spacer of a plurality of second spacers is deposited on sidewalls of each first spacer. In some embodiments, a spacing between adjacent first spacers is configured such that second spacers formed on sidewalls of the adjacent first spacers physically merge to form a merged second spacer. A second spacer cut process may be performed to selectively remove at least one second spacer. In some embodiments, a third spacer of a plurality of third spacers is formed on sidewalls of each second spacer. A third spacer cut process may be performed to selectively remove at least one third spacer. A first etch process is performed on the substrate to form fin regions. The plurality of third spacers mask portions of the substrate during the first etch process.

Abstract: A method includes providing a semiconductor structure that includes an epitaxial layer and a cap layer above the epitaxial layer, filling a trench above the cap layer with a sacrificial layer, and removing the sacrificial layer. As such, the cap layer is protected by the sacrificial layer during an etching process and the epitaxial layer is protected by the cap layer during another etching process.