Abstract: The present disclosure relates to a semiconductor device including a substrate and first and second spacers on the substrate. The semiconductor device also includes a gate stack between the first and second spacers. The gate stack includes a gate dielectric layer having a first portion formed on the substrate and a second portion formed on the first and second spacers; an internal gate formed on the first and second portions of the gate dielectric layer; a ferroelectric dielectric layer formed on the internal gate and in contact with the gate dielectric layer; and a gate electrode on the ferroelectric dielectric layer.

Abstract: A heat dissipation fastener structure includes a support body, a heat sink, a cover body and an operation unit assembly. The support body comprises a window formed on an upper side and support legs extended from a lower side to together define a reciprocating space in communication with the window. The heat sink is formed with perforations at four corners and disposed in the reciprocating space. Threaded locking members, around which elastic members are fitted, are correspondingly passed through the perforations to mount the heat sink above a heat source in a floating state. The cover body is disposed on the support body and comprises at least one vertical folded edge. The operation unit assembly is disposed on the heat sink to drive the cover body to shield the threaded locking members and make the heat sink get close to or away from the heat source.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a base portion and a fin portion over the base portion. The semiconductor device structure includes an isolation layer over the base portion and surrounding the fin portion. The semiconductor device structure includes a metal gate stack over the isolation layer and wrapping around an upper part of the fin portion. The metal gate stack includes a gate dielectric layer and a metal gate electrode layer over the gate dielectric layer, and the gate dielectric layer includes fluorine. A first part of the isolation layer is not covered by the metal gate stack, the first part includes fluorine, and a first concentration of fluorine in the first part increases toward a first top surface of the first part.

Abstract: The method includes receiving a semiconductor device having a first surface and a second surface. The first surface is a top surface including a conductive material exposed thereon; and the second surface is an embedded surface including the conductive material and a dielectric material. The method also includes selecting a first polishing slurry to achieve a first polishing rate of the conductive material in the first polishing slurry and a second polishing rate of the dielectric material in the first polishing slurry. The method further includes selecting a second polishing slurry to achieve a third polishing rate of the conductive material in the second polishing slurry and a fourth polishing rate of the dielectric material in the second polishing slurry. The method additionally includes polishing the first surface with the first polishing slurry until the second surface is exposed; and polishing the second surface with the second polishing slurry.

Abstract: A ferroelectric memory cell (FeRAM) is disclosed that includes an active device (e.g., a transistor) and a passive device (e.g., a ferroelectric capacitor) integrated in a substrate. The transistor and its gate contacts are formed on a front side of the substrate. A carrier wafer can be bonded to the active device to allow the active device to be inverted so that the passive device and associated contacts can be electrically coupled from a back side of the substrate.

Abstract: A thermal module structure includes an aluminum base having a heat pipe receiving groove formed on one side thereof; a heat dissipation unit including a plurality of radiation fin assemblies or heat sinks and being provided with a first heat pipe receiving section; a plurality of heat pipes made of a copper material and respectively having a heat absorption section and a horizontally extended condensation section; and a copper embedding layer provided on surfaces of the heat pipe receiving groove and the first heat pipe receiving section. The aluminum base and the heat dissipation unit are horizontally parallelly arranged. The heat absorption sections are fitted in the heat pipe receiving groove, and the condensation sections are extended through the first heat pipe receiving section. With the copper embedding layer, the aluminum base and the heat dissipation unit can be directly welded to the heat pipes.

Abstract: A method includes removing a first dummy gate stack and a second dummy gate stack to form a first trench and a second trench. The first dummy gate stack and the second dummy gate stack are in a first device region and a second device region, respectively. The method further includes depositing a first gate dielectric layer and a second gate dielectric layer extending into the first trench and the second trench, respectively, forming a fluorine-containing layer comprising a first portion over the first gate dielectric layer, and a second portion over the second gate dielectric layer, removing the second portion, performing an annealing process to diffuse fluorine in the first portion into the first gate dielectric layer, and at a time after the annealing process, forming a first work-function layer and a second work-function layer over the first gate dielectric layer and the second gate dielectric layer, respectively.

Abstract: An anti-corrosive coating and a preparation method therefor are provided. The method includes the following steps: (1) dispersing graphite and a modifier in water to prepare a pretreated graphite dispersion; (2) stripping and modifying the pretreated graphite dispersion obtained in step (1) to prepare a modified graphene dispersion; and (3a) mixing the modified graphene dispersion obtained in the step (2) with epoxy resin and a cationic photoinitiator, standing, carry out phase splitting, removing a water phase, further deeply removing water to obtain a graphene/epoxy resin mixture, and curing the obtained mixture to obtain the anti-corrosive coating. By means of a phase transfer method, the application of a modified graphene aqueous dispersion in resin can be realized without drying graphene first, so that uniform dispersion of modified graphene in epoxy resin can be ensured, and additionally, stacking of the modified graphene in the drying process can be avoided.

Abstract: An electronic device includes a camera assembly, a function assembly, and a controller. The camera assembly is configured to capture a first depth image of a first user and a second depth image of the first user. The controller is configured to determine a first spatial position between the first user and the camera assembly according to the first depth image, and control the function assembly to execute a first action according to the first spatial position. The controller further configured to determine a relative displacement between the first user and the camera assembly according to the first depth image and the second depth image, and control the function assembly to execute a second action according to the relative displacement. The second action is an action to adjust a result of the function assembly based on the first action. A method and a non-transitory storage medium are also provided.

Abstract: A thermal module structure includes an aluminum base having an upper and a lower surface, at least one L-shaped copper heat pipe, a first aluminum fin assembly, a second aluminum fin assembly, and at least one copper embedding layer. The copper heat pipe includes a heat absorption section fitted on the aluminum base, and a heat dissipation section connected to the second aluminum fin assembly. The copper embedding layers are provided on the aluminum base at areas corresponding to the first aluminum fin assembly and the heat absorption section of the copper heat pipe, and on a bottom surface of the first aluminum fin assembly that is to be connected to the aluminum base. Thus, the first aluminum fin assembly and the copper heat pipe can be directly welded to the aluminum base via the copper embedding layers without the need of electroless nickel plating.

Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a first and second transistors arranged over a substrate. The first transistor includes first channel structures extending between first and second source/drain regions. A first gate electrode is arranged between the first channel structures, and a first protection layer is arranged over a topmost one of the first channel structures. The second transistor includes second channel structures extending between the second source/drain region and a third source/drain region. A second gate electrode is arranged between the second channel structures, and a second protection layer is arranged over a topmost one of the second channel structures. The integrated chip further includes a first interconnect structure arranged between the substrate and the first and second channel structures, and a contact plug structure coupled to the second source/drain region and arranged above the first and second gate electrodes.

Abstract: A dust-excluding carrier for product storage comprises a housing cavity and dust-excluding isolation members. The dust-excluding isolation member comprises a first main body, the first main body is provided with a first opening; the material tray and the dust-excluding isolation member are detachably connected. The material tray comprises a second main body with a second opening. The first main body and the second main body may be snap-fitted together and apart, so the first opening is covered by the second body and the second opening covered by the first body.

Abstract: An integrated circuit (IC) chip with polish stop layers and a method of fabricating the IC chip are disclosed. The method includes forming a first IC chip having a device region and a peripheral region. Forming the first IC chip includes forming a device layer on a substrate, forming an interconnect structure on the device layer, depositing a first dielectric layer on a first portion of the interconnect structure in the peripheral region, depositing a second dielectric layer on the first dielectric layer and on a second portion of the interconnect structure in the device region, and performing a polishing process on the second dielectric layer to substantially coplanarize a top surface of the second dielectric layer with a top surface of the first dielectric layer. The method further includes performing a bonding process on the second dielectric layer to bond a second IC chip to the first IC chip.

Abstract: The present disclosure provides a method for manufacturing a semiconductor. The method includes: forming a metal oxide layer over a gate structure over a substrate; forming a dielectric layer over the metal oxide layer; forming a metal layer over the metal oxide layer; and performing a chemical mechanical polish (CMP) operation to remove a portion of the dielectric layer and a portion of the metal layer, the CMP operation stopping at the metal oxide layer, wherein a slurry used in the CMP operation includes a ceria compound. The present disclosure also provides a method for planarizing a metal-dielectric surface.

Abstract: An apparatus for non-contact measuring temperature includes a stand, for securing a vapor chamber, wherein the vapor chamber comprises a condenser area and an evaporator area, wherein the evaporator area comprises a heating spot; a continuous-wave laser device, facing the stand, for irradiating the heating spot by providing an infrared laser beam, wherein the infrared laser beam comprises a first infrared wavelength range; a switch device, controlling an irradiating cycle of the infrared laser beam, wherein the irradiating cycle comprises a irradiating time-interval and a non-irradiating time-interval; a first infrared sensor, facing the stand, for collecting a first thermal radiation data of the heating spot in a second infrared wavelength range; a data processing unit, only transferring the first thermal radiation data in the non-irradiating time-interval into a first temperature, wherein the irradiating time-interval is longer than the non-irradiating time-interval.

Abstract: A method includes removing a first dummy gate stack and a second dummy gate stack to form a first trench and a second trench. The first dummy gate stack and the second dummy gate stack are in a first device region and a second device region, respectively. The method further includes depositing a first gate dielectric layer and a second gate dielectric layer extending into the first trench and the second trench, respectively, forming a fluorine-containing layer comprising a first portion over the first gate dielectric layer, and a second portion over the second gate dielectric layer, removing the second portion, performing an annealing process to diffuse fluorine in the first portion into the first gate dielectric layer, and at a time after the annealing process, forming a first work-function layer and a second work-function layer over the first gate dielectric layer and the second gate dielectric layer, respectively.

Abstract: The present disclosure describes forming a crystalline high-k dielectric layer at a reduced crystallization temperature in a semiconductor device. The method includes forming a channel structure on a substrate, forming an interfacial layer on the channel structure, forming a first high-k dielectric layer on the interfacial layer, forming dipoles in the first high-k dielectric layer with a dopant, and forming a second high-k dielectric layer on the first high-k dielectric layer. The dopant includes a first metal element. The second high-k dielectric layer includes a second metal element different from the first metal element.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a base portion and a fin portion over the base portion. The semiconductor device structure includes an isolation layer over the base portion and surrounding the fin portion. The isolation layer includes fluorine, and a first concentration of fluorine in the isolation layer increases toward a top surface of the isolation layer. The semiconductor device structure includes a gate stack over the isolation layer and wrapping around the fin portion.

Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, first and second fin structures formed over the substrate, and an isolation structure between the first and second fin structures. The isolation structure can include a lower portion and an upper portion. The lower portion of the isolation structure can include a metal-free dielectric material. The upper portion of the isolation structure can include a metallic element and silicon.

Abstract: The structure of a semiconductor device with different gate structures configured to provide ultra-low threshold voltages and a method of fabricating the semiconductor device are disclosed. The method includes forming first and second nanostructured channel regions in first and second nanostructured layers, respectively, and forming first and second gate-all-around (GAA) structures surrounding the first and second nanostructured channel regions, respectively. The forming the first and second GAA structures includes selectively forming an Al-based n-type work function metal layer and a Si-based capping layer on the first nanostructured channel regions, depositing a bi-layer of Al-free p-type work function metal layers on the first and second nanostructured channel regions, depositing a fluorine blocking layer on the bi-layer of Al-free p-type work function layers, and depositing a gate metal fill layer on the fluorine blocking layer.