Abstract: A system on a chip (SoC) with a Universal Asynchronous Receiver/Transmitter (UART) interface includes a UART interface circuit, a detection circuit, and a control circuit. The UART interface circuit includes: a plurality of UART signal pads for receiving and transmitting signals; and a UART voltage pad for receiving an external operating voltage. The detection circuit is configured to detect the magnitude of the external operating voltage and thereby generate a detection result. The control circuit is configured to determine setting of a supply voltage for the plurality of UART signal pads according to the detection result. The control circuit makes the setting of the supply voltage be compatible with the external operating voltage according to the detection result, wherein the external operating voltage is a lower first voltage or a higher second voltage, and the first lower voltage is equal to an internal device operating voltage of the SoC.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a source/drain epitaxial feature disposed over a substrate, a plurality of semiconductor layers disposed parallelly to each other and in contact with the source/drain epitaxial feature, a gate electrode layer surrounding a portion of each of the plurality of semiconductor layers, and a dielectric region in the substrate below the source/drain epitaxial feature. The dielectric region includes a first oxidation region having a first dopant, and a second oxidation region having a second dopant different than the first dopant.

Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, first and second fin structures formed over the substrate, and an isolation structure between the first and second fin structures. The isolation structure can include a lower portion and an upper portion. The lower portion of the isolation structure can include a metal-free dielectric material. The upper portion of the isolation structure can include a metallic element and silicon.

Abstract: A method for manufacturing a semiconductor structure includes: forming a first bonding layer on a device substrate, the first bonding layer including a first bonding sub-layer and a second bonding sub-layer, the first bonding sub-layer including a first metal oxide material in an amorphous state and a plurality of metal nanoparticles, the second bonding sub-layer including a second metal oxide material in an amorphous state; forming a second bonding layer on a carrier substrate, the second bonding layer including a third metal oxide material in an amorphous state; conducting a surface modification process on the first and second bonding layers; bonding the device and carrier substrates to each other through the first and second bonding layers; and annealing the first and second bonding layers to convert the first, second, and third metal oxide materials from the amorphous state to a crystalline state.

Abstract: The method includes receiving a semiconductor structure including a first surface, the first surface including a uniform material composition of ruthenium (Ru), selecting a first polishing slurry including a first abrasive component of titanium oxide and a first amine-based alkaline component of ammonium hydroxide, selecting a second polishing slurry including a second abrasive component of silicon oxide, a second amine-based alkaline component of hydroxyamine, and a non-amine alkaline component, polishing the first surface with the first polishing slurry until a second surface is exposed, the second surface including a conductive material and a dielectric material, and polishing the second surface with the second polishing slurry.

Abstract: In-situ defect count detection in post chemical mechanical polishing (post-CMP) is provided. Post-CMP is performed, in-situ and according to a recipe, on a surface of a semiconductor wafer within a post-CMP chamber. A light signal is scanned over a target area of the surface of the semiconductor wafer and a reflected light signal reflected from the target area is detected. A defect count of defects present in the target area is determined based on the reflected light signal reflected from the target area.

Abstract: The structure of a semiconductor device with different gate structures configured to provide ultra-low threshold voltages and a method of fabricating the semiconductor device are disclosed. The method includes forming first and second nanostructured channel regions in first and second nanostructured layers, respectively, and forming first and second gate-all-around (GAA) structures surrounding the first and second nanostructured channel regions, respectively. The forming the first and second GAA structures includes selectively forming an Al-based n-type work function metal layer and a Si-based capping layer on the first nanostructured channel regions, depositing a bi-layer of Al-free p-type work function metal layers on the first and second nanostructured channel regions, depositing a fluorine blocking layer on the bi-layer of Al-free p-type work function layers, and depositing a gate metal fill layer on the fluorine blocking layer.

Abstract: A thermal module includes a radiating fin unit having a plurality of superposed radiating fin assemblies, and a plurality of groups of heat pipes. The heat pipes respectively have a heat absorbing section and a heat dissipating section formed at two opposite ends thereof. The heat absorbing sections in each heat pipe group is in contact with a heat source, and the heat dissipating sections in the same heat pipe group is sandwiched between two adjacent ones of the radiating fin assemblies. The thermal module is characterized in that the heat dissipating sections are horizontally extended through the radiating fin assemblies from one of two opposite shorter sides to another shorter side along two parallel longer sides thereof, such that the heat dissipating sections not only have a maximum contact area with the radiating fin assemblies, but also give the radiating fin unit an enhanced structural strength.

Abstract: One or more active region structures each protrude vertically out of a substrate in a vertical direction and each extend horizontally in a first horizontal direction. A source/drain component is disposed over the one or more active region structures in the vertical direction. A source/drain contact is disposed over the source/drain component in the vertical direction. The source/drain contact includes a bottom portion and a top portion. A protective liner is disposed on side surfaces of the top portion of the source/drain contact but not on side surfaces of the bottom portion of the source/drain contact.

Abstract: Semiconductor structures and methods for manufacturing the same are provided. The method includes nanostructures formed over a substrate, and a gate structure formed on the nanostructures. The semiconductor structure includes a source/drain (S/D) structure formed adjacent to the gate structure. The semiconductor structure includes a contact structure formed on the S/D structure, and a portion of the contact structure is embedded in the S/D structure, and the contact structure has a T-shaped structure.

Abstract: The present disclosure relates to a semiconductor device including a substrate and first and second spacers on the substrate. The semiconductor device also includes a gate stack between the first and second spacers. The gate stack includes a gate dielectric layer having a first portion formed on the substrate and a second portion formed on the first and second spacers; an internal gate formed on the first and second portions of the gate dielectric layer; a ferroelectric dielectric layer formed on the internal gate and in contact with the gate dielectric layer; and a gate electrode on the ferroelectric dielectric layer.

Abstract: A heat dissipation fastener structure includes a support body, a heat sink, a cover body and an operation unit assembly. The support body comprises a window formed on an upper side and support legs extended from a lower side to together define a reciprocating space in communication with the window. The heat sink is formed with perforations at four corners and disposed in the reciprocating space. Threaded locking members, around which elastic members are fitted, are correspondingly passed through the perforations to mount the heat sink above a heat source in a floating state. The cover body is disposed on the support body and comprises at least one vertical folded edge. The operation unit assembly is disposed on the heat sink to drive the cover body to shield the threaded locking members and make the heat sink get close to or away from the heat source.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a base portion and a fin portion over the base portion. The semiconductor device structure includes an isolation layer over the base portion and surrounding the fin portion. The semiconductor device structure includes a metal gate stack over the isolation layer and wrapping around an upper part of the fin portion. The metal gate stack includes a gate dielectric layer and a metal gate electrode layer over the gate dielectric layer, and the gate dielectric layer includes fluorine. A first part of the isolation layer is not covered by the metal gate stack, the first part includes fluorine, and a first concentration of fluorine in the first part increases toward a first top surface of the first part.

Abstract: The method includes receiving a semiconductor device having a first surface and a second surface. The first surface is a top surface including a conductive material exposed thereon; and the second surface is an embedded surface including the conductive material and a dielectric material. The method also includes selecting a first polishing slurry to achieve a first polishing rate of the conductive material in the first polishing slurry and a second polishing rate of the dielectric material in the first polishing slurry. The method further includes selecting a second polishing slurry to achieve a third polishing rate of the conductive material in the second polishing slurry and a fourth polishing rate of the dielectric material in the second polishing slurry. The method additionally includes polishing the first surface with the first polishing slurry until the second surface is exposed; and polishing the second surface with the second polishing slurry.

Abstract: A ferroelectric memory cell (FeRAM) is disclosed that includes an active device (e.g., a transistor) and a passive device (e.g., a ferroelectric capacitor) integrated in a substrate. The transistor and its gate contacts are formed on a front side of the substrate. A carrier wafer can be bonded to the active device to allow the active device to be inverted so that the passive device and associated contacts can be electrically coupled from a back side of the substrate.

Abstract: A thermal module structure includes an aluminum base having a heat pipe receiving groove formed on one side thereof; a heat dissipation unit including a plurality of radiation fin assemblies or heat sinks and being provided with a first heat pipe receiving section; a plurality of heat pipes made of a copper material and respectively having a heat absorption section and a horizontally extended condensation section; and a copper embedding layer provided on surfaces of the heat pipe receiving groove and the first heat pipe receiving section. The aluminum base and the heat dissipation unit are horizontally parallelly arranged. The heat absorption sections are fitted in the heat pipe receiving groove, and the condensation sections are extended through the first heat pipe receiving section. With the copper embedding layer, the aluminum base and the heat dissipation unit can be directly welded to the heat pipes.

Abstract: A method includes removing a first dummy gate stack and a second dummy gate stack to form a first trench and a second trench. The first dummy gate stack and the second dummy gate stack are in a first device region and a second device region, respectively. The method further includes depositing a first gate dielectric layer and a second gate dielectric layer extending into the first trench and the second trench, respectively, forming a fluorine-containing layer comprising a first portion over the first gate dielectric layer, and a second portion over the second gate dielectric layer, removing the second portion, performing an annealing process to diffuse fluorine in the first portion into the first gate dielectric layer, and at a time after the annealing process, forming a first work-function layer and a second work-function layer over the first gate dielectric layer and the second gate dielectric layer, respectively.

Abstract: An electronic device includes a camera assembly, a function assembly, and a controller. The camera assembly is configured to capture a first depth image of a first user and a second depth image of the first user. The controller is configured to determine a first spatial position between the first user and the camera assembly according to the first depth image, and control the function assembly to execute a first action according to the first spatial position. The controller further configured to determine a relative displacement between the first user and the camera assembly according to the first depth image and the second depth image, and control the function assembly to execute a second action according to the relative displacement. The second action is an action to adjust a result of the function assembly based on the first action. A method and a non-transitory storage medium are also provided.

Abstract: An anti-corrosive coating and a preparation method therefor are provided. The method includes the following steps: (1) dispersing graphite and a modifier in water to prepare a pretreated graphite dispersion; (2) stripping and modifying the pretreated graphite dispersion obtained in step (1) to prepare a modified graphene dispersion; and (3a) mixing the modified graphene dispersion obtained in the step (2) with epoxy resin and a cationic photoinitiator, standing, carry out phase splitting, removing a water phase, further deeply removing water to obtain a graphene/epoxy resin mixture, and curing the obtained mixture to obtain the anti-corrosive coating. By means of a phase transfer method, the application of a modified graphene aqueous dispersion in resin can be realized without drying graphene first, so that uniform dispersion of modified graphene in epoxy resin can be ensured, and additionally, stacking of the modified graphene in the drying process can be avoided.

Abstract: A thermal module structure includes an aluminum base having an upper and a lower surface, at least one L-shaped copper heat pipe, a first aluminum fin assembly, a second aluminum fin assembly, and at least one copper embedding layer. The copper heat pipe includes a heat absorption section fitted on the aluminum base, and a heat dissipation section connected to the second aluminum fin assembly. The copper embedding layers are provided on the aluminum base at areas corresponding to the first aluminum fin assembly and the heat absorption section of the copper heat pipe, and on a bottom surface of the first aluminum fin assembly that is to be connected to the aluminum base. Thus, the first aluminum fin assembly and the copper heat pipe can be directly welded to the aluminum base via the copper embedding layers without the need of electroless nickel plating.