Patents by Inventor Huang Lin

Huang Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250068023
    Abstract: A liquid crystal display (LCD) of the chiral polymer stabilized alignment (C-PSA) mode, a method of its production and its use as an energy-saving display.
    Type: Application
    Filed: December 14, 2022
    Publication date: February 27, 2025
    Applicant: MERCK PATENT GmbH
    Inventors: Chia-Sheng HSIEH, Yinghua HUANG, Cheng-Jui LIN
  • Publication number: 20250067270
    Abstract: A fan noise control method includes being activated by a power-on signal to perform: controlling a rotation speed of a fan not to be greater than a first predetermined rotation speed, obtaining a power consumption of a computing device, obtaining a first temperature, wherein the first temperature is a temperature of the computing device, obtaining a second temperature, wherein the second temperature is not the temperature of the computing device, and switching from controlling the rotation speed of the fan not to be greater than the first predetermined rotation speed to controlling the rotation speed of the fan according to the first temperature when the power consumption of the computing device is greater than a first predetermined power consumption, or the second temperature is greater than a predetermined temperature.
    Type: Application
    Filed: October 26, 2023
    Publication date: February 27, 2025
    Applicants: MICRO-STAR INT’L CO.,LTD., MSI ELECTRONIC (KUN SHAN) CO.,LTD.
    Inventors: Yi-Fen LIN, Hsin-Huang TSAI, Yu-Szu LEE
  • Patent number: 12237441
    Abstract: A light-emitting device includes: a light-emitting mesa structure having a first top surface and a peripheral surface connected to the first top surface; a transparent conductive layer that is disposed on the first top surface and that has a second top surface; a first insulating structure that is at least disposed on the peripheral surface and that has a third top surface and an inner tapered surface indented from the third top surface, the inner tapered surface having an acute angle with respect to the second top surface; and a reflective layer that is disposed on the transparent conductive layer and that has a first side surface in contact with the inner tapered surface. A method for manufacturing the light-emitting device is also disclosed.
    Type: Grant
    Filed: September 1, 2021
    Date of Patent: February 25, 2025
    Assignee: XIAMEN SAN'AN OPTOELECTRONICS CO., LTD.
    Inventors: Xiaoliang Liu, Xiushan Zhu, Min Huang, Gaolin Zheng, Anhe He, Kang-Wei Peng, Su-Hui Lin
  • Publication number: 20250062153
    Abstract: A system and method for cleaning ring frames is disclosed. In one embodiment, a ring frame processing system includes: a plurality of blades for mechanically removing tapes and tape residues from surfaces of a ring frame; a plurality of wheel brushes for conditioning the surfaces of the ring frame; and a transport mechanism for transporting the ring frame.
    Type: Application
    Filed: November 4, 2024
    Publication date: February 20, 2025
    Inventors: Chien-Fa LEE, Hsu-Shui LIU, Jiun-Rong PAI, Shou-Wen KUO, Jian-Hung CHEN, M.C. LIN, C.C. CHIEN, Hsuan LEE, Boris HUANG
  • Publication number: 20250063778
    Abstract: A method includes removing a first dummy gate stack and a second dummy gate stack to form a first trench and a second trench. The first dummy gate stack and the second dummy gate stack are in a first device region and a second device region, respectively. The method further includes depositing a first gate dielectric layer and a second gate dielectric layer extending into the first trench and the second trench, respectively, forming a fluorine-containing layer comprising a first portion over the first gate dielectric layer, and a second portion over the second gate dielectric layer, removing the second portion, performing an annealing process to diffuse fluorine in the first portion into the first gate dielectric layer, and at a time after the annealing process, forming a first work-function layer and a second work-function layer over the first gate dielectric layer and the second gate dielectric layer, respectively.
    Type: Application
    Filed: October 31, 2024
    Publication date: February 20, 2025
    Inventors: Hsin-Yi Lee, Weng Chang, Hsiang-Pi Chang, Huang-Lin Chao, Chung-Liang Cheng, Chi On Chui, Kun-Yu Lee, Tzer-Min Shen, Yen-Tien Tung, Chun-I Wu
  • Publication number: 20250051593
    Abstract: An anti-corrosive coating and a preparation method therefor are provided. The method includes the following steps: (1) dispersing graphite and a modifier in water to prepare a pretreated graphite dispersion; (2) stripping and modifying the pretreated graphite dispersion obtained in step (1) to prepare a modified graphene dispersion; and (3a) mixing the modified graphene dispersion obtained in the step (2) with epoxy resin and a cationic photoinitiator, standing, carry out phase splitting, removing a water phase, further deeply removing water to obtain a graphene/epoxy resin mixture, and curing the obtained mixture to obtain the anti-corrosive coating. By means of a phase transfer method, the application of a modified graphene aqueous dispersion in resin can be realized without drying graphene first, so that uniform dispersion of modified graphene in epoxy resin can be ensured, and additionally, stacking of the modified graphene in the drying process can be avoided.
    Type: Application
    Filed: December 14, 2023
    Publication date: February 13, 2025
    Inventors: Longhui ZHENG, Huang LIN, Zixiang WENG, Jianlei WANG, Lixin WU
  • Publication number: 20250054182
    Abstract: An electronic device includes a camera assembly, a function assembly, and a controller. The camera assembly is configured to capture a first depth image of a first user and a second depth image of the first user. The controller is configured to determine a first spatial position between the first user and the camera assembly according to the first depth image, and control the function assembly to execute a first action according to the first spatial position. The controller further configured to determine a relative displacement between the first user and the camera assembly according to the first depth image and the second depth image, and control the function assembly to execute a second action according to the relative displacement. The second action is an action to adjust a result of the function assembly based on the first action. A method and a non-transitory storage medium are also provided.
    Type: Application
    Filed: December 18, 2023
    Publication date: February 13, 2025
    Inventors: CHING-HUANG LIN, Wei-Wei Qi, Chun-Ren Liu
  • Patent number: 12221461
    Abstract: The present disclosure is related to the six isomer structures (OBI-821-1990-V1A, OBI-821-1990-V1B, OBI-821-1990-V2A, OBI-821-1990-V2B, OBI-821-1858-A, and OBI-821-1858-B) of isolated OBI-821 adjuvant and the method for evaluating the quality thereof. The method of the present disclosure adopts hydrophilic interaction liquid chromatography (HILIC) and reverse phase high performance liquid chromatography (RP-HPLC) either alone or in tandem and is able to separate the isomers of OBI-821 adjuvant in the consequent chromatography. Accordingly, the quality of OBI-821 adjuvant can be further evaluated.
    Type: Grant
    Filed: March 27, 2019
    Date of Patent: February 11, 2025
    Assignee: OBI PHARMA, INC.
    Inventors: Cheng-Der Tony Yu, Yih-Huang Hsieh, Wei Han Lee, Yu Chen Lin, Nan Hsuan Wang
  • Patent number: 12215872
    Abstract: There is provided an auto detection system including a thermal detection device and a host. The host controls an indication device to indicate a prompt message or detection results according to a slope variation of voltage values or 2D distribution of temperature values detected by the thermal detection device, wherein the voltage values include the detected voltage of a single pixel or the sum of detected voltages of multiple pixels of a thermal sensor.
    Type: Grant
    Filed: July 20, 2023
    Date of Patent: February 4, 2025
    Assignee: PIXART IMAGING INC.
    Inventors: Chih-Ming Sun, Ming-Han Tsai, Chiung-Wen Lin, Po-Wei Yu, Wei-Ming Wang, Sen-Huang Huang
  • Patent number: 12215934
    Abstract: A thermal module structure includes an aluminum base having an upper and a lower surface, at least one L-shaped copper heat pipe, a first aluminum fin assembly, a second aluminum fin assembly, and at least one copper embedding layer. The copper heat pipe includes a heat absorption section fitted on the aluminum base, and a heat dissipation section connected to the second aluminum fin assembly. The copper embedding layers are provided on the aluminum base at areas corresponding to the first aluminum fin assembly and the heat absorption section of the copper heat pipe, and on a bottom surface of the first aluminum fin assembly that is to be connected to the aluminum base. Thus, the first aluminum fin assembly and the copper heat pipe can be directly welded to the aluminum base via the copper embedding layers without the need of electroless nickel plating.
    Type: Grant
    Filed: December 12, 2022
    Date of Patent: February 4, 2025
    Assignee: ASIA VITAL COMPONENTS CO., LTD.
    Inventors: Sheng-Huang Lin, Yuan-Yi Lin
  • Publication number: 20250038412
    Abstract: A semiconductor package is provided. The semiconductor package includes a first passive component module, a first antenna module, a first conductive structure and a second conductive structure. The first passive component module has a top surface, a bottom surface and a first side surface between the top surface and the bottom surface. The passive component module has a first size. The first antenna module is separated from the first passive component module and stacked on the top surface of the first passive component module. The antenna module has a second size. The first conductive structure is in contact with the top surface of the first passive component module and electrically connected to the first antenna module. The second conductive structure is in contact with the bottom surface of the first passive component module.
    Type: Application
    Filed: April 23, 2023
    Publication date: January 30, 2025
    Inventors: Nai-Chen LIU, Shih-Huang YEH, Chung-Hsin CHIANG, Wun-Jian LIN
  • Patent number: 12205596
    Abstract: Systems, methods, and devices are provided for generating and using text-to-speech (TTS) data for improved speech recognition models. A main model is trained with keyword independent baseline training data. In some instances, acoustic and language model sub-components of the main model are modified with new TTS training data. In some instances, the new TTS training is obtained from a multi-speaker neural TTS system for a keyword that is underrepresented in the baseline training data. In some instances, the new TTS training data is used for pronunciation learning and normalization of keyword dependent confidence scores in keyword spotting (KWS) applications. In some instances, the new TTS training data is used for rapid speaker adaptation in speech recognition models.
    Type: Grant
    Filed: February 10, 2023
    Date of Patent: January 21, 2025
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Guoli Ye, Yan Huang, Wenning Wei, Lei He, Eva Sharma, Jian Wu, Yao Tian, Edward C. Lin, Yifan Gong, Rui Zhao, Jinyu Li, William Maxwell Gale
  • Patent number: 12202651
    Abstract: A dust-excluding carrier for product storage comprises a housing cavity and dust-excluding isolation members. The dust-excluding isolation member comprises a first main body, the first main body is provided with a first opening; the material tray and the dust-excluding isolation member are detachably connected. The material tray comprises a second main body with a second opening. The first main body and the second main body may be snap-fitted together and apart, so the first opening is covered by the second body and the second opening covered by the first body.
    Type: Grant
    Filed: August 30, 2022
    Date of Patent: January 21, 2025
    Assignee: TRIPLE WIN TECHNOLOGY(SHENZHEN) CO.LTD.
    Inventors: Hui Xu, Ching-Huang Lin
  • Publication number: 20250014943
    Abstract: An integrated circuit (IC) chip with polish stop layers and a method of fabricating the IC chip are disclosed. The method includes forming a first IC chip having a device region and a peripheral region. Forming the first IC chip includes forming a device layer on a substrate, forming an interconnect structure on the device layer, depositing a first dielectric layer on a first portion of the interconnect structure in the peripheral region, depositing a second dielectric layer on the first dielectric layer and on a second portion of the interconnect structure in the device region, and performing a polishing process on the second dielectric layer to substantially coplanarize a top surface of the second dielectric layer with a top surface of the first dielectric layer. The method further includes performing a bonding process on the second dielectric layer to bond a second IC chip to the first IC chip.
    Type: Application
    Filed: July 7, 2023
    Publication date: January 9, 2025
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Zheng Yong LIANG, Wei-Ting YEH, I-Han HUANG, Chen-Hao WU, An-Hsuan LEE, Huang-Lin CHAO, Yu-Yun PENG, Keng-Chu LIN
  • Patent number: 12176217
    Abstract: The present disclosure provides a method for manufacturing a semiconductor. The method includes: forming a metal oxide layer over a gate structure over a substrate; forming a dielectric layer over the metal oxide layer; forming a metal layer over the metal oxide layer; and performing a chemical mechanical polish (CMP) operation to remove a portion of the dielectric layer and a portion of the metal layer, the CMP operation stopping at the metal oxide layer, wherein a slurry used in the CMP operation includes a ceria compound. The present disclosure also provides a method for planarizing a metal-dielectric surface.
    Type: Grant
    Filed: May 17, 2023
    Date of Patent: December 24, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chun-Hung Liao, Chung-Wei Hsu, Tsung-Ling Tsai, Chen-Hao Wu, An-Hsuan Lee, Shen-Nan Lee, Teng-Chun Tsai, Huang-Lin Chao
  • Publication number: 20240418571
    Abstract: An apparatus for non-contact measuring temperature includes a stand, for securing a vapor chamber, wherein the vapor chamber comprises a condenser area and an evaporator area, wherein the evaporator area comprises a heating spot; a continuous-wave laser device, facing the stand, for irradiating the heating spot by providing an infrared laser beam, wherein the infrared laser beam comprises a first infrared wavelength range; a switch device, controlling an irradiating cycle of the infrared laser beam, wherein the irradiating cycle comprises a irradiating time-interval and a non-irradiating time-interval; a first infrared sensor, facing the stand, for collecting a first thermal radiation data of the heating spot in a second infrared wavelength range; a data processing unit, only transferring the first thermal radiation data in the non-irradiating time-interval into a first temperature, wherein the irradiating time-interval is longer than the non-irradiating time-interval.
    Type: Application
    Filed: June 16, 2023
    Publication date: December 19, 2024
    Inventors: KUANG-YU HSU, Chiao-Jung Tien, Yi-Jing Chu, MING-HUANG LIN, Ming-Hsien Hsiao
  • Patent number: 12166074
    Abstract: A method includes removing a first dummy gate stack and a second dummy gate stack to form a first trench and a second trench. The first dummy gate stack and the second dummy gate stack are in a first device region and a second device region, respectively. The method further includes depositing a first gate dielectric layer and a second gate dielectric layer extending into the first trench and the second trench, respectively, forming a fluorine-containing layer comprising a first portion over the first gate dielectric layer, and a second portion over the second gate dielectric layer, removing the second portion, performing an annealing process to diffuse fluorine in the first portion into the first gate dielectric layer, and at a time after the annealing process, forming a first work-function layer and a second work-function layer over the first gate dielectric layer and the second gate dielectric layer, respectively.
    Type: Grant
    Filed: February 21, 2022
    Date of Patent: December 10, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsin-Yi Lee, Weng Chang, Hsiang-Pi Chang, Huang-Lin Chao, Chung-Liang Cheng, Chi On Chui, Kun-Yu Lee, Tzer-Min Shen, Yen-Tien Tung, Chun-I Wu
  • Publication number: 20240405093
    Abstract: The present disclosure describes forming a crystalline high-k dielectric layer at a reduced crystallization temperature in a semiconductor device. The method includes forming a channel structure on a substrate, forming an interfacial layer on the channel structure, forming a first high-k dielectric layer on the interfacial layer, forming dipoles in the first high-k dielectric layer with a dopant, and forming a second high-k dielectric layer on the first high-k dielectric layer. The dopant includes a first metal element. The second high-k dielectric layer includes a second metal element different from the first metal element.
    Type: Application
    Filed: June 2, 2023
    Publication date: December 5, 2024
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shen-Yang LEE, Hsiang-Pi CHANG, Huang-Lin CHAO, Pinyen LIN
  • Publication number: 20240395855
    Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, first and second fin structures formed over the substrate, and an isolation structure between the first and second fin structures. The isolation structure can include a lower portion and an upper portion. The lower portion of the isolation structure can include a metal-free dielectric material. The upper portion of the isolation structure can include a metallic element and silicon.
    Type: Application
    Filed: July 30, 2024
    Publication date: November 28, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Pinyen LIN, Chin-Hsiang LIN, Huang-Lin CHAO
  • Publication number: 20240395564
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a base portion and a fin portion over the base portion. The semiconductor device structure includes an isolation layer over the base portion and surrounding the fin portion. The isolation layer includes fluorine, and a first concentration of fluorine in the isolation layer increases toward a top surface of the isolation layer. The semiconductor device structure includes a gate stack over the isolation layer and wrapping around the fin portion.
    Type: Application
    Filed: July 31, 2024
    Publication date: November 28, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: I-Ming CHANG, Chih-Cheng LIN, Chi-Ying WU, Wei-Ming YOU, Ziwei FANG, Huang-Lin CHAO