Abstract: The invention relates to the use of a compound of Formula (I) as described herein and its effective dose in the prevention and/or treatment of fibrosis diseases. The compound can effectively prevent and/or treat a fibrosis disease without cytotoxicity or genotoxicity.

Abstract: A media management system including an application layer, a system layer, and a solid state drive (SSD) storage layer. The application layer includes a media data analytics application configured to assign a classification code to a data file. The system layer is in communication with the application layer. The system layer includes a file system configured to issue a write command to a SSD controller. The write command includes the classification code of the data file. The SSD storage layer includes the SSD controller and erasable blocks. The SSD controller is configured to write the data file to one of the erasable blocks based on the classification code of the data file in the write command. In an embodiment, the SSD controller is configured to write the data file to one of the erasable blocks storing other data files also having the classification code.

Abstract: An integrated circuit device includes a gate stack disposed over a substrate. A first L-shaped spacer is disposed along a first sidewall of the gate stack and a second L-shaped spacer is disposed along a second sidewall of the gate stack. The first L-shaped spacer and the second L-shaped spacer include silicon and carbon. A first source/drain epitaxy region and a second source/drain epitaxy region are disposed over the substrate. The gate stack is disposed between the first source/drain epitaxy region and the second source/drain epitaxy region. An interlevel dielectric (ILD) layer disposed over the substrate. The ILD layer is disposed between the first source/drain epitaxy region and a portion of the first L-shaped spacer disposed along the first sidewall of the gate stack and between the second source/drain epitaxy region and a portion of the second L-shaped spacer disposed along the second sidewall of the gate stack.

Abstract: A manufacturing method of housing structure of electronic device is provided. The manufacturing method includes stacking a first structural layer, a painting layer, and a second structural layer, wherein the painting layer is located between the first and the second structural layers. The layer stacked after the painting layer washes and squeezes at least a portion of the flowing painting layer to form a random texture pattern.

Abstract: A trimming method is provided. The trimming method includes the following steps. A first wafer including a substrate and a device layer over a first side of the substrate is provided. The first wafer is bonded to a second wafer with the first side of the substrate facing toward the second wafer. An edge trimming process is performed to remove a trimmed portion of the substrate from a second side opposite to the first side vertically downward toward the first side in a first direction along a perimeter of the substrate, wherein the edge trimming process results in the substrate having a flange pattern laterally protruding from the device layer and laterally surrounding an untrimmed portion of the substrate along a second direction perpendicular to the first direction.

Abstract: A method for forming a semiconductor package is provided. The method includes forming a first alignment mark in a first substrate of a first wafer and forming a first bonding structure over the first substrate. The method also includes forming a second bonding structure over a second substrate of a second wafer and trimming the second substrate, so that a first width of the first substrate is greater than a second width of the second substrate. The method further includes attaching the second wafer to the first wafer via the first bonding structure and the second bonding structure, thinning the second wafer until a through-substrate via in the second substrate is exposed, and performing a photolithography process on the second wafer using the first alignment mark.

Abstract: A semiconductor structure includes an interfacial layer disposed over a semiconductor channel region, a metal oxide layer disposed over the interfacial layer, a high-k gate dielectric layer disposed over the metal oxide layer, a metal halide layer disposed over the high-k gate dielectric layer, and a metal gate electrode disposed over the high-k gate dielectric layer. The metal oxide layer and the interfacial layer form a dipole moment. The metal oxide layer includes a first metal. The metal halide layer includes a second metal different from the first metal.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first fin, a second fin and a third fin therebetween. A first insulating structure includes a first insulating layer formed between the first and third fins, a capping structure covering the first insulating layer, a first insulating liner covering sidewall surfaces of the first insulating layer and the capping structure and a bottom surface of the first insulating layer, and a second insulating liner formed between the first insulating liner and the first fin and between the first insulating liner and the third fin. The second insulating structure includes a second insulating layer formed between the second fin and the third fin and a third insulating liner formed between the second insulating layer and the second fin and between the second insulating layer and the third fin.

Abstract: A method for tuning a threshold voltage of a transistor is disclosed. A channel layer is formed over a substrate. An interfacial layer is formed over and surrounds the channel layer. A gate dielectric layer is formed over and surrounds the interfacial layer. A dipole layer is formed over and wraps around the gate dielectric layer by performing a cyclic deposition etch process, and the dipole layer includes dipole metal elements and has a substantially uniform thickness. A thermal drive-in process is performed to drive the dipole metal elements in the dipole layer into the gate dielectric layer to form an interfacial dipole surface, and then the dipole layer is removed.

Abstract: A thermal module includes a radiating fin unit having a plurality of superposed radiating fin assemblies, and a plurality of groups of heat pipes. The heat pipes respectively have a heat absorbing section and a heat dissipating section formed at two opposite ends thereof. The heat absorbing sections in each heat pipe group is in contact with a heat source, and the heat dissipating sections in the same heat pipe group is sandwiched between two adjacent ones of the radiating fin assemblies. The thermal module is characterized in that the heat dissipating sections are horizontally extended through the radiating fin assemblies from one of two opposite shorter sides to another shorter side along two parallel longer sides thereof, such that the heat dissipating sections not only have a maximum contact area with the radiating fin assemblies, but also give the radiating fin unit an enhanced structural strength.

Abstract: A radio frequency (RF) system and a communication device are provided. The RF system includes a flexible circuit board, a first antenna module and a RF module. The flexible circuit board has a first surface and a second surface, and the first surface and the second surface are located at different sides of the flexible circuit board. The first antenna module is disposed on the first surface of the flexible circuit board. The first antenna module includes a first carrier, a first antenna element disposed on or in the first carrier, and a first conductive member between the first carrier and the flexible circuit board. The RF module is disposed on the second surface of the flexible circuit board and electrically connected to the first antenna module.

Abstract: The structure of a semiconductor device with different gate structures configured to provide ultra-low threshold voltages and a method of fabricating the semiconductor device are disclosed. The method includes forming first and second nanostructured channel regions in first and second nanostructured layers, respectively, and forming first and second gate-all-around (GAA) structures surrounding the first and second nanostructured channel regions, respectively. The forming the first and second GAA structures includes selectively forming an Al-based n-type work function metal layer and a Si-based capping layer on the first nanostructured channel regions, depositing a bi-layer of Al-free p-type work function metal layers on the first and second nanostructured channel regions, depositing a fluorine blocking layer on the bi-layer of Al-free p-type work function layers, and depositing a gate metal fill layer on the fluorine blocking layer.

Abstract: An antenna structure is provided. The antenna structure includes a first metal layer and a second metal layer disposed over the first metal layer. The second metal layer forms a first antenna resonating element operating at a first band and has a first opening. The antenna structure also includes a third metal layer disposed over the second metal layer. The third metal layer forms a second antenna resonating element operating at a second band, which is different from the first band. The antenna structure further includes a first transmission line extending from the first metal layer to the second metal layer and a second transmission line extending from the first metal layer through the first opening to the third metal layer.

Abstract: A ferroelectric memory cell (FeRAM) is disclosed that includes an active device (e.g., a transistor) and a passive device (e.g., a ferroelectric capacitor) integrated in a substrate. The transistor and its gate contacts are formed on a front side of the substrate. A carrier wafer can be bonded to the active device to allow the active device to be inverted so that the passive device and associated contacts can be electrically coupled from a back side of the substrate.

Abstract: An antenna module is provided. The antenna module includes a dielectric substrate, a radio frequency integrated circuit (RFIC) and a first number of first antennas. The radio frequency integrated circuit (RFIC) is disposed on the dielectric substrate, wherein the RFIC comprises a single first antenna port group and second antenna port groups to receive or transmit signals. The first number of first antennas is arranged in a first row on the dielectric substrate, wherein at least two of the first antennas are connected to the first antenna port group of the RFIC.

Abstract: Aspects of the present disclosure provide a method for training a predictor that predicts performance of a plurality of machine learning (ML) models on platforms. For example, the method can include converting each of the ML models into a plurality of instructions or the instructions and a plurality of intermediate representations (IRs). The method can also include simulating execution of the instructions corresponding to each of the ML models on a platform and generating instruction performance reports. Each of the instruction performance reports can be associated with performance of the instructions corresponding to one of the ML models that are executed on the platform. The method can also include training the predictor with the instructions or the IRs as learning features and the instruction performance reports as learning labels, compiling the predictor into a library file, and storing the library file in a storage device.

Abstract: A method includes forming a transistor, which includes forming a dummy gate stack over a semiconductor region, and forming an Inter-Layer Dielectric (ILD). The dummy gate stack is in the ILD, and the ILD covers a source/drain region in the semiconductor region. The method further includes removing the dummy gate stack to form a trench in the first ILD, forming a low-k gate spacer in the trench, forming a replacement gate dielectric extending into the trench, forming a metal layer to fill the trench, and performing a planarization to remove excess portions of the replacement gate dielectric and the metal layer to form a gate dielectric and a metal gate, respectively. A source region and a drain region are then formed on opposite sides of the metal gate.

Abstract: Exemplary methods of semiconductor processing may include forming a layer of silicon-containing material on a semiconductor substrate. The methods may include performing a post-formation treatment on the layer of silicon-containing material to yield a treated layer of silicon-containing material. The methods may include contacting the treated layer of silicon-containing material with an adhesion agent. The methods may include forming a layer of a resist material on the treated layer of silicon-containing material.

Abstract: The present disclosure provides antibodies and antibody fragments thereof that bind to human TNFR2. The disclosed antibodies, inhibit the TNF-TNFR2 signaling axis and enhance cytokine secretion in T effector cells and are therefore useful for the treatment of cancer, either alone or in combination with other agents.

Abstract: An antenna and an electronic device including the antenna are provided. The antenna includes a pair of radiators, a pair of feeding elements, first and second feeding ports. The radiators are located beside a geometric origin and separated from each other. The geometric origin is located between the radiators. The feeding elements are located below the pair of radiators and are configured to feed signals to the radiators. The pair of feeding elements includes a first feeding element and a second feeding element that are separated from each other. The first feeding element has a first geometric configuration. The second feeding element has a second geometric configuration that is asymmetric to the first geometric configuration. The first feeding port is electrically connected to the first feeding element. The second feeding port is separated from the first feeding port and electrically connected to the second feeding element.