Abstract: A semiconductor structure includes an interfacial layer disposed over a semiconductor layer, a high-k gate dielectric layer disposed over the interfacial layer, where the high-k gate dielectric layer includes a first metal, a metal oxide layer disposed between the high-k gate dielectric layer and the interfacial layer, where the metal oxide layer is configured to form a dipole moment with the interfacial layer, and a metal gate stack disposed over the high-k gate dielectric layer. The metal oxide layer includes a second metal different from the first metal, and a concentration of the second metal decreases from a top surface of the high-k gate dielectric layer to the interface between the high-k gate dielectric layer and the interfacial layer.

Abstract: A semiconductor structure includes a plurality of semiconductor devices, each of which includes at least one channel layer, at least one interfacial layer, a gate dielectric layer, a gate electrode, and dipole elements. The at least one interfacial layer is disposed on the at least one channel layer. The gate dielectric layer is disposed over the at least one interfacial layer such that the at least one channel layer is separated from the gate dielectric layer through the at least one interfacial layer. The gate electrode is disposed on the gate dielectric layer. The dipole elements are present in the interfacial layer of at least one of the semiconductor devices in a predetermined amount such that the at least one of the semiconductor devices has a tunability of threshold voltage from that of the other of the semiconductor devices. Methods for manufacturing the semiconductor structure are also disclosed.

Abstract: A semiconductor structure includes a substrate including a first region and a second region, a first channel layer disposed in the first region and a second channel layer disposed in the second region, a first dielectric layer disposed on the first channel layer and a second dielectric layer disposed on the second channel layer, and a first gate electrode disposed on the first dielectric layer and a second gate electrode disposed on the second dielectric layer. The first channel layer in the first region includes Ge compound of a first Ge concentration, the second channel layer in the second region includes Ge compound of a second Ge concentration. The first Ge concentration in the first channel layer is greater than the second Ge concentration in the second channel layer.

Abstract: Embodiments of the present disclosure provide a method of forming N-type and P-type source/drain features using one patterned mask and one self-aligned mask to increase windows of error tolerance and provide flexibilities for source/drain features of various shapes and/or volumes. In some embodiments, after forming a first type of source/drain features, a self-aligned mask layer is formed over the first type of source/drain features without using photolithography process, thus, avoid damaging the first type of source/drain features in the patterning process.

Abstract: The invention relates to the use of a compound of Formula (I) as described herein and its effective dose in the prevention and/or treatment of fibrosis diseases. The compound can effectively prevent and/or treat a fibrosis disease without cytotoxicity or genotoxicity.

Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a first and second transistors arranged over a substrate. The first transistor includes first channel structures extending between first and second source/drain regions. A first gate electrode is arranged between the first channel structures, and a first protection layer is arranged over a topmost one of the first channel structures. The second transistor includes second channel structures extending between the second source/drain region and a third source/drain region. A second gate electrode is arranged between the second channel structures, and a second protection layer is arranged over a topmost one of the second channel structures. The integrated chip further includes a first interconnect structure arranged between the substrate and the first and second channel structures, and a contact plug structure coupled to the second source/drain region and arranged above the first and second gate electrodes.

Abstract: A method is provided for forming a contact plug by bottom-up metal growth. In one step, a substrate is etched to form a contact hole that exposes a silicon-containing feature in the substrate. In one step, a silicide layer is formed on the silicon-containing feature. In one step, a metal seed layer is formed over the silicide layer. In one step, a metal contact layer is deposited over the metal seed layer to form the contact plug in the contact hole.

Abstract: A method of forming a semiconductor device includes forming a transistor comprising a gate stack on a semiconductor substrate by, at least, forming a first dielectric layer on the semiconductor substrate, forming a dipole layer on the dielectric layer; forming a second dielectric layer on the dipole layer, forming a conductive work function layer on the second dielectric layer, forming a gate electrode layer on the conductive work function layer. The method also includes varying a distance between dipole inducing elements in the dipole layer and a surface of the semiconductor substrate by tuning a thickness of the first dielectric layer to adjust a threshold voltage of the transistor.

Abstract: A method of fabricating a semiconductor device with superlattice structures on a substrate with an embedded isolation structure is disclosed. The method includes forming an etch stop layer on a substrate, forming a superlattice structure on the etch stop layer, depositing an isolation layer on the superlattice structure, depositing a semiconductor layer on the isolation layer, forming a bi-layer isolation structure on the semiconductor layer, removing the substrate and the etch stop layer, etching the superlattice structure, the isolation layer, the semiconductor layer, and the bi-layer isolation structure to form a fin structure, and forming a gate-all-around structure on the fin structure.

Abstract: A method of fabricating a semiconductor device with superlattice structures on a substrate with an embedded isolation structure is disclosed. The method includes forming an etch stop layer on a substrate, forming a superlattice structure on the etch stop layer, depositing an isolation layer on the superlattice structure, depositing a semiconductor layer on the isolation layer, forming a bi-layer isolation structure on the semiconductor layer, removing the substrate and the etch stop layer, etching the superlattice structure, the isolation layer, the semiconductor layer, and the bi-layer isolation structure to form a fin structure, and forming a gate-all-around structure on the fin structure.

Abstract: A heat sink device, comprising a body, at least a heat pipe, and a base. The body has a first side and a second side onto which a heat source is attached. The heat pipe has a heat-absorbing portion and a heat-dissipating portion. The heat-absorbing portion is attached to the first side, while the heat-dissipating portion is away from the heat-absorbing portion, so that the heat generated by the heat source is absorbed by the heat-absorbing portion and transferred to the distal end of the heat-dissipating portion. The base is disposed on the heat pipe and above the body.

Abstract: The present disclosure describes a method and an apparatus that can enhance the slurry oxidizability for a chemical mechanical polishing (CMP) process. The method can include securing a substrate onto a carrier of a polishing system. The method can further include dispensing, via a feeder of the polishing system, a first slurry towards a polishing pad of the polishing system. The method can further include forming a second slurry by enhancing an oxidizability of the first slurry, and performing a polishing process, with the second slurry, on the substrate.

Abstract: A semiconductor device structure includes a gate structure formed over a substrate. The semiconductor device structure also includes a source/drain structure formed beside the gate structure. The semiconductor device structure further includes a contact structure formed over the source/drain structure. The semiconductor device structure also includes a first cap layer formed over the contact structure. The semiconductor device structure further includes a dielectric structure extending from a top surface of the first cap layer into the contact structure. The dielectric structure and the source/drain structure are separated by the contact structure.

Abstract: A detecting method for a behavior disorder event during rapid-eye-movement sleep is provided. The detecting method includes: collecting a heart rate value and a motion value of a user per epoch within a time period; generating a plurality of corresponding sleep condition values by using the motion values, to distinguish epochs into an awake period and a sleep period; transforming the motion values corresponding to the sleep period into a score according to a predetermined rule, to generate a plurality of sleep depth scores, and distinguishing the sleep period into a light sleep period and a deep sleep period by using the sleep depth scores; grouping the heart rate values corresponding to the deep sleep period as a high heart rate group and a low heart rate group; and determining, when the motion values corresponding to the high heart rate group satisfy a condition, that a behavior disorder event happens.

Abstract: A multifocal lens is revealed. The multifocal lens includes a lens with an incident curved surface and an emergent curved surface arranged opposite to each other. The incident curved surface consists of a plurality of incident areas disposed circularly around an axis of the lens and each of the incident areas is formed by a plurality of incident surfaces. The two adjacent incident surfaces belonged to the same incident area are not in contact with each other optimally and the incident areas have respective focal points correspondingly. Thereby light with different properties emitted from a plurality of light sources corresponding to the focal points of the respective incident areas is passed through the multifocal lens and projected to have preset light patterns for warning or decoration.

Abstract: In-situ defect count detection in post chemical mechanical polishing (post-CMP) is provided. Post-CMP is performed, in-situ and according to a recipe, on a surface of a semiconductor wafer within a post-CMP chamber. A light signal is scanned over a target area of the surface of the semiconductor wafer and a reflected light signal reflected from the target area is detected. A defect count of defects present in the target area is determined based on the reflected light signal reflected from the target area.

Abstract: The present disclosure provides a method for manufacturing a semiconductor. The method includes: forming a metal oxide layer over a gate structure over a substrate; forming a dielectric layer over the metal oxide layer; forming a metal layer over the metal oxide layer; and performing a chemical mechanical polish (CMP) operation to remove a portion of the dielectric layer and a portion of the metal layer, the CMP operation stopping at the metal oxide layer, wherein a slurry used in the CMP operation includes a ceria compound. The present disclosure also provides a method for planarizing a metal-dielectric surface.

Abstract: The present disclosure describes a method and an apparatus that can enhance the slurry oxidizability for a chemical mechanical polishing (CMP) process. The method can include securing a substrate onto a carrier of a polishing system. The method can further include dispensing, via a feeder of the polishing system, a first slurry towards a polishing pad of the polishing system. The method can further include forming a second slurry by enhancing an oxidizability of the first slurry, and performing a polishing process, with the second slurry, on the substrate.

Abstract: A method includes forming a dummy gate stack over a semiconductor region, forming a source/drain region on a side of the dummy gate stack, removing the dummy gate stack to form a trench, forming a gate dielectric layer extending into the trench and on the semiconductor region, and depositing a fist work-function layer over the gate dielectric layer. The work-function layer comprises a metal selected from the group consisting of ruthenium, molybdenum, and combinations thereof. The method further includes depositing a conductive filling layer over the first work-function layer, and performing a planarization process to remove excess portions of the conductive filling layer, the first work-function layer, and the gate dielectric layer to form a gate stack.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first fin, a second fin and a third fin therebetween. A first insulating structure includes a first insulating layer formed between the first and third fins, a capping structure covering the first insulating layer, a first insulating liner covering sidewall surfaces of the first insulating layer and the capping structure and a bottom surface of the first insulating layer, and a second insulating liner formed between the first insulating liner and the first fin and between the first insulating liner and the third fin. The second insulating structure includes a second insulating layer formed between the second fin and the third fin and a third insulating liner formed between the second insulating layer and the second fin and between the second insulating layer and the third fin.