Abstract: A method in a computer-aided design system for generating a functional design model of an integrated circuitry structure including generating a functional representation of at least first and second regions of the integrated circuitry structure, generating a functional representation of an optical layer comprising optical waveguides, and generating a functional representation of a heat-conductive material for transferring heat from at least the second region through the optical layer to a heat sink.

Abstract: A computer system includes a processor, and the processor includes at least one interface for communicating with an electronic component. Each of the at least one interface has a set of interface settings. The computer system further includes a memory containing machine executable instructions. Execution of the instructions causes the processor to: monitor communications traffic on the at least one interface; store, eye distribution data acquired during the monitoring of the communications traffic in a database; compare the eye distribution data to a set of predetermined criteria; and generate a set of updated interface settings if the eye distribution does not satisfy the set of predetermined criteria.

Abstract: An integrated circuit coupling device includes an integrated circuit package; and an optical data transmission medium connected to the integrated circuit package, and comprising a movable coolant, adapted to remove heat from the integrated circuit package, in operation.

Abstract: Transferring data from a first clock domain to a second clock domain, wherein the second clock domain has a fixed clock frequency, and the first clock domain has a variable clock frequency. The first clock domain and the second clock domain operate in a synchronous mode when the variable clock frequency is equal to the fixed clock frequency, and in an asynchronous mode when the variable frequency is lower than the fixed frequency. A first buffer and a second buffer are used for a data transfer from the first clock domain to the second clock domain. The second clock domain comprises a multiplexor connected to the first buffer and the second buffer. The multiplexor forwards data from the first buffer further into the second clock domain in the synchronous mode and from the second buffer into the second clock domain in the asynchronous mode.

Abstract: A method is provided for determining a power noise histogram of a computer system. The computer system includes a skitter circuit with multiple skitter bins, each skitter bin of the multiple skitter bins being connected to a signal line at one or more clock cycles. The method includes: connecting each skitter bin to an individual counter circuit; and incrementing a counter when the respective skitter bin is enabled.

Abstract: An integrated circuit coupling device includes an integrated circuit package with N integrated circuit layers (L1-LN) arranged as a 3D stack; and a data transmission medium with n data transmission layers (l1-ln), wherein n?1 and N?2, and wherein the N integrated circuit layers are electrically connectable to the n data transmission layers.

Abstract: A switchgear unit switches high DC voltages, particularly for interrupting of direct current between a direct current source and an electrical device. The switchgear unit contains two connections which project from a housing and which are electrically conductively coupled by a conductor path, a contact system which is arranged between the first and second connections and an isolating apparatus that can be tripped by a thermal fuse. The thermal fuse contains a melting location which is arranged in the conductor path and which is connected first to the contact system and second via a moving conductor section to the first connection. The isolating apparatus is tripped and the connection between the conductor section and the contact system is broken at the melting location when an arc produced when the contact system is opened has caused the melting temperature of the melting location to be reached or exceeded.

Abstract: A technique for routing signal traces in an electronic package design includes extracting near-end and far-end crosstalk values for traces and vias from a model of the electronic package design. The extracted values are then length-normalized and the normalized values are allocated to coupling factors of a cost-function. A first bus routing for the electronic package design is performed to provide a first routed design. Length segments from the first routed design are extracted and inserted in the cost-function. Crosstalk for each bus net is accumulated using the cost-function. In response to the accumulated crosstalk being less than a determined limit, the first routed design is saved. In response to the accumulated crosstalk being greater than the determined limit, an additional bus routing for the electronic package design is performed.

Abstract: Transferring data from a first clock domain to a second clock domain, wherein the second clock domain has a fixed clock frequency, and the first clock domain has a variable clock frequency. The first clock domain and the second clock domain operate in a synchronous mode when the variable clock frequency is equal to the fixed clock frequency, and in an asynchronous mode when the variable frequency is lower than the fixed frequency. A first buffer and a second buffer are used for a data transfer from the first clock domain to the second clock domain. The second clock domain comprises a multiplexor connected to the first buffer and the second buffer. The multiplexor forwards data from the first buffer further into the second clock domain in the synchronous mode and from the second buffer into the second clock domain in the asynchronous mode.

Abstract: A method in a computer-aided design system for generating a functional design model of an integrated circuitry structure including generating a functional representation of at least first and second regions of the integrated circuitry structure, generating a functional representation of an optical layer comprising optical waveguides, and generating a functional representation of a heat-conductive material for transferring heat from at least the second region through the optical layer to a heat sink.

Abstract: A mechanism is provided for optimizing semiconductor packing in a three-dimensional (3D) very-large-scale integration (VLSI) device. The 3D VLSI device comprises a processor layer coupled, via a first set of coupling devices, to at least one signaling and input/output (I/O) layer. The 3D VLSI device further comprises a power delivery layer coupled, via a second set of coupling devices, to the processor layer. In the 3D VLSI device the power delivery layer is dedicated to only delivering power and does not provide data communication signals to the elements of the three-dimensional VLSI device, and the at least one signaling and input/output (I/O) layer is dedicated to only transmitting the data communication signals to and receiving the data communications signals from the processor layer and does not provide power to the elements of the processor layer.

Abstract: A mechanism is provided for a thermal power plane that delivers power and constitutes minimal thermal resistance. The mechanism comprises a processor layer coupled, via a first set of coupling devices, to a signaling and input/output (I/O) layer and a power delivery layer coupled, via a second set of coupling devices, to the processor layer. In the mechanism, the power delivery layer is dedicated to only delivering power and does not provide data communication signals to the elements of the mechanism. In the mechanism, the power delivery layer comprises a plurality of conductors, a plurality of insulating materials, one or more ground planes, and a plurality of through laminate vias. In the mechanism, the signaling and input/output (I/O) layer is dedicated to only transmitting the data communication signals to and receiving the data communications signals from the processor layer and does not provide power to the elements of the processor layer.

Abstract: A mechanism is provided for integrated power delivery and distribution via a heat sink. The mechanism comprises a processor layer coupled to a signaling and input/output (I/O) layer via a first set of coupling devices and a heat sink coupled to the processor layer via a second set of coupling devices. In the mechanism, the heat sink comprises a plurality of grooves on one face, where each groove provides either a path for power or a path for ground to be delivered to the processor layer. In the mechanism, the heat sink is dedicated to only delivering power and does not provide data communication signals to the elements of the mechanism and the signaling and I/O layer is dedicated to only transmitting the data communication signals to and receiving the data communications signals from the processor layer and does not provide power to the elements of the processor layer.

Abstract: A mechanism is provided for optimizing semiconductor packing in a three-dimensional (3D) very-large-scale integration (VLSI) device. The 3D VLSI device comprises a processor layer coupled, via a first set of coupling devices, to at least one signaling and input/output (I/O) layer. The 3D VLSI device further comprises a power delivery layer coupled, via a second set of coupling devices, to the processor layer. In the 3D VLSI device the power delivery layer is dedicated to only delivering power and does not provide data communication signals to the elements of the three-dimensional VLSI device, and the at least one signaling and input/output (I/O) layer is dedicated to only transmitting the data communication signals to and receiving the data communications signals from the processor layer and does not provide power to the elements of the processor layer.

Abstract: A computer system includes a processor, and the processor includes at least one interface for communicating with an electronic component. Each of the at least one interface has a set of interface settings. The computer system further includes a memory containing machine executable instructions. Execution of the instructions causes the processor to: monitor communications traffic on the at least one interface; store, eye distribution data acquired during the monitoring of the communications traffic in a database; compare the eye distribution data to a set of predetermined criteria; and generate a set of updated interface settings if the eye distribution does not satisfy the set of predetermined criteria.

Abstract: A switchgear unit switches high DC voltages, particularly for interrupting of direct current between a direct current source and an electrical device. The switchgear unit contains two connections which project from a housing and which are electrically conductively coupled by a conductor path, a contact system which is arranged between the first and second connections and an isolating apparatus that can be tripped by a thermal fuse. The thermal fuse contains a melting location which is arranged in the conductor path and which is connected first to the contact system and second via a moving conductor section to the first connection. The isolating apparatus is tripped and the connection between the conductor section and the contact system is broken at the melting location when an arc produced when the contact system is opened has caused the melting temperature of the melting location to be reached or exceeded.

Abstract: A mechanism is provided for optimizing semiconductor packing in a three-dimensional (3D) very-large-scale integration (VLSI) device. The 3D VLSI device comprises a processor layer coupled, via a first set of coupling devices, to at least one signaling and input/output (I/O) layer. The 3D VLSI device further comprises a power delivery layer coupled, via a second set of coupling devices, to the processor layer. In the 3D VLSI device the power delivery layer is dedicated to only delivering power and does not provide data communication signals to the elements of the three-dimensional VLSI device, and the at least one signaling and input/output (I/O) layer is dedicated to only transmitting the data communication signals to and receiving the data communications signals from the processor layer and does not provide power to the elements of the processor layer.

Abstract: An integrated circuitry structure includes at least first and second regions. An optical layer includes optical waveguides. A heat-conductive material transfers heat from at least the second region through the optical layer to a heat sink.

Abstract: An integrated circuit coupling device includes an integrated circuit package; and an optical data transmission medium connected to the integrated circuit package, and comprising a movable coolant, adapted to remove heat from the integrated circuit package, in operation.

Abstract: An integrated circuit coupling device includes an integrated circuit package with N integrated circuit layers (L1-LN) arranged as a 3D stack; and a data transmission medium with n data transmission layers (l1-ln), wherein n?1 and N?2, and wherein the N integrated circuit layers are electrically connectable to the n data transmission layers.