Patents by Inventor Hui Lin

Hui Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • MEMORY CIRCUIT WITH SENSE AMPLIFIER CALIBRATION MECHANISM
    Publication number: 20230267973
    Abstract: According to an exemplary embodiments, the disclosure is directed to a memory circuit which includes not limited to a first half sense amplifier circuit connected to a first plurality of memory cells through a first bit line and configured to receive a unit of analog electrical signal from each of the first plurality of memory cells and to generate a first half sense amplifier output signal corresponding to the first bit line based on a first gain of the half sense amplifier and an accumulation of the units of analog signals, a locking code register circuit configured to receive a locking data and to generate a digital locking sequence, and a source selector circuit configured to receive the digital locking sequence and to generate a first adjustment signal to adjust the first half sense amplifier output signal corresponding to the first bit line by adjusting the first gain.
    Type: Application
    Filed: December 5, 2022
    Publication date: August 24, 2023
    Applicant: Industrial Technology Research Institute
    Inventors: Chih-Sheng Lin, Fu-Cheng Tsai, Tuo-Hung Hou, Jian-Wei Su, Yu-Hui Lin, Chih-Ming Lai
  • Light-emitting diode, and light-emitting diode package, light-emitting diode module and display device including the same
    Patent number: 11735696
    Abstract: A light-emitting diode (LED) includes a light-transmissive substrate which has a first surface, an epitaxial structure which is disposed on the first surface, a first insulation layer, and a second insulation layer. The epitaxial structure has an upper surface opposite to the first surface, and a side wall interconnecting the upper surface and the first surface. The first insulation layer covers the side wall and the upper surface. The second insulation layer covers a portion of the first surface that is not covered by the epitaxial structure and the first insulation layer, and has a light transmittance greater than that of the first insulation layer. An LED package, an LED module, and a display device including the LEDs are also disclosed.
    Type: Grant
    Filed: October 16, 2020
    Date of Patent: August 22, 2023
    Assignee: XIAMEN SAN'AN OPTOELECTRONICS CO. LTD.
    Inventors: Feng Wang, Zhanggen Xia, Yu Zhan, En-song Nie, Anhe He, Kang-Wei Peng, Su-Hui Lin
  • Magnetoresistive random access memory (MRAM) device
    Patent number: 11737370
    Abstract: A semiconductor device includes a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate, a passivation layer on the first MTJ and the second MTJ, and an ultra low-k (ULK) dielectric layer on the passivation layer. Preferably, a top surface of the passivation layer between the first MTJ and the second MTJ is lower than a top surface of the passivation layer directly on top of the first MTJ.
    Type: Grant
    Filed: January 4, 2021
    Date of Patent: August 22, 2023
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Tai-Cheng Hou, Wei-Xin Gao, Fu-Yu Tsai, Chin-Yang Hsieh, Chen-Yi Weng, Jing-Yin Jhang, Bin-Siang Tsai, Kun-Ju Li, Chih-Yueh Li, Chia-Lin Lu, Chun-Lung Chen, Kun-Yuan Liao, Yu-Tsung Lai, Wei-Hao Huang
  • Control method of flash memory controller and associated flash memory controller and storage device
    Patent number: 11733895
    Abstract: The present invention provides a control method of the flash memory controller. In the control method, after receiving a deallocate command from a host device, the flash memory controller will update a valid page count table, a detailed valid page count table and/or a zone valid page count table according to deallocate command, for the flash memory controller to efficiently and quickly determine if any one of the zones does not have any valid data, so that the flash memory controller can recommend the host device to send a reset command to reset the zone.
    Type: Grant
    Filed: February 15, 2022
    Date of Patent: August 22, 2023
    Assignee: Silicon Motion, Inc.
    Inventor: Ching-Hui Lin
  • Memory array having strap region with staggered dummy magnetic storage elements
    Patent number: 11737285
    Abstract: A memory array includes at least one strap region having therein a plurality of source line straps and a plurality of word line straps, and at least two sub-arrays having a plurality of staggered, active magnetic storage elements. The at least two sub-arrays are separated by the strap region. A plurality of staggered, dummy magnetic storage elements is disposed within the strap region.
    Type: Grant
    Filed: March 15, 2021
    Date of Patent: August 22, 2023
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Po-Kai Hsu, Hui-Lin Wang, Kun-I Chou, Ching-Hua Hsu, Ju-Chun Fan, Yi-Yu Lin, Hung-Yueh Chen
  • SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
    Publication number: 20230263067
    Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a cap layer adjacent to the MTJ and extended to overlap a top surface of the MTJ, a top electrode on the MTJ, a metal interconnection under the MTJ, a first inter-metal dielectric (IMD) layer around the MTJ, and a second IMD layer around the metal interconnection. Preferably, the cap layer is adjacent to the top electrode and the MTJ and on the second IMD layer and a top surface of the cap layer is higher than a top surface of the first IMD layer.
    Type: Application
    Filed: April 18, 2023
    Publication date: August 17, 2023
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Po-Kai Hsu, Hung-Yueh Chen, Yu-Ping Wang
  • Contact structure
    Patent number: 11728170
    Abstract: A semiconductor device includes: a fin structure disposed on a substrate; a gate feature that traverses the fin structure to overlay a central portion of the fin structure; a pair of source/drain features, along the fin structure, that are disposed at respective sides of the gate feature; and a plurality of contact structures that are formed of tungsten, wherein a gate electrode of the gate feature and the pair of source/drain features are each directly coupled to a respective one of the plurality of contact structures.
    Type: Grant
    Filed: July 8, 2021
    Date of Patent: August 15, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hong-Ying Lin, Cheng-Yi Wu, Alan Tu, Chung-Liang Cheng, Li-Hsuan Chu, Ethan Hsiao, Hui-Lin Sung, Sz-Yuan Hung, Sheng-Yung Lo, C. W. Chiu, Chih-Wei Hsieh, Chin-Szu Lee
  • LIGHT-EMITTING DIODE
    Publication number: 20230253531
    Abstract: A light-emitting diode includes a semiconductor light-emitting stack, a transparent conductive layer, a first current blocking layer, and a first electrode pad. The semiconductor light-emitting stack includes, in sequence from bottom to top, a second conductivity type semiconductor layer, a light-emitting layer, and a first conductivity type semiconductor layer. The transparent conductive layer is disposed on the first conductivity type semiconductor layer, and is formed with a first opening which is defined by an inner edge of the transparent conductive layer. The first current blocking layer is formed on the first conductivity type semiconductor layer. The first electrode pad is formed on and in contact with both the first current blocking layer and on the first conductivity type semiconductor layer. The first electrode pad has a width not greater than a dimension of the first opening.
    Type: Application
    Filed: April 7, 2023
    Publication date: August 10, 2023
    Inventors: GONG CHEN, SU-HUI LIN, SHENG-HSIEN HSU, MINYOU HE, KANG-WEI PENG, LING-YUAN HONG
  • Light-emitting diode device and method for manufacturing the same
    Patent number: 11721789
    Abstract: A light-emitting diode (LED) device includes a substrate, an epitaxial layered structure disposed on the substrate, a current-spreading layer disposed on the epitaxial layered structure, a current-blocking unit disposed on the current-spreading layer, and a distributed Bragg reflector. The epitaxial layered structure, the current-spreading layer and the current-blocking unit are covered by the distributed Bragg reflector. One of the current-spreading layer, the current-blocking unit, and a combination thereof has a patterned rough structure. A method for manufacturing the LED device is also disclosed.
    Type: Grant
    Filed: June 13, 2022
    Date of Patent: August 8, 2023
    Inventors: Jiangbin Zeng, Anhe He, Ling-yuan Hong, Kang-Wei Peng, Su-hui Lin, Chia-Hung Chang
  • Semiconductor device and method for fabricating the same
    Patent number: 11716860
    Abstract: A method for fabricating a semiconductor device includes the steps of: forming a magnetic tunneling junction (MTJ) on a substrate; forming a first inter-metal dielectric (IMD) layer around the MTJ; forming a first metal interconnection adjacent to the MTJ; forming a stop layer on the first IMD layer; removing the stop layer to form an opening; and forming a channel layer in the opening to electrically connect the MTJ and the first metal interconnection.
    Type: Grant
    Filed: May 26, 2020
    Date of Patent: August 1, 2023
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Po-Kai Hsu, Jing-Yin Jhang, Yu-Ping Wang, Hung-Yueh Chen, Wei Chen
  • MRAM structure with source lines having alternating branches at opposite sides and storage units in staggered arrangement
    Patent number: 11715499
    Abstract: A MRAM structure, which is provided with multiple source lines between active areas, each source line has multiple branches electrically connecting with the active areas at opposite sides in alternating arrangement. Multiple word lines traverse through the active areas to form transistors. Multiple storage units are disposed between the word lines on the active areas in staggered array arrangement, and multiple bit lines electrically connect with storage units on corresponding active areas, wherein each storage cell includes one of the storage unit, two of the transistors respectively at both sides of the storage unit, and two branches of the source line.
    Type: Grant
    Filed: April 7, 2021
    Date of Patent: August 1, 2023
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Po-Kai Hsu, Hung-Yueh Chen, Kun-I Chou, Jing-Yin Jhang, Hui-Lin Wang, Yu-Ping Wang
  • ANTENNA STRUCTURE AND ELECTRONIC DEVICE USING THE SAME
    Publication number: 20230238700
    Abstract: An antenna structure for a metal-cased electronic device includes a radiator, a feed portion, and a slit. The feed portion can feed signals into the radiator, the radiator includes a first end and a second end, the first end disposes a first radiation portion, the second end disposes a second radiation portion and a third radiation portion, the second radiation portion and the third radiation portion are coupled to each other to radiate a radiation signal at a first frequency band, the slit and the radiator is spaced at intervals, and the slit is coupled to the first radiation portion to radiate the radiation signal at a second frequency band. The present disclosure also provides an electronic device with the antenna structure.
    Type: Application
    Filed: January 9, 2023
    Publication date: July 27, 2023
    Inventors: CHIH-HUNG LAI, YEN-HUI LIN, WEI-CHENG SU, YUN-JIAN CHANG, GENG-HONG LIOU, CHO-KANG HSU
  • SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
    Publication number: 20230240151
    Abstract: A method for fabricating a semiconductor device includes the steps of forming a magnetic tunneling junction (MTJ) on a MRAM region of a substrate, forming a first inter-metal dielectric (IMD) layer around the MTJ, forming a patterned mask on a logic region of the substrate, performing a nitridation process to transform part of the first IMD layer to a nitride layer, forming a first metal interconnection on the logic region, forming a stop layer on the first IMD layer, forming a second IMD layer on the stop layer, and forming a second metal intercom in the second IMD layer to connect to the MTJ.
    Type: Application
    Filed: March 17, 2023
    Publication date: July 27, 2023
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Chen-Yi Weng, Si-Han Tsai, Che-Wei Chang, Po-Kai Hsu, Jing-Yin Jhang, Yu- Ping Wang, Ju-Chun Fan, Ching-Hua Hsu, Yi-Yu Lin, Hung-Yueh Chen
  • SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME
    Publication number: 20230238043
    Abstract: A semiconductor structure includes a substrate having a memory device region and a logic device region, a first dielectric layer on the substrate, a plurality of memory stack structures on the first dielectric layer on the memory device region, an insulating layer conformally covering the memory stack structures and the first dielectric layer, a second dielectric layer on the insulating layer and completely filling the spaces between the memory stack structures, and a first interconnecting structure formed in the second dielectric layer on the logic device region. A top surface of the first interconnecting structure is flush with a top surface of the second dielectric layer and higher than top surfaces of the memory stack structures.
    Type: Application
    Filed: March 28, 2023
    Publication date: July 27, 2023
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Yu-Ping Wang, Chen-Yi Weng, Chin-Yang Hsieh, Yi-Hui Lee, Ying-Cheng Liu, Yi-An Shih, I-Ming Tseng, Jing-Yin Jhang, Chien-Ting Lin
  • SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURING SEMICONDUCTOR STRUCTURE
    Publication number: 20230240079
    Abstract: A semiconductor structure includes a first die, a second die, and an inter die via (IDV). The first die includes an interconnection structure and a CMOS device electrically connected to the interconnection structure. The second die includes a memory element including a first electrode, a ferroelectric layer on the first electrode, and a second electrode on the ferroelectric layer, wherein a peripheral region of the ferroelectric layer is exposed by and surrounding the second electrode from a top view perspective. The IDV electrically connects the interconnection structure of the first die to the memory element of the second die.
    Type: Application
    Filed: June 7, 2022
    Publication date: July 27, 2023
    Inventors: Chun-Ren Cheng, Ching-Hui Lin, Fu-Chun Huang, Chao-Hung Chu, Po-Chen Yeh
  • LIGHT-EMITTING DEVICE
    Publication number: 20230231075
    Abstract: A light-emitting device includes an epitaxial structure that includes a first semiconductor layer, an active layer and a second semiconductor layer. The light-emitting device further has a transparent current spreading unit, a first electrode and a second electrode. The transparent current spreading unit includes a first transparent current spreading layer and a second transparent current spreading layer. The first transparent current spreading layer is doped with aluminum and has a thickness that accounts for 0.5% to 33% of a thickness of the transparent current spreading unit. The second transparent current spreading layer has a thickness greater than that of the first transparent current spreading layer. A light-emitting apparatus includes a circuit control component, and a light source that is coupled to the circuit control component and that includes the aforesaid light-emitting device.
    Type: Application
    Filed: November 22, 2022
    Publication date: July 20, 2023
    Inventors: Huining Wang, Hongwei Xia, Quanyang Ma, Shiwei Liu, Jiali Zhuo, Shuo Yang, Su-Hui Lin, Chung-Ying Chang
  • MAGNETIC MEMORY DEVICE AND METHOD FOR FORMING THE SAME
    Publication number: 20230232637
    Abstract: A magnetic memory device includes a bottom electrode layer, a magnetic tunneling junction (MTJ) stack disposed on the bottom electrode layer, a dielectric cap layer disposed on the MTJ stack, and a metal cap layer disposed on the dielectric cap layer, wherein the metal cap layer comprises a plurality of first metal layers and second metal layers alternately stacked on the dielectric cap layer.
    Type: Application
    Filed: February 20, 2022
    Publication date: July 20, 2023
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Jing-Yin Jhang
  • ORGANOMETALLIC COMPLEX COATING SOLUTION AND NEAR INFRARED ABSORPTION FILM
    Publication number: 20230227669
    Abstract: Provided are an organometallic complex coating solution and a near-infrared absorption film, including an organometallic complex, a phosphorus-containing dispersant, and optical resin. The present disclosure greatly reduces the temperature and time of the film-forming process by formulating components of the organometallic complex coating solution.
    Type: Application
    Filed: January 17, 2023
    Publication date: July 20, 2023
    Inventors: Feng-Ling WU, Shih-Song CHENG, Tang-Hao YANG, Tzu-Ling CHAO, Bo-Xun ZHU, Hsing-Hui LIN, Kuo-Chen LI, Chang-Jun LIN
  • MEMORY ARRAY
    Publication number: 20230232638
    Abstract: Abstract of Disclosure A memory array includes at least one strap region, at least two sub-arrays, a plurality of staggered, dummy magnetic storage elements, and a plurality of bit line structures. The strap region includes a plurality of source line straps and a plurality of word line straps. The two sub-arrays include a plurality of staggered, active magnetic storage elements. The two sub -arrays are separated by the strap region. The staggered, dummy magnetic storage elements are disposed within the strap region. The bit line structures are disposed in the two sub-arrays, and each of the bit line structures is disposed above and directly connected with at least one of the staggered, active magnetic storage elements.
    Type: Application
    Filed: February 16, 2022
    Publication date: July 20, 2023
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Ju-Chun Fan, Ching-Hua Hsu, Chun-Hao Wang, Yi-Yu Lin, Dong-Ming Wu, Po-Kai Hsu
  • Soap dispenser
    Patent number: D994384
    Type: Grant
    Filed: November 5, 2020
    Date of Patent: August 8, 2023
    Assignee: Ableman International Co., Ltd.
    Inventor: Po-Hui Lin