Patents by Inventor Hui Lin

Hui Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240032440
    Abstract: A semiconductor device includes a substrate comprising a MTJ region and a logic region, a magnetic tunneling junction (MTJ) on the MTJ region, and a contact plug on the logic region. Preferably, the MTJ includes a bottom electrode layer having a gradient concentration, a free layer on the bottom electrode layer, and a top electrode layer on the free layer.
    Type: Application
    Filed: October 3, 2023
    Publication date: January 25, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Chia-Chang Hsu, Chen-Yi Weng, Chin-Yang Hsieh, Jing-Yin Jhang
  • Publication number: 20240032439
    Abstract: A method of fabricating magnetoresistive random access memory, including providing a substrate, forming a bottom electrode layer, a magnetic tunnel junction stack, a top electrode layer and a hard mask layer sequentially on the substrate, wherein a material of the top electrode layer is titanium nitride, a material of the hard mask layer is tantalum or tantalum nitride, and a percentage of nitrogen in the titanium nitride gradually decreases from a top surface of top electrode layer to a bottom surface of top electrode layer, and patterning the bottom electrode layer, the magnetic tunnel junction stack, the top electrode layer and the hard mask layer into multiple magnetoresistive random access memory cells.
    Type: Application
    Filed: September 27, 2023
    Publication date: January 25, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Chen-Yi Weng, Chin-Yang Hsieh, Yi-Hui Lee, Ying-Cheng Liu, Yi-An Shih, Jing-Yin Jhang, I-Ming Tseng, Yu-Ping Wang, Chien-Ting Lin, Kun-Chen Ho, Yi-Syun Chou, Chang-Min Li, Yi-Wei Tseng, Yu-Tsung Lai, JUN XIE
  • Publication number: 20240030262
    Abstract: A semiconductor structure is disclosed. The semiconductor structure includes a number of pixels and neighboring pixels are isolated by deep trench isolation structures. In an embodiment, a method of forming the semiconductor structure includes epitaxially growing a p-type semiconductor layer on a substrate, epitaxially growing an n-type semiconductor layer over the p-type semiconductor layer, after the epitaxially growing of the n-type semiconductor layer, forming a p-type well in the n-type semiconductor layer, forming an n-type doped region in the n-type semiconductor layer and surrounded by the p-type well, forming a first trench extending through the n-type semiconductor layer and the p-type semiconductor layer and surrounding the p-type well, and forming a first isolation structure in the first trench.
    Type: Application
    Filed: March 14, 2023
    Publication date: January 25, 2024
    Inventors: Po Chun Chang, Ping-Hao Lin, Kun-Hui Lin, Kuo-Cheng Lee
  • Publication number: 20240027549
    Abstract: A method for fabricating semiconductor device includes the steps of first forming a magnetic tunneling junction (MTJ) stack on a substrate, in which the MTJ stack includes a pinned layer on the substrate, a barrier layer on the pinned layer, and a free layer on the barrier layer. Next, a top electrode is formed on the MTJ stack, the top electrode, the free layer, and the barrier layer are removed, a first cap layer is formed on the top electrode, the free layer, and the barrier layer, and the first cap layer and the pinned layer are removed to form a MTJ and a spacer adjacent to the MTJ.
    Type: Application
    Filed: October 4, 2023
    Publication date: January 25, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Chen-Yi Weng, Che-Wei Chang, Si-Han Tsai, Ching-Hua Hsu, Jing-Yin Jhang, Yu-Ping Wang
  • Patent number: 11882769
    Abstract: A magnetoresistive random access memory (MRAM) structure is provided in the present invention, including multiple MRAM cells, and an atomic layer deposition dielectric layer between and at outer sides of the MRAM cells, wherein the material of top electrode layer is titanium nitride, and the nitrogen percentage is greater than titanium percentage and further greater than oxygen percentage in the titanium nitride, and the nitrogen percentage gradually increases inward from the top surface of top electrode layer to a depth and then start to gradually decrease to a first level and then remains constant, and the titanium percentage gradually decreases inward from the top surface of top electrode layer to the depth and then start to gradually increase to a second level and then remains constant.
    Type: Grant
    Filed: April 25, 2021
    Date of Patent: January 23, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Bo-Yun Huang, Wen-Wen Zhang, Kun-Chen Ho
  • Publication number: 20240023456
    Abstract: A method for fabricating semiconductor device includes the steps of first forming a spin orbit torque (SOT) layer on a substrate, forming a magnetic tunneling junction (MTJ) stack on the SOT layer, performing a first etching process to remove part of the MTJ stack, and then performing a second etching process to remove part of the MTJ stack for forming a MTJ.
    Type: Application
    Filed: August 15, 2022
    Publication date: January 18, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventor: Hui-Lin Wang
  • Publication number: 20240023455
    Abstract: A method for fabricating semiconductor device includes the steps of first forming a bottom electrode on a substrate, forming a magnetic tunneling junction (MTJ) on the bottom electrode, and then forming a cap layer on the MTJ. Preferably, the formation of the cap layer could be accomplished by the following steps: (a) forming a first metal layer on the MTJ; (b) forming a second metal layer on the first metal layer; and (c) performing an oxidation process.
    Type: Application
    Filed: August 14, 2022
    Publication date: January 18, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventor: Hui-Lin Wang
  • Publication number: 20240021113
    Abstract: The present disclosure provides an electronic device including a substrate, a first circuit layer, and a plurality of diodes. The substrate has a plurality of first through holes. The first circuit layer is disposed on the substrate and has a plurality of light through holes. The diodes disposed on the first circuit layer. One of the light through holes is located between two adjacent ones of the diodes, and the light through holes overlap a portion of the plurality of first through holes and do not overlap another portion of the plurality of first through holes in a normal direction of the substrate.
    Type: Application
    Filed: September 26, 2023
    Publication date: January 18, 2024
    Applicant: InnoLux Corporation
    Inventors: Chin-Lung Ting, Chung-Kuang Wei, Li-Wei Mao, Chi-Liang Chang, Chia-Hui Lin
  • Publication number: 20240001613
    Abstract: A feed detection apparatus of a 3D printer, comprising a gear, a measurement device, a support, and a compression assembly. The gear is provided on the support to abut against a filament material, and rotates along with a movement of the filament material. The measurement device is placed on the support to measure a rotating speed of the gear, and determines a feeding status of the filament material according to a measurement result. The compression assembly comprises a connection member and an abutment member; the connection member is provided between the support and the abutment member; the abutment member is used for regulating a pressure of the connecting member applied on the support so as to enable the gear to abut against the filament material.
    Type: Application
    Filed: December 30, 2020
    Publication date: January 4, 2024
    Inventors: HUI-LIN LIU, JING-KE TANG, CHUN CHEN, DAN-JUN AO, SHENG-YUAN LV
  • Publication number: 20240008369
    Abstract: A semiconductor device includes a bottom electrode on a substrate, a magnetic tunneling junction (MTJ) on the bottom electrode, a first cap layer on the MTJ, a second cap layer on the first cap layer, a block layer on the second cap layer, and a top electrode on the block layer. Preferably, the block layer could be made of Co-based alloy or metal nitride, in which the Co-based alloy could further include CoW alloy whereas the metal nitride could include WN.
    Type: Application
    Filed: August 1, 2022
    Publication date: January 4, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventor: Hui-Lin Wang
  • Patent number: 11859176
    Abstract: A method for in vitro activation and/or expansion of immune cells is provided, including the steps of: a) providing magnetic particles having multi-protrusive surface modified with at least one type of immuno-inducing substance, in which each magnetic particle includes a copolymer core, a polymer layer, a magnetic substance layer, and a silicon-based layer from the inside to the outside; b) providing a cell solution including at least one type of immune cell in the cell solution; and c) bringing the magnetic particles in contact with the cell solution, in which the at least one type of immuno-inducing substance on the surface of the magnetic particle activates and/or expands the at least one type of immune cell in the cell solution.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: January 2, 2024
    Assignees: Industrial Technology Research Institute, National Taiwan University Hospital
    Inventors: Cheng-Tai Chen, Chien-An Chen, Wen-Ting Chiang, Su-Feng Chiu, Pei-Shin Jiang, Jih-Luh Tang, Chien-Ting Lin, Xuan-Hui Lin
  • Patent number: 11864468
    Abstract: A magnetoresistive random access memory (MRAM) device includes a first array region and a second array region on a substrate, a first magnetic tunneling junction (MTJ) on the first array region, a first top electrode on the first MTJ, a second MTJ on the second array region, and a second top electrode on the second MTJ. Preferably, the first top electrode and the second top electrode include different nitrogen to titanium (N/Ti) ratios.
    Type: Grant
    Filed: June 16, 2021
    Date of Patent: January 2, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Si-Han Tsai, Dong-Ming Wu, Chen-Yi Weng, Ching-Hua Hsu, Ju-Chun Fan, Yi-Yu Lin, Che-Wei Chang, Po-Kai Hsu, Jing-Yin Jhang
  • Patent number: 11862752
    Abstract: A light-emitting diode includes a substrate, a distributed Bragg reflector (DBR) structure and a semiconductor layered structure. The DBR structure is disposed on the substrate. The semiconductor layered structure is disposed on the DBR structure opposite to the substrate, and is configured to emit a light having a first wavelength. The DBR structure has a reflectance of not greater than 30% for the light having the first wavelength, and a reflectance of not smaller than 50% for a laser beam having a second wavelength that is different from the first wavelength.
    Type: Grant
    Filed: July 2, 2021
    Date of Patent: January 2, 2024
    Assignee: Quanzhou San'an Semiconductor Technology Co., Ltd.
    Inventors: Qing Wang, Dazhong Chen, Sheng-Hsien Hsu, Ling-yuan Hong, Kang-Wei Peng, Su-hui Lin, Chia-Hung Chang
  • Patent number: 11856863
    Abstract: A method of forming a semiconductor memory device is disclosed. A top electrode layer is formed on the MTJ stack layer. A patterned buffer layer is formed to cover only the logic circuit region. A hard mask layer is formed on the top electrode layer and the patterned buffer layer. A patterned resist layer is formed on the hard mask layer. A first etching process is performed to etch the hard mask layer and the top electrode layer not covered by the patterned resist layer in the memory region and the hard mask layer, the patterned buffer layer and the top electrode layer in the logic circuit region, thereby forming a top electrode on the MTJ stack layer in the memory region and a remaining top electrode layer covering only the logic circuit region on the MTJ stack layer.
    Type: Grant
    Filed: June 10, 2021
    Date of Patent: December 26, 2023
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventor: Hui-Lin Wang
  • Patent number: 11849766
    Abstract: The present disclosure relates to an aerosol-generating device, including a heater, a bottom support, a drive assembly, and a linkage assembly. The heater is configured to be inserted into an aerosol-generating article to heat an aerosol-generating material therein to generate aerosol. The bottom support is slidably connected to a housing defining the accommodating cavity. A movement direction of the bottom support is parallel to a length direction of the accommodating cavity. The drive assembly is movably coupled to the heater assembly and configured to push or drawn the heater assembly to slide between a heating position and a separation position. The linkage assembly is configured to trigger movement of the bottom support toward an insertion opening of the accommodating cavity when the heater approaches or reaches the separation position to extract the aerosol-generating article from the accommodating cavity.
    Type: Grant
    Filed: November 26, 2020
    Date of Patent: December 26, 2023
    Inventors: Bin Chen, Yong-Hui Lin
  • Patent number: 11853648
    Abstract: Systems and methods for smart sensors are provided. A smart sensor includes: a case; a power adapter configured to be plugged directly into an electrical outlet; a computer processor; a microphone; a speaker; a camera; at least one sensor; a control switch; a sync button; a USB port; and a memory storing: an operating system; a voice control module; a peer interaction module; a remote interaction module; and a cognitive module. In embodiments, the power adapter includes prongs that extend from a back side of the case, and the microphone, the speaker, the camera, and the at least one sensor are on a front side of the case opposite the back side of the case.
    Type: Grant
    Filed: April 16, 2021
    Date of Patent: December 26, 2023
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Stan K. Daley, Zhong-Hui Lin, Tao Liu, Dean Phillips, Kent R. VanOoyen
  • Patent number: 11849648
    Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a first spacer on one side of the of the MTJ, a second spacer on another side of the MTJ, a first metal interconnection on the MTJ, and a liner adjacent to the first spacer, the second spacer, and the first metal interconnection. Preferably, each of a top surface of the MTJ and a bottom surface of the first metal interconnection includes a planar surface and two sidewalls of the first metal interconnection are aligned with two sidewalls of the MTJ.
    Type: Grant
    Filed: June 8, 2021
    Date of Patent: December 19, 2023
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Chen-Yi Weng, Yi-Wei Tseng, Chin-Yang Hsieh, Jing-Yin Jhang, Yi-Hui Lee, Ying-Cheng Liu, Yi-An Shih, I-Ming Tseng, Yu-Ping Wang
  • Patent number: 11848843
    Abstract: Anomalies in network traffic are detected using machine learning. A plurality of machine learning models is employed to determine whether there are anomalies in network traffic of an MPLS (Multiprotocol Label Switching) network that can affect the performance of devices in the network. A first machine learning model is trained on network traffic passed through network tunnels of a plurality of routers in the network. A second machine learning model is trained on router-specific network traffic passed through router-specific network traffic for a subset of the network tunnels associated with a particular router. The first machine learning model is employed to determine a network anomaly, and the second machine learning model is employed to determine a router-specific anomaly. A router error is identified when both a network anomaly and a router-specific anomaly are determined. An indication of the router error is communicated to a computing device.
    Type: Grant
    Filed: December 28, 2021
    Date of Patent: December 19, 2023
    Assignee: T-Mobile Innovations LLC
    Inventors: Lance Paul Lukens, Hui-Lin Chang, Shawn Derek Wallace, Piradee Nganrungruang
  • Publication number: 20230401281
    Abstract: A matrix operation-based method for modifying a mobile social network graph, including step S1: obtaining a accessibility matrix set A of a social network graph to be modified; step S2: determining information to be modified for each node in the social network graph to be modified, and creating a List to be modified; step S3: for each node in the social network graph to be modified, determining whether edge adding is required according to the List to be modified; and step S4: if there is still a non-zero value in the List after all nodes are traversed, directly adding Max(List) nodes to a network, and randomly performing edge connection between the added nodes and nodes still requiring edge adding, so that all values in the List are zero, thereby completing graph modification.
    Type: Application
    Filed: August 23, 2022
    Publication date: December 14, 2023
    Applicant: FUJIAN NORMAL UNIVERSITY
    Inventors: Li XU, Xiaolin LI, Binting SU, Hongyan ZHANG, Hui LIN
  • Patent number: D1010000
    Type: Grant
    Filed: August 2, 2021
    Date of Patent: January 2, 2024
    Assignee: Shenzhen Creality 3D Technology Co., Ltd.
    Inventors: Hui-Lin Liu, Jing-Ke Tang, Chun Chen, Dan-Jun Ao