Patents by Inventor Hui Lin

Hui Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11853648
    Abstract: Systems and methods for smart sensors are provided. A smart sensor includes: a case; a power adapter configured to be plugged directly into an electrical outlet; a computer processor; a microphone; a speaker; a camera; at least one sensor; a control switch; a sync button; a USB port; and a memory storing: an operating system; a voice control module; a peer interaction module; a remote interaction module; and a cognitive module. In embodiments, the power adapter includes prongs that extend from a back side of the case, and the microphone, the speaker, the camera, and the at least one sensor are on a front side of the case opposite the back side of the case.
    Type: Grant
    Filed: April 16, 2021
    Date of Patent: December 26, 2023
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Stan K. Daley, Zhong-Hui Lin, Tao Liu, Dean Phillips, Kent R. VanOoyen
  • Patent number: 11849648
    Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a first spacer on one side of the of the MTJ, a second spacer on another side of the MTJ, a first metal interconnection on the MTJ, and a liner adjacent to the first spacer, the second spacer, and the first metal interconnection. Preferably, each of a top surface of the MTJ and a bottom surface of the first metal interconnection includes a planar surface and two sidewalls of the first metal interconnection are aligned with two sidewalls of the MTJ.
    Type: Grant
    Filed: June 8, 2021
    Date of Patent: December 19, 2023
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Chen-Yi Weng, Yi-Wei Tseng, Chin-Yang Hsieh, Jing-Yin Jhang, Yi-Hui Lee, Ying-Cheng Liu, Yi-An Shih, I-Ming Tseng, Yu-Ping Wang
  • Patent number: 11848843
    Abstract: Anomalies in network traffic are detected using machine learning. A plurality of machine learning models is employed to determine whether there are anomalies in network traffic of an MPLS (Multiprotocol Label Switching) network that can affect the performance of devices in the network. A first machine learning model is trained on network traffic passed through network tunnels of a plurality of routers in the network. A second machine learning model is trained on router-specific network traffic passed through router-specific network traffic for a subset of the network tunnels associated with a particular router. The first machine learning model is employed to determine a network anomaly, and the second machine learning model is employed to determine a router-specific anomaly. A router error is identified when both a network anomaly and a router-specific anomaly are determined. An indication of the router error is communicated to a computing device.
    Type: Grant
    Filed: December 28, 2021
    Date of Patent: December 19, 2023
    Assignee: T-Mobile Innovations LLC
    Inventors: Lance Paul Lukens, Hui-Lin Chang, Shawn Derek Wallace, Piradee Nganrungruang
  • Publication number: 20230401281
    Abstract: A matrix operation-based method for modifying a mobile social network graph, including step S1: obtaining a accessibility matrix set A of a social network graph to be modified; step S2: determining information to be modified for each node in the social network graph to be modified, and creating a List to be modified; step S3: for each node in the social network graph to be modified, determining whether edge adding is required according to the List to be modified; and step S4: if there is still a non-zero value in the List after all nodes are traversed, directly adding Max(List) nodes to a network, and randomly performing edge connection between the added nodes and nodes still requiring edge adding, so that all values in the List are zero, thereby completing graph modification.
    Type: Application
    Filed: August 23, 2022
    Publication date: December 14, 2023
    Applicant: FUJIAN NORMAL UNIVERSITY
    Inventors: Li XU, Xiaolin LI, Binting SU, Hongyan ZHANG, Hui LIN
  • Publication number: 20230399225
    Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a first device and a second device disposed adjacent to the first device; a conductive pillar disposed adjacent to the first device or the second device; a molding surrounding the first device, the second device and the conductive pillar; and a redistribution layer (RDL) over the first device, the second device, the molding and the conductive pillar, wherein the RDL electrically connects the first device to the second device and includes an opening penetrating the RDL and exposing a sensing area over the first device.
    Type: Application
    Filed: June 10, 2022
    Publication date: December 14, 2023
    Inventors: PO CHEN YEH, YI-HSIEN CHANG, FU-CHUN HUANG, CHING-HUI LIN, CHIAHUNG LIU, SHIH-FEN HUANG, CHUN-REN CHENG
  • Publication number: 20230403941
    Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a cap layer adjacent to and directly contacting the MTJ, a first inter-metal dielectric (IMD) layer around the MTJ, a top electrode on the MTJ, a metal interconnection under the MTJ, and a second IMD layer around the metal interconnection. Preferably, the cap layer is a single layer structure made of dielectric material and an edge of the cap layer contacts the first IMD layer directly.
    Type: Application
    Filed: August 27, 2023
    Publication date: December 14, 2023
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Po-kai Hsu, Hung-Yueh Chen, Yu-Ping Wang
  • Publication number: 20230403946
    Abstract: A method for fabricating semiconductor device includes first forming a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate, performing an atomic layer deposition (ALD) process or a high-density plasma (HDP) process to form a passivation layer on the first MTJ and the second MTJ, performing an etching process to remove the passivation layer adjacent to the first MTJ and the second MTJ, and then forming an ultra low-k (ULK) dielectric layer on the passivation layer.
    Type: Application
    Filed: August 28, 2023
    Publication date: December 14, 2023
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Tai-Cheng Hou, Wei-Xin Gao, Fu-Yu Tsai, Chin-Yang Hsieh, Chen-Yi Weng, Jing-Yin Jhang, Bin-Siang Tsai, Kun-Ju Li, Chih-Yueh Li, Chia-Lin Lu, Chun-Lung Chen, Kun-Yuan Laio, Yu-Tsung Lai, Wei-Hao Huang
  • Patent number: 11844134
    Abstract: A cell site maintenance system. The system comprises a plurality of data stores, a processor, a memory coupled to the processor, and a part replacement prediction application stored in memory. When executed by the processor the application extracts features based on data read from the data stores, executes a plurality of part machine learning models, where each part machine learning model analyses some of the extracted features by a multi-label classification model trained for a specific part associated with that part machine learning model and each part machine learning model outputs a probability that the associated part can fix the cell site associated with the trouble ticket, and, based on a probability output by a part machine learning model associated with a first part exceeding a predefined threshold, determining that the first part is to be pulled from a part inventory to make ready for a service truck.
    Type: Grant
    Filed: February 2, 2020
    Date of Patent: December 12, 2023
    Assignee: T-MOBILE INNOVATIONS LLC
    Inventors: Diksha Agarwal, Hui-Lin Chang, Lance P. Lukens, Daqi Li, Leland John Garris, Wayne Alexander Thompson
  • Publication number: 20230389309
    Abstract: The present disclosure describes a patterning process for a strap region in a memory cell for the removal of material between polysilicon lines. The patterning process includes depositing a first hard mask layer in a divot formed on a top portion of a polysilicon layer interposed between a first polysilicon gate structure and a second polysilicon gate; depositing a second hard mask layer on the first hard mask layer. The patterning process also includes performing a first etch to remove the second hard mask layer and a portion of the second hard mask layer from the divot; performing a second etch to remove the second hard mask layer from the divot; and performing a third etch to remove the polysilicon layer not covered by the first and second hard mask layers to form a separation between the first polysilicon gate structure and the second polysilicon structure.
    Type: Application
    Filed: August 10, 2023
    Publication date: November 30, 2023
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yen-Jou WU, Hsin-Hui Lin, Yu-Liang Wang, Chih-Ming Lee, Keng-Ying Liao, Ping-Pang Hsieh, Su-Yu Yeh
  • Publication number: 20230387164
    Abstract: The present disclosure relates to an integrated chip including a semiconductor layer and a photodetector disposed along the semiconductor layer. A color filter is over the photodetector. A micro-lens is over the color filter. A dielectric structure comprising one or more dielectric layers is over the micro-lens. A receptor layer is over the dielectric structure. An optical signal enhancement structure is disposed along the dielectric structure and between the receptor layer and the micro-lens.
    Type: Application
    Filed: May 25, 2022
    Publication date: November 30, 2023
    Inventors: Yi-Hsien Chang, Shih-Fen Huang, Chun-Ren Cheng, Fu-Chun Huang, Ching-Hui Lin
  • Publication number: 20230382052
    Abstract: Disclosed in the present invention are a method and apparatus for automatically improving printing effect, a device, and a storage medium. The method comprises: receiving an import request of a 3D model, and parsing a triangle patch comprised in the 3D model; acquiring all angular points of the 3D model according to the triangle patch, subtracting a minimum angular point from a maximum angular point to obtain a bounding box of the 3D model, creating an axis perpendicular to the bounding box; using the axis and a platform inclination angle to calculate a quaternion related to the rotation of the 3D model; multiplying a space matrix of the bounding box of the 3D model by the rotation matrix, enabling a printing path to be perpendicular to the bounding box. The model is imported to automatically keep the inclination angle consistent with a platform, thereby improving the printing effect.
    Type: Application
    Filed: December 28, 2020
    Publication date: November 30, 2023
    Applicant: Shenzhen Creality 3D Technology Co., Ltd.
    Inventors: HUI-LIN LIU, JING-KE TANG, CHUN CHEN, DAN-JUN AO, WEN-BIN WANG
  • Publication number: 20230375500
    Abstract: A bioFET device includes a semiconductor substrate having a first surface and an opposite, parallel second surface and a plurality of bioFET sensors on the semiconductor substrate. Each of the bioFET sensors includes a gate formed on the first surface of the semiconductor substrate and a channel region formed within the semiconductor substrate beneath the gate and between source/drain (S/D) regions in the semiconductor substrate. The channel region includes a portion of the second surface of the semiconductor substrate. An isolation layer is disposed on the second surface of the semiconductor substrate. The isolation layer has an opening positioned over the channel region of more than one bioFET sensor of the plurality of bioFET sensors. An interface layer is disposed on the channel region of the more than one bioFET sensor in the opening.
    Type: Application
    Filed: July 31, 2023
    Publication date: November 23, 2023
    Applicant: Tawian Semiconductor Manufacturing Co., Ltd.
    Inventors: Jui-Cheng Huang, Yi-Hsien Chang, Chin-Hua Wen, Chun-Ren Cheng, Shih-Fen Huang, Tung-Tsun Chen, Yu-Jie Huang, Ching-Hui Lin, Sean Cheng, Hector Chang
  • Publication number: 20230377989
    Abstract: A method includes etching a first recess adjacent a first dummy gate stack and a first fin; etching a second recess adjacent a second dummy gate stack and a second fin; and epitaxially growing a first epitaxy region in the first recess. The method further includes depositing a first metal-comprising mask over the first dummy gate stack, over the second dummy gate stack, over the first epitaxy region in the first recess, and in the second recess; patterning the first metal-comprising mask to expose the first dummy gate stack and the first epitaxy region; epitaxially growing a second epitaxy region in the first recess over the first epitaxy region; and after epitaxially growing the second epitaxy region, removing remaining portions of the first metal-comprising mask.
    Type: Application
    Filed: August 4, 2023
    Publication date: November 23, 2023
    Inventors: Hui-Lin Huang, Li-Li Su, Yee-Chia Yeo, Chii-Horng Li
  • Patent number: 11821964
    Abstract: A method for fabricating semiconductor device includes the steps of first forming a magnetic tunneling junction (MTJ) stack on a substrate, in which the MTJ stack includes a pinned layer on the substrate, a barrier layer on the pinned layer, and a free layer on the barrier layer. Next, a top electrode is formed on the MTJ stack, the top electrode, the free layer, and the barrier layer are removed, a first cap layer is formed on the top electrode, the free layer, and the barrier layer, and the first cap layer and the pinned layer are removed to form a MTJ and a spacer adjacent to the MTJ.
    Type: Grant
    Filed: July 13, 2020
    Date of Patent: November 21, 2023
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Chen-Yi Weng, Che-Wei Chang, Si-Han Tsai, Ching-Hua Hsu, Jing-Yin Jhang, Yu-Ping Wang
  • Patent number: 11818965
    Abstract: A semiconductor device includes a substrate comprising a MTJ region and a logic region, a magnetic tunneling junction (MTJ) on the MTJ region, and a contact plug on the logic region. Preferably, the MTJ includes a bottom electrode layer having a gradient concentration, a free layer on the bottom electrode layer, and a top electrode layer on the free layer.
    Type: Grant
    Filed: July 19, 2022
    Date of Patent: November 14, 2023
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Chia-Chang Hsu, Chen-Yi Weng, Chin-Yang Hsieh, Jing-Yin Jhang
  • Publication number: 20230361450
    Abstract: A microminiaturized antenna feed module includes a substrate, a plurality of coupled feed portions, and an active circuit. The substrate defines a plurality of visa penetrating the substrate. The coupled feed portions, made of conductive material and have different coupling areas, are electrically connected to the active circuit through the holes, to feed in electrical signals, the coupled feed portions couple the electrical signals to the metal frame to radiate wireless signals; the active circuit controls the switching of radiation modes of the metal frame. The application also provides an electronic device with the microminiaturized antenna feed module.
    Type: Application
    Filed: May 31, 2022
    Publication date: November 9, 2023
    Inventors: CHO-KANG HSU, MIN-HUI HO, WEI-CHENG SU, YEN-HUI LIN
  • Publication number: 20230361449
    Abstract: An electronic device includes a metal frame, a middle frame, and at least one antenna feed module. The metal frame includes an upper metal frame, a first side metal frame, a bottom metal frame, and a second side metal frame sequentially connected. The middle frame, spaced apart from the first side metal frame and the second side metal frame, forms a slit, the at least one antenna feed module is received in the slit.
    Type: Application
    Filed: May 31, 2022
    Publication date: November 9, 2023
    Inventors: CHO-KANG HSU, MIN-HUI HO, YEN-HUI LIN, WEI-CHENG SU
  • Patent number: 11808731
    Abstract: A bioFET device includes a semiconductor substrate having a first surface and an opposite, parallel second surface and a plurality of bioFET sensors on the semiconductor substrate. Each of the bioFET sensors includes a gate formed on the first surface of the semiconductor substrate and a channel region formed within the semiconductor substrate beneath the gate and between source/drain (S/D) regions in the semiconductor substrate. The channel region includes a portion of the second surface of the semiconductor substrate. An isolation layer is disposed on the second surface of the semiconductor substrate. The isolation layer has an opening positioned over the channel region of more than one bioFET sensor of the plurality of bioFET sensors. An interface layer is disposed on the channel region of the more than one bioFET sensor in the opening.
    Type: Grant
    Filed: December 28, 2020
    Date of Patent: November 7, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jui-Cheng Huang, Yi-Hsien Chang, Chin-Hua Wen, Chun-Ren Cheng, Shih-Fen Huang, Tung-Tsun Chen, Yu-Jie Huang, Ching-Hui Lin, Sean Cheng, Hector Chang
  • Patent number: 11812669
    Abstract: A magnetoresistive random access memory (MRAM), including a bottom electrode layer on a substrate, a magnetic tunnel junction stack on the bottom electrode layer, a top electrode layer on the magnetic tunnel junction stack, and a hard mask layer on said top electrode layer, wherein the material of top electrode layer is titanium nitride, a material of said hard mask layer is tantalum or tantalum nitride, and the percentage of nitrogen in the titanium nitride gradually decreases from the top surface of top electrode layer to the bottom surface of top electrode layer.
    Type: Grant
    Filed: June 9, 2022
    Date of Patent: November 7, 2023
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Chen-Yi Weng, Chin-Yang Hsieh, Yi-Hui Lee, Ying-Cheng Liu, Yi-An Shih, Jing-Yin Jhang, I-Ming Tseng, Yu-Ping Wang, Chien-Ting Lin, Kun-Chen Ho, Yi-Syun Chou, Chang-Min Li, Yi-Wei Tseng, Yu-Tsung Lai, Jun Xie
  • Patent number: 11809328
    Abstract: The present invention provides a control method of the flash memory controller. In the control method, by establishing a valid page count table, a detailed valid page count table and/or a zone valid page count table according to deallocate command from the host device, the flash memory controller can efficiently and quickly determine if any one of the zones does not have any valid data, so that the flash memory controller can recommend the host device to send a reset command to reset the zone. In addition, after receiving the reset command from the host device, the flash memory controller can use a garbage collection operation or directly put the blocks corresponding to the erased zone into a spare block pool, for the further use.
    Type: Grant
    Filed: January 24, 2022
    Date of Patent: November 7, 2023
    Assignee: Silicon Motion, Inc.
    Inventors: Ken-Fu Hsu, Ching-Hui Lin