Abstract: A semiconductor device including a substrate, a semiconductor package, a plurality of pillars and a lid is provided. The semiconductor package is disposed on the substrate and includes at least one semiconductor die. The plurality of pillars are disposed on the semiconductor package. The lid is disposed on the substrate and covers the semiconductor package and the plurality of pillars. The lid includes an inflow channel and an outflow channel to allow a coolant to flow into and out of a space between the substrate, the semiconductor package, the plurality of pillars and the lid. An inner surface of the lid, which faces and overlaps the plurality of pillars along a stacking direction of the semiconductor package and the lid, is a flat surface.

Abstract: A semiconductor device includes a substrate. The semiconductor device further includes a waveguide on a first side of the substrate. The semiconductor device further includes a photodetector (PD) on a second side of the substrate, opposite the first side of the substrate. The semiconductor device further includes an optical through via (OTV) optically connecting the PD with the waveguide, wherein the OTV extends through the substrate from the first side of the substrate to the second side of the substrate.

Abstract: The present invention relates to a post-exascale graph computing method, and corresponding system, storage medium and electronic device. The invention solves the problems of low computing performance, poor scalability and high communication overhead in the large-scale distributed environment, and improves the performance of the supercomputer when supporting large-scale graph computing.

Abstract: This disclosure relates to the fields of applied meteorology, in particular to a visualization analysis method of the tropical cyclone forecast verification index data, which comprises the following steps: acquiring tropical cyclone data; obtaining a track forecast verification index and an intensity forecast verification index of the tropical cyclone with the tropical cyclone data; obtaining a visible view of the tropical cyclone track forecast error and a visible view of the tropical cyclone intensity forecast error according to the track forecast verification index and the intensity forecast verification index, and in combination with the geographic information of the tropical cyclone; obtaining a first error and a second error according to the track forecast verification index, and obtaining a joint distribution map of the first error and the second error by using the first error and the second error; obtaining a composite box-shaped histogram through the intensity forecast verification index.

Abstract: The present disclosure describes heat dissipating structures that can be formed either in functional or non-functional areas of three-dimensional system on integrated chip structures. In some embodiments, the heat dissipating structures maintain an average operating temperature of memory dies or chips below about 90° C. For example, a structure includes a stack with chip layers, where each chip layer includes one or more chips and an edge portion. The structure further includes a thermal interface material disposed on the edge portion of each chip layer, a thermal interface material layer disposed over a top chip layer of the stack, and a heat sink over the thermal interface material layer.

Abstract: Disclosed are a point cloud polar coordinate coding method and a device, including dividing a circular scanning area scanned by a lidar at an equal angle with an angle ?? to obtain a plurality of identical polar coordinate areas; dividing each of the polar coordinate areas with equal length along a radial direction with a length ?r to obtain a plurality of polar coordinate grids and generating a plurality of polar coordinate cylinders corresponding to each of the polar coordinate grids in a three-dimensional space; generating polar coordinate cylinder voxels; extracting structural features from the all point cloud data in each of the polar coordinate cylinder voxels; obtaining a two-dimensional point cloud pseudo-image; boundary supplementing to the two-dimensional point cloud pseudo-image; and performing feature extraction on the two-dimensional point cloud pseudo-image by using convolutional neural networks, and outputting a final feature map.

Abstract: Disclosed are apparatus and methods for a silicon photonic (SiPh) structure comprising the integration of an electrical integrated circuit (EIC); a photonic integrated circuit (PIC) disposed on top of the EIC; two or more polymer waveguides (PWGs) disposed on top of the PIC and formed by layers of cladding polymer and core polymer; and an integration fan-out redistribution (InFO RDL) layer disposed on top of the two or more PWGs. The operation of PWGs is based on the refractive indexes of the cladding and core polymers. Inter-layer optical signals coupling is provided by edge-coupling, reflective prisms and grating coupling. A wafer-level system implements a SiPh structure die and provides inter-die signal optical interconnections among the PWGs.

Abstract: An image processing method including the following steps is provided. An image information of an image is received, wherein the image includes a plurality of blocks and the image information includes a plurality of pixel information of each block. A dual gamma correction is performed on a first group of blocks of the image to obtain one or more corrected blocks and the dual gamma correction is skipped on a second group of blocks of the image to obtain a plurality of uncorrected blocks. A first encoding process is performed on the one or more corrected blocks to obtain a plurality of first encoded blocks. A second encoding process different from the first encoding process is performed on the plurality of uncorrected blocks to obtain a plurality of second encoded blocks.

Abstract: A laterally diffused metal oxide semiconductor device can include: a well region having a second doping type; a reduced surface field effect layer of a first doping type formed by an implantation process in a predetermined region of the well region, where a length of the reduced surface field effect layer is less than a length of the well region; a body region of the first doping type extending from a top surface of the well region into the well region; a drain portion of the second doping type extending from the top surface of the well region into the well region; and an insulating structure located between the body region and the drain portion, at least a portion of the insulating structure is located on the top surface of the well region.

Abstract: A window air conditioner includes a casing including a receiving groove formed at an outer peripheral wall of the casing. The receiving groove has an open top, an open left side, and an open right side. The casing is divided into an indoor part and an outdoor part by the receiving groove. The window air conditioner further includes an indoor heat exchanger and an indoor fan arranged in the indoor part, and an outdoor heat exchanger and an outdoor fan arranged in the outdoor part.

Abstract: Circuits and methods for sensing output current of a power converter, controlling output current in multiple parallel power converters, and enabling reconfigurability of output control for multiple parallel power converters. One embodiment includes a current sensing circuit configured to be coupled to a power converter, the current sensing circuit configured to receive a first voltage representative of an output current of the power converter and output a low-frequency filtered second voltage based on the first voltage and a high-frequency filtered third voltage based on the first voltage. In some embodiments, the first voltage is generated by sensing an output current of the power converter and converting the sensed output current to the first voltage. Other embodiments include a plurality of power stages and corresponding current sensing circuits, wherein the outputs of the low-frequency filters of the current sensing circuits are coupled in common.

Abstract: A method and a system for verifying an integrated circuit stack having a silicon photonic (SIPH) device is introduced. A single first dummy layer is added to at least one terminal of the SIPH device in a first layout of the first integrated circuit, wherein a shape of the single first dummy layer added to the at least one terminal of the SIPH device maps a shape of the at least one terminal of the SIPH device. A first layout versus schematic (LVS) check is performed on the first integrated circuit based on the single first dummy layer added to the at least one terminal of the SIPH device to verify a connection of the SIPH device in the first integrated circuit.

Abstract: A bus interconnection system and a method for detecting bad routing by the same are provided. The bus interconnection system includes a master node, destination nodes, and a first order switch node. The destination nodes include slave nodes, the bus interconnection system assigns an identification symbol to each of the destination nodes, and adds a destination identification symbol to data sent to the slave nodes by the master node through the first order switch node. When the first order switch node receives the data, the first order switch node updates the destination identification symbol of the data according to a payload of the data, and when one of the destination nodes receives the data, the one of the destination nodes determines whether a bad routing occurs by checking whether the destination identification symbol is equal to the identification symbol assigned to the destination node that receives the data.

Abstract: A 6.4 Tbps silicon-based photonics engine transceiver chip module for high-speed optical communication manufactured based on processing techniques of semiconductors such as silicon-on-insulator (SOI) and indium phosphide (InP). The photonics engine transceiver chip module uses a silicon photonic chip as a substrate, and optical chips of an InP laser and an optical amplifier are heterogeneously integrated with the silicon photonic chip through bonding or flip-chip soldering. As a pump light source, the laser generates a soliton-based optical frequency comb by using an ultra-low loss silicon nitride (SiN) resonator cavity, and can be used as a multi-wavelength laser. This reduces use of a single-wavelength laser chip, reduces a power consumption and heat conduction of a laser in an optical chip of a photonic engine, and improves an integration level of an optical device. The optical frequency comb generates an optical carrier with wide bandwidth coverage and a large quantity of wavelengths.

Abstract: A light reflecting structure, a backlight module, and a display device are provided. The light reflecting structure is configured to reflect light emitted from plural light emitting units. The light reflecting structure includes a bottom portion and plural sidewall portions. The sidewall portions are erected on the bottom portion. The sidewall portions respectively and correspondingly surround the light-emitting units, and the light emitted from each of the light-emitting units can be directed to a light reflecting surface corresponding to each of the sidewall portions to be reflected outward. A distance P is defined between any two adjacent sidewall portions, and each of the sidewall portions has a height H1. The distance P and the height H1 satisfy a first inequality, and the first inequality is H1<P/2×tan ?. ? represents a complementary angle of a half light-intensity angle of each of the light-emitting units.

Abstract: A window air conditioner includes a casing and a positioning member provided at the casing and configured to be switchable between a storage state and a working state. In the storage state, the positioning member is stored at the casing. In the working state, the positioning member is at least partially outside the casing for connecting and positioning the casing with a window frame.

Abstract: A laterally diffused metal oxide semiconductor device can include: a base layer; a source region and a drain region located in the base layer; a first dielectric layer located on a top surface of the base layer and adjacent to the source region; a voltage withstanding layer located on the top surface of the base layer and located between the first dielectric layer and the drain region; a first conductor at least partially located on the first dielectric layer; a second conductor at least partially located on the voltage withstanding layer; and a source electrode electrically connected to the source region, where the first and second conductors are spatially isolated, and the source electrode at least covers a space between the first and second conductors.

Abstract: An optical circuit includes one or more input waveguides, a plurality of output waveguides, and a reflector structure. At least a portion of the reflector structure forms an interface with the one or more input waveguides. The portion of the reflector structure has a smaller refractive index than the one or more input waveguides. An electrical circuit is electrically coupled to the optical circuit. The electrical circuit generates and sends different electrical signals to the reflector structure. In response to the reflector structure receiving the different electrical signals, a carrier concentration level at or near the interface or a temperature at or near the interface changes, such that incident radiation received from the one or more input waveguides is tunably reflected by the reflector structure into a targeted output waveguide of the plurality of output waveguides.

Abstract: A photonic heater is provided. The photonic heater includes a current source and a transfer circuit. The transfer circuit connected to the current source. The photonic heater further includes a heating element. The heating element is connected to the transfer circuit. The transfer circuit is operable to regulate an amount of current being transferred from the current court to the heating element.

Abstract: Among other things, the present disclosure provides oligonucleotides and compositions thereof. In some embodiments, provided oligonucleotides and compositions are useful for adenosine modification. In some embodiments, the present disclosure provides methods for treating various conditions, disorders or diseases that can benefit from adenosine modification.