Patents by Inventor Hui Yu

Hui Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230367815
    Abstract: The present invention relates to energy-efficient collaborative method and apparatus for graph processing, wherein the apparatus comprises at least: a dependency path prefetching unit for receiving active vertex information and prefetching an edge of graph partition along a dependency path, starting with an active vertex in a circular queue; and a direct dependency managing unit for converting dependency relationship between head and tail vertices of a core dependency path into direct dependency and managing it in a cache, and updating dependency indexes according to dynamic changes in graph structure during dynamic graph processing, so as to ensure accurate results of graph processing. The accelerator of the present invention is capable of being integrated into a multi-core processor, thereby processing multiple paths on multiple processor kernels with high concurrency, and in turn accelerating dissemination of vertex states in a graph to speed convergence during graph processing.
    Type: Application
    Filed: September 15, 2022
    Publication date: November 16, 2023
    Inventors: Yu ZHANG, Jin ZHAO, Qiange SHEN, Xinyu JIANG, Hui YU, Hao QI, Yun YANG, Shijun LI, Xiaofei LIAO, Hai JIN
  • Publication number: 20230352366
    Abstract: The present disclosure describes heat dissipating structures that can be formed either in functional or non-functional areas of three-dimensional system on integrated chip structures. In some embodiments, the heat dissipating structures maintain an average operating temperature of memory dies or chips below about 90° C. For example, a structure includes a stack with chip layers, where each chip layer includes one or more chips and an edge portion. The structure further includes a thermal interface material disposed on the edge portion of each chip layer, a thermal interface material layer disposed over a top chip layer of the stack, and a heat sink over the thermal interface material layer.
    Type: Application
    Filed: July 5, 2023
    Publication date: November 2, 2023
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Po-Hsiang HUANG, Chin-chou Liu, Chin-Her Chien, Fong-yuan Chang, Hui Yu Lee
  • Patent number: 11804192
    Abstract: A display module is provided. The display module includes a main display panel, an auxiliary display panel and a backlight module which are laminated sequentially, at least one temperature sensing circuit in the auxiliary display panel, and a control circuit coupled to the at least one temperature sensing circuit. The temperature sensing circuit is configured to generate, based on temperature of the auxiliary display panel, a temperature signal related to the temperature, and the control circuit is configured to adjust a display parameter of the main display panel based on the temperature signal.
    Type: Grant
    Filed: January 25, 2022
    Date of Patent: October 31, 2023
    Assignees: Fuzhou BOE Optoelectronics Technology Co., Ltd., BOE Technology Group Co., Ltd.
    Inventors: Hui Yu, Xin Fang, Kai Diao, Jie Liu, Chengkun Liu, Xin Chen
  • Publication number: 20230343559
    Abstract: Some implementations described herein provide techniques and apparatuses for overcoming forces that may deflect an injector nozzle into an interior wall of a thin-film furnace. The implementations include a fixture that is coupled to the injector nozzle. The fixture is configurable to lock to a selected property of the injector nozzle to maintain, between a portion of the injector nozzle and the interior wall, a gap. In this way, the portion of the injector nozzle is prevented from colliding with the interior wall and dislodging particulates that may contaminate semiconductor product fabricated using the thin-film furnace.
    Type: Application
    Filed: April 21, 2022
    Publication date: October 26, 2023
    Inventors: Yi Chen HO, Chih Ping LIAO, Shih Hao YANG, Wei-Ming WANG, Chien Ting LIN, Jie-Ying YANG, Chih-Che TANG, Kuo Kang TENG, Ming-Hui YU, Ker-hsun LIAO, Chi-Hsun LIN
  • Publication number: 20230333596
    Abstract: A display module for a head-mounted display device includes a display assembly, an optical imaging assembly, and a virtual image location adjustment assembly. The display assembly is configured to display an image. The optical imaging assembly is configured to form a virtual image based on the image. The virtual image location adjustment assembly is configured to adjust at least one of the optical imaging assembly and the display assembly to adjust the virtual image to a target location. The virtual image location adjustment assembly adjusts the optical imaging assembly and/or the display assembly.
    Type: Application
    Filed: June 23, 2023
    Publication date: October 19, 2023
    Inventors: Shaorui Gao, Jushuai Wu, Weicheng Luo, Meng Qiu, Hui Yu, Yunneng Mo, Tizheng Wang
  • Publication number: 20230334872
    Abstract: Provided is a traffic sign recognition method based on a lightweight neural network, which including: a lightweight neural network model is constructed for training and pruning to obtain a lightweight neural network model; the lightweight neural network model comprises a convolution feature extraction part and a classifier part; the convolution feature extraction part includes one layer of conventional 3×3 convolution and 16 layers of separable asymmetric convolution. The classifier part includes three layers of separable full connection modules.
    Type: Application
    Filed: June 23, 2023
    Publication date: October 19, 2023
    Inventors: Jielong GUO, Xian WEI, Xuan TANG, Hui YU, Jianfeng ZHANG, Dongheng SHAO, Xiaodi YANG, Yufang XIE
  • Publication number: 20230329201
    Abstract: Among other things, the present disclosure provides cells and non-human animals engineered to express an ADAR1 polypeptide or a characteristic portion thereof. In some embodiments, the present disclosure provides cells and non-human animals engineered to express a human ADAR1 polypeptide or a characteristic portion thereof. In some embodiments, non-human animals are genetically modified rodents such as mice, rat, etc. In some embodiments, non-human animals are mice. In some embodiments, the present disclosure provides technologies for assessing an agent comprising administering the agent to a cell or non-human animal engineered to express an ADAR1 polypeptide or a characteristic portion thereof. In some embodiments, such a cell or non-human animal is engineered to express a human ADAR1 polypeptide or a characteristic portion thereof. In some embodiments, an agent is a pharmaceutical agent. In some embodiments, an agent is or comprises an oligonucleotide.
    Type: Application
    Filed: August 23, 2021
    Publication date: October 19, 2023
    Inventors: Hailin Yang, Prashant Monian, Chikdu Shakti Shivalila, Subramanian Marappan, Chandra Vargeese, Pachamuthu Kandasamy, Genliang Lu, Hui Yu, David Charles Donnell Butler, Luciano Henrique Apponi, Mamoru Shimizu, Stephany Michelle Standley, David John Boulay, Jack David Godfrey, Naoki Iwanmoto
  • Patent number: 11792923
    Abstract: A storage device of the present invention is provided to store flexible circuit packages, each of the flexible circuit packages includes an electronic component and two circuit portions warped at both sides of the electronic component, respectively. The storage device includes a first carrier and a second carrier. The first carrier includes first accommodation elements provided for placement of the flexible circuit packages, and the second carrier includes a first press portion and a second press portion. As the second carrier is placed on the first carrier, the first and second press portions are provided to press the two circuit portions warped upwardly toward the second carrier so as to reduce the warpage of the two circuit portions.
    Type: Grant
    Filed: September 9, 2021
    Date of Patent: October 17, 2023
    Assignee: CHIPBOND TECHNOLOGY CORPORATION
    Inventors: Shih-Chieh Chang, Hui-Yu Huang, Chih-Ming Peng, Chun-Te Lee
  • Patent number: 11782300
    Abstract: The present disclosure provides a display device, including: a backlight module; side frames on different sides of the display module; a first supporting part is provided on at least one side frame, and extends toward a middle part of the backlight module; a panel assembly on a light-emitting side of the backlight module and including a first display panel, a second display panel and a connection layer between the first display panel and the second display panel, where the first display panel, the second display panel and the connection layer define an accommodation space, the first supporting part extends into the accommodation space, the first display panel is on a side of the first supporting part away from the backlight module, and the second display panel is supported by the backlight module; the first display panel and the side frame overlap in a thickness direction of the display device.
    Type: Grant
    Filed: September 27, 2021
    Date of Patent: October 10, 2023
    Assignees: Fuzhou BOE Optoelectronics Technology Co., Ltd., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Yuhang Lin, Hui Yu, Liri Chen, Chengkun Liu, Han Zhang, Ming Chen, Jie Liu, Kai Diao
  • Patent number: 11783037
    Abstract: Disclosed are a defense method and a model of deep learning model aiming at adversarial attacks in the technical field of image recognition, which makes full use of the internal relationship between the adversarial samples and the initial samples, and transforms the adversarial samples into common samples by constructing a filter layer in front of the input layer of the deep learning model; the parameters of the filter layer are trained by using the adversarial attack samples, so as to improve the ability of the model to resist adversarial attack; then the trained filter layer is combined with the learning model after the adversarial training, and a deep learning model with strong robustness and high classification accuracy is obtained, which ensures that the recognition ability of the initial sample is not reduced while resisting the adversarial attacks.
    Type: Grant
    Filed: May 15, 2023
    Date of Patent: October 10, 2023
    Assignee: Quanzhou Equipment Manufacturing Research Institute
    Inventors: Jielong Guo, Xian Wei, Xuan Tang, Hui Yu, Dongheng Shao, Jianfeng Zhang, Jie Li, Yanhui Huang
  • Publication number: 20230312807
    Abstract: Disclosed are a spandex fiber with a reversible triple-shape memory effect and a preparation method thereof. In the present disclosure, the spandex fiber includes the following raw materials in parts by weight: 3 parts to 100 parts of a crystalline polyester diol or a crystalline polyether diol, 1 part to 30 parts of a diisocyanate, 0.1 parts to 15 parts of a polyurethane chain extender, and 0.2 parts to 11 parts of a polyurethane cross-linking agent, where the crystalline polyester diol or the crystalline polyether diol has a number-average molecular weight of 1,000-10,000 Daltons. The spandex fiber has a reversible deformation process, shows an ability to transform between “stretched” and “shortened” states infinitely under the action of a temperature field, and can memorize two temporary shapes. Moreover, the spandex fiber has easily accessible raw materials and a simple preparation method, and is suitable for large-scale industrial production.
    Type: Application
    Filed: June 8, 2023
    Publication date: October 5, 2023
    Applicant: Wuyi University
    Inventors: Longfei Fan, Lei Min, Hui Yu, Yuxiao Wu
  • Patent number: 11778134
    Abstract: The present invention relates to a fault detection circuit for detecting one or more column faults in a pixel array of an image sensor. The present invention further relates to a readout circuit for reading out a column line of an image sensor, and to an image sensor comprising the same. The fault detection circuit according to the invention comprises a signal unit for applying an electrical signal to a given column line of the pixel array, a determining unit for measuring a response to the applied electrical signal and for determining whether a fault exists for said given column line in dependence of the measured response, and a controller for controlling the signal unit and the determining unit, and for outputting a fault status for said given column line.
    Type: Grant
    Filed: February 24, 2021
    Date of Patent: October 3, 2023
    Assignee: TELEDYNE DALSA B.V.
    Inventors: Willem J. Kindt, Hui-Yu Chen
  • Publication number: 20230308003
    Abstract: An integrated circuit (IC) for controlling a power converter. The IC includes a controller that, in a first sensing period, enables a sensing circuit of the power converter and electrically connects an output node of an op amp of the sensing circuit and a first node of a capacitor of the sensing circuit, creating a first voltage across the capacitor; in a period between the first sensing period and a second sensing period, disables the sensing circuit and disconnects the output node of the op amp and the first node of the capacitor to maintain the first voltage across the capacitor; and in the second sensing period, enables the sensing circuit and connects the output node of the op amp and the first node of the capacitor, the maintained first voltage across the capacitor reducing a settling time for the enabled sensing circuit.
    Type: Application
    Filed: March 25, 2022
    Publication date: September 28, 2023
    Inventors: Tim Wen Hui YU, Gregory SZCZESZYNSKI
  • Patent number: 11770548
    Abstract: A method of encoding video data by an electronic device is provided. A block unit is determined from an image frame according to the video data. A line index is encoded in a bitstream based on a selected reference line of the block unit and is compared with a first predefined value to determine whether to encode a mode flag in the bitstream. A mode index is directly encoded in the bitstream for indicating a prediction mode of the block unit from a most probable mode (MPM) list of the block unit when the mode flag is not encoded. The mode flag is compared to a second predefined value for encoding the mode index when the mode flag is encoded in the bitstream to indicate whether the prediction mode is selected from the MPM list. The block unit is predicted based on the selected reference line and the prediction mode.
    Type: Grant
    Filed: July 8, 2022
    Date of Patent: September 26, 2023
    Assignee: FG Innovation Company Limited
    Inventors: Hui-Yu Jiang, Yao-Jen Chang
  • Publication number: 20230298220
    Abstract: An image processing method including the following steps is provided. An image information of an image is received, wherein the image includes a plurality of blocks and the image information includes a plurality of pixel information of each block. A dual gamma correction is performed on a first group of blocks of the image to obtain one or more corrected blocks and the dual gamma correction is skipped on a second group of blocks of the image to obtain a plurality of uncorrected blocks. A first encoding process is performed on the one or more corrected blocks to obtain a plurality of first encoded blocks. A second encoding process different from the first encoding process is performed on the plurality of uncorrected blocks to obtain a plurality of second encoded blocks.
    Type: Application
    Filed: May 24, 2023
    Publication date: September 21, 2023
    Applicant: Novatek Microelectronics Corp.
    Inventors: Hui-Yu Jiang, Heng-Yao Lin, Yen-Tao Liao
  • Publication number: 20230299052
    Abstract: An integrated circuit includes a first semiconductor wafer, a second semiconductor wafer, a first interconnect structure, a first through substrate via, and an under bump metallurgy (UBM) layer. The first semiconductor wafer has a first side of the first semiconductor wafer. The second semiconductor wafer is coupled to the first semiconductor wafer, and is over the first semiconductor wafer. The second semiconductor wafer has a first device in a first side of the second semiconductor wafer. The first interconnect structure is on a second side of the first semiconductor wafer opposite from the first side of the first semiconductor wafer. The first interconnect structure includes an inductor below the first semiconductor wafer. The first through substrate via extends through the first semiconductor wafer. The first through substrate via electrically couples the inductor to at least the first device. The UBM layer is on a surface of the first interconnect structure.
    Type: Application
    Filed: May 23, 2023
    Publication date: September 21, 2023
    Inventors: Chih-Lin CHEN, Hui-Yu LEE, Fong-Yuan CHANG, Po-Hsiang HUANG, Chin-Chou LIU
  • Patent number: 11762768
    Abstract: A device is provided that includes a first memory and a second memory and an accessing circuit. Actual addresses of the first memory and the second memory alternately correspond to reference addresses of a processing circuit. The accessing circuit is configured to perform the steps outlined below. A read command corresponding to a reference read address is received from the processing circuit to convert the reference read address to an actual read address of the first memory and the second memory. A first read data is read from a first one of the first memory and the second memory according to the actual read address and a second read data is prefetched from a second one of the first memory and a second memory according to a next first read address simultaneously.
    Type: Grant
    Filed: December 29, 2020
    Date of Patent: September 19, 2023
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Yung-Hui Yu, Chih-Wea Wang
  • Publication number: 20230286285
    Abstract: A printing fluid delivery system comprising a fluid pump having an inlet and an outlet, a valve connected to the outlet of the fluid pump, and a controller to close the valve while the fluid pump is driven to increase the pressure at the outlet of the fluid pump based on a service condition and to open the valve based on a predefined relief condition to relieve the pressure at the outlet of the fluid pump.
    Type: Application
    Filed: July 20, 2020
    Publication date: September 14, 2023
    Applicant: Hewlett-Packard Development Company, L.P.
    Inventors: Dorkaitz Alain VAZQUEZ FERNANDEZ, Alvin Zheng-Hui YU, Joan-Albert MIRAVET JIMENEZ, Albert CRESPI SERRANO
  • Publication number: 20230291483
    Abstract: A programmable two-dimensional simultaneous multi-beam optically operated phased array receiver chip is manufactured based on silicon-on-insulator (SOI) and indium phosphide (InP) semiconductor manufacturing processes, including the SiN process. The InP-based semiconductor is used for preparing a laser array chip and a semiconductor optical amplifier array chip, the SiN is used for preparing an optical power divider, and the SOI semiconductor is used for preparing a silicon optical modulator, a germanium-silicon detector, an optical wavelength multiplexer, a true delay line, and other passive optical devices. The whole integration of the receiver chip is realized through heterogeneous integration of the InP-based chip and the SOI-based chip. Simultaneous multi-beam scanning can be realized through peripheral circuit programming control.
    Type: Application
    Filed: May 16, 2023
    Publication date: September 14, 2023
    Applicant: ZHEJIANG LAB
    Inventors: Qiang ZHANG, Hui YU
  • Patent number: 11754314
    Abstract: A water receiving tray for a window air conditioner includes a tray body and a wiring body. The tray body includes a water tank. The wiring body is provided at a side of the tray body proximal to an outdoor part of the window air conditioner. The wiring body includes a wiring groove.
    Type: Grant
    Filed: June 29, 2020
    Date of Patent: September 12, 2023
    Assignees: GD MIDEA AIR-CONDITIONING EQUIPMENT CO., LTD., MIDEA GROUP CO., LTD.
    Inventors: Hui Yu, Zhigang Xing, Kangwen Zhang, Ali Zhao, Yu Liu, Wenjun Shen, Yuhang Tang