Abstract: Process to release Silicon stress in forming CMOS image sensor. In one embodiment, a method for manufacturing an image sensor includes providing a first wafer that is a semiconductor substrate, where the first wafer has a first side and a second side opposite from the first side. The method also includes attaching a second wafer to the second side of the first wafer. The method further includes forming isolation structures in the second wafer by etching. The isolation structures are bounded by the second side of the first wafer. The method also includes growing an epitaxial layer between individual isolation structures.

Abstract: A global-shutter pixel includes a semiconductor substrate that has a storage node and a photodiode region. A front surface of the substrate has a first recessed region between the photodiode region and the storage node in a first direction parallel to the front surface, and a second recessed region between the first recessed region and the storage node in the first direction. The first and second recessed regions extend into the substrate to a respective first recess-depth and a second recess-depth that exceeds the first recess-depth. The photodiode region includes (i) a first doped-section spanning a depth-range and having a first dopant concentration, and (ii) a second doped-section between the front surface and the first doped-section and having a second dopant concentration that is less than the first dopant concentration. The first doped-section includes a protrusion that extends at least partially beneath the first recessed region in the first direction.

Abstract: A pixel for an image sensor is described. The pixel comprises a photodiode and an isolation structure disposed within a semiconductor substrate and between a first and second side of the semiconductor substrate. The isolation structure includes a bottom sidewall coupled to a first sidewall and a second sidewall is the isolation structure. The isolation structure is disposed, at least in part, between a gate electrode and the second side of the semiconductor substrate. A first implant region of the semiconductor substrate is disposed proximate to the first sidewall of the isolation. The first implant region is disposed between the photodiode and the first sidewall. A first dopant concentration of the first implant region is greater than a bulk dopant concentration of the semiconductor substrate.

Abstract: An uneven-trench pixel cell includes a semiconductor substrate that includes a floating diffusion region, a photodiode region, and, between a front surface and a back surface: a first sidewall surface, a shallow bottom surface, a second sidewall surface, and a deep bottom surface. The first sidewall surface and a shallow bottom surface define a shallow trench, located between the floating diffusion region and the photodiode region, that extends into the semiconductor substrate from the front surface. A shallow depth of the shallow trench exceeds a junction depth of the floating diffusion region. The second sidewall surface and a deep bottom surface define a deep trench, located between the floating diffusion region and the photodiode region, that extends into the semiconductor substrate from the front surface. A distance between the deep bottom surface and the front surface defines a deep depth, of the deep trench, that exceeds the shallow depth.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a single diffusion cut for gate structures and methods of manufacture. The structure includes: a plurality of fin structures; a plurality of gate structures extending over the plurality of fin structures; a plurality of diffusion regions adjacent to the each of the plurality of gate structures; a single diffusion break between the diffusion regions of the adjacent gate structures; and a liner separating the single diffusion break from the diffusion regions.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to single diffusion cut for gate structures and methods of manufacture. The structure includes a single diffusion break extending into a substrate between diffusion regions of adjacent gate structures, the single diffusion break filled with an insulator material and further comprising an undercut region lined with a liner material which is between the insulator material and the diffusion regions.

Abstract: A pixel includes a semiconductor substrate, a low-? dielectric, and a photodiode region in the semiconductor substrate. The semiconductor substrate has a substrate top surface that forms a trench. The trench extends into the semiconductor substrate and has a trench depth relative to a planar region of the substrate top surface surrounding the trench. The low-? dielectric is in the trench between the trench depth and a low-? depth with respect to the planar region. The low-? depth is less than the trench depth. The photodiode region is in the semiconductor substrate and includes (i) a bottom photodiode section beneath the trench and (ii) a top photodiode section adjacent to the trench. The top photodiode section begins at a photodiode depth, with respect to the planar region, that is less than the low-? depth, and extends toward and adjoining the bottom photodiode section.

Abstract: A system and method is provided for optimizing general matrix multiplication (GEMM) on target hardware by splitting matrices to be multiplied into tiles and formulating a tiling configuration search problem for matrices to be multiplied that explores a configuration search space to identify an optimal tiling configuration that minimizes running time on the target hardware for multiplication of matrices A (m×k) and B (k×n) on the target hardware for respective configuration states as a function of matrix parameters m, k, and n, and numbers of respective nested loops for each dimension m, k, and n, respectively. The optimal tiling configuration for the target hardware is obtained by implementing a Greedy Best-First-Search (GBFS) algorithm or a Neighborhood Actor Advantage Critic (N-A2C) algorithm that optimizes the running time for multiplication of the matrices on the target hardware, and the target hardware is configured and computations are run accordingly.

Abstract: A pixel-array substrate includes (i) a semiconductor substrate including a photodiode region and a floating diffusion region, and (ii) a vertical-transfer-gate structure that includes a trench and a gate electrode. The trench is defined by a bottom surface and a sidewall surface of the substrate each located between a front substrate-surface and a back substrate-surface thereof. The trench extends into the substrate. In a cross-sectional plane perpendicular to the front substrate-surface and intersecting the floating diffusion region, the photodiode region, and the sidewall surface, (a) the trench is located between the floating diffusion region and the photodiode region, and (b) a top section of the sidewall surface is adjacent to the floating diffusion region. A gate electrode partially fills the trench such that the top section and a conductive-surface of the gate electrode in-part define a recess located between the floating diffusion region and the gate electrode.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to single diffusion cut for gate structures and methods of manufacture. The structure includes a single diffusion break extending into a substrate between diffusion regions of adjacent gate structures, the single diffusion break filled with an insulator material and further comprising an undercut region lined with a liner material which is between the insulator material and the diffusion regions.

Abstract: A pointed-trench pixel-array substrate includes a floating diffusion region and a photodiode region formed in a semiconductor substrate. The semiconductor substrate includes, between a top surface and a back surface thereof, a sidewall surface and a bottom surface defining a trench extending into the semiconductor substrate away from a planar region of the top surface surrounding the trench. In a cross-sectional plane perpendicular to the top surface and intersecting the floating diffusion region, the photodiode region, and the trench, (i) the bottom surface is V-shaped and (ii) the trench is located between the floating diffusion region and the photodiode region.

Abstract: A pixel-array substrate includes a floating diffusion region and a first photodiode formed in a semiconductor substrate. A top surface of the semiconductor substrate defines a trench 1A and a trench 1B each (i) extending into the semiconductor substrate away from a planar region of the top surface between the trench 1A and the trench 1B and (ii) having a respective distal end, with respect to the floating diffusion region, located between the floating diffusion region and the first photodiode. In a horizontal plane parallel to the top surface and along an inter-trench direction between the trench 1A and the trench 1B, a first spatial separation between the trench 1A and the trench 1B increases with increasing distance from the floating diffusion region.

Abstract: Transistors, electronic devices, and methods are provided. Transistors include a gate trench formed in a semiconductor substrate and extending to a gate trench depth, and a source and a drain formed as doped regions in the semiconductor substrate and having a first conductive type. The source and the drain are formed along a channel length direction of the transistor at a first end and a second end of the gate trench, respectively, and the source and the drain each includes a first doped region and a second doped region extending away from the first doped region. The second doped region extends to a depth in the semiconductor substrate deeper than the first doped region relative to a surface of the semiconductor substrate.

Abstract: Image sensors, isolation structures, and techniques of fabrication are provided. An image sensor includes a source of electromagnetic radiation disposed on a substrate, a pixel array disposed on the substrate and thermally coupled with source of electromagnetic radiation, and an isolation structure disposed on the substrate between the source of electromagnetic radiation and the pixel array. The isolation structure can define a first reflective surface oriented on a first bias relative to a lateral axis of the pixel array and a second reflective surface oriented on a second bias relative to the lateral axis. The isolation structure can be configured to attenuate residual electromagnetic radiation reaching a proximal region of the pixel array by pairing a first reflection and a second reflection of the electromagnetic radiation by the first reflective surface and the second reflective surface.

Abstract: A backside-illuminated image sensor includes photodiodes in photodiode regions electrically isolated by filled trenches with openings in a dielectric layer over the photodiodes. The image sensor has a metal grid aligned over the trenches, the metal grid within 80 nanometers of the trenches. The image sensor is formed by: fabricating photodiodes in photodiode regions of a frontside of a silicon substrate with source-drain regions of transistors, the photodiodes electrically isolated by deep trenches, each photodiode within a photodiode region of the substrate; forming the filled trenches in a backside of the semiconductor substrate; forming protective oxide and process stop layers over the backside of the semiconductor substrate; depositing a metal grid over the deep trenches, removing the process stop layer from over photodiode regions; and depositing color filters over the photodiode regions.

Abstract: Image sensors include a pixel array arranged about an array center, each pixel of the pixel array having a photodiode formed in a semiconductor substrate, and a central deep trench isolation structure disposed in the semiconductor substrate relative to a pixel center between the photodiode and an illuminated surface of the semiconductor substrate. If the pixel center is not coincident with the array center, then the central deep trench isolation structure is disposed at a CDTI shift distance away from the pixel center.

Abstract: A flicker-mitigating pixel-array substrate includes a semiconductor substrate and a metal annulus. The semiconductor substrate includes a small-photodiode region. A back surface of the semiconductor substrate forms a trench surrounding the small-photodiode region in a cross-sectional plane parallel to a back-surface region of the back surface above the small-photodiode region. The metal annulus (i) at least partially fills the trench, (ii) surrounds the small-photodiode region in the cross-sectional plane, and (iii) extends above the back surface. A method for fabricating a flicker-mitigating pixel-array substrate includes forming a metal layer (i) in a trench that surrounds the small-photodiode region in a cross-sectional plane parallel to a back-surface region of the back surface above the small-photodiode region and (ii) on the back-surface region. The method also includes decreasing a thickness of an above-diode section of the metal layer located above the back-surface region.

Abstract: Transistors include trenches formed in the semiconductor substrate having a first conductive type. The trenches define, in a channel width plane of the transistor, at least one nonplanar substrate structure having a plurality of sidewall portions and a tip portion disposed between the plurality of sidewall portions. An epitaxial overlayer is epitaxially grown on the sidewall portions and the tip portion. A channel doping layer having a doped portion of the semiconductor substrate is formed in the nonplanar substrate structure and enclosed by the epitaxial overlayer. An isolation layer is disposed in the trenches and over the epitaxial overlayer. A gate is disposed on the isolation layer and extends into the trenches.

Abstract: Pixels, such as for image sensors and electronic devices, include a photodiode formed in a semiconductor substrate, a floating diffusion, and a transfer structure selectively coupling the photodiode to the floating diffusion. The transfer structure includes a transfer gate formed on the semiconductor substrate, and a vertical channel structure including spaced apart first doped regions formed in the semiconductor substrate between the transfer gate and the photodiode. Each spaced apart first doped region is doped at a first dopant concentration with a first-type dopant. The spaced apart first doped regions are formed in a second doped region doped at a second dopant concentration with a second-type dopant of a different conductive type.

Abstract: A method for forming a pixel includes forming, in a semiconductor substrate, a wide trench having an upper depth with respect to a planar top surface of the semiconductor substrate. The method also includes ion-implanting a floating-diffusion region between the planar top surface and a junction depth in the semiconductor substrate. In a cross-sectional plane perpendicular to the planar top surface, the floating-diffusion region has (i) an upper width between the planar top surface and the upper depth, and (ii) between the upper depth and the junction depth, a lower width that exceeds the upper width. Part of the floating-diffusion region is beneath the wide trench and between the upper depth and the junction depth.