Patents by Inventor Hui Zang

Hui Zang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11004953
    Abstract: A method is provided for fabricating a semiconductor device structure with a short channel and long channel component having different gate dielectric layers without using lithography processes or masks. The method includes forming first and second openings having sidewalls and bottom surfaces in a dielectric layer, the first opening being narrower than the second opening. A first material layer is formed in the first and second openings. A protective layer is formed over the first material layer, wherein the protective layer covers the sidewalls and the bottom surface of the second opening. A block layer is formed to fill the second opening and cover the protective layer therein. The method further includes removing side portions of the protective layer to expose upper portions of the first material layer in the second opening. The block layer is removed from the second opening to expose the protective layer remaining in the second opening.
    Type: Grant
    Filed: June 26, 2019
    Date of Patent: May 11, 2021
    Assignee: GLOBALFOUNDRIES U.S. Inc.
    Inventors: Rinus Tek Po Lee, Hui Zang, Jiehui Shu, Hong Yu, Wei Hong
  • Patent number: 10998422
    Abstract: At least one method, apparatus and system disclosed herein involves adjusting for a misalignment of a gate cut region with respect to semiconductor processing. A plurality of fins are formed on a semiconductor substrate. A gate region is formed over a portion of the fins. The gate region comprises a first dummy gate and a second dummy gate. A gate cut region is formed over the first dummy gate. A conformal fill material is deposited into the gate cut region. At least one subsequent processing step is performed.
    Type: Grant
    Filed: December 30, 2019
    Date of Patent: May 4, 2021
    Inventors: Hui Zang, Laertis Economikos, Ruilong Xie
  • Publication number: 20210118925
    Abstract: A pixel cell includes a photodiode buried beneath a first side of semiconductor material and coupled to photogenerate image charge in response to incident light. A transfer gate is disposed over the photodiode and includes a vertical transfer gate portion extending a first distance from the first side into the semiconductor material. A floating diffusion region is disposed in the semiconductor material proximate to the transfer gate and is coupled to transfer the image charge from the photodiode toward the first side of the semiconductor material and into the floating diffusion region in response to a transfer control signal. A first pixel transistor having a first gate is disposed over the photodiode proximate to the first side of the semiconductor material. The first gate has a ring structure laterally surrounding the floating diffusion region and the transfer gate at the first side of the semiconductor material.
    Type: Application
    Filed: October 16, 2019
    Publication date: April 22, 2021
    Inventors: Hui Zang, Gang Chen
  • Patent number: 10978566
    Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to middle of line structures and methods of manufacture. The structure includes: a plurality of gate structures comprising source and/or drain metallization features; spacers on sidewalls of the gate structures and composed of a first material and a second material; and contacts in electrical contact with the source and/or drain metallization features, and separated from the gate structures by the spacers.
    Type: Grant
    Filed: January 15, 2020
    Date of Patent: April 13, 2021
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Hui Zang, Guowei Xu, Keith Tabakman, Viraj Sardesai
  • Patent number: 10971583
    Abstract: A gate cut isolation including an air gap and an IC including the same are disclosed. A method of forming the gate cut isolation may include forming an opening in a dummy gate that extends over a plurality of spaced active regions, the opening positioned between and spaced from a pair of active regions. The opening is filled with a fill material, and the dummy gate is removed. A metal gate is formed in a space vacated by the dummy gate on each side of the fill material, and the fill material is removed to form a preliminary gate cut opening. A liner is deposited in the preliminary gate cut opening, creating a gate cut isolation opening, which is then sealed by depositing a sealing layer. The sealing layer closes an upper end of the gate cut isolation opening and forms the gate cut isolation including an air gap.
    Type: Grant
    Filed: November 13, 2018
    Date of Patent: April 6, 2021
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Hong Yu, Hui Zang, Jiehui Shu
  • Patent number: 10957578
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a single diffusion break device and methods of manufacture. The structure includes a single diffusion break structure with a fill material between sidewall spacers of the single diffusion break structure and a channel oxidation below the fill material.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: March 23, 2021
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Wei Hong, Hui Zang, Hsien-Ching Lo, Zhenyu Hu, Liu Jiang
  • Patent number: 10950692
    Abstract: One device disclosed herein includes, among other things, first and second active regions, a first source/drain contact positioned above the first active region, a second source/drain contact positioned above the second active region, and a dielectric material disposed between the first and second source/drain contacts, wherein the dielectric material defines an air gap cavity positioned between the first and second source/drain contacts.
    Type: Grant
    Filed: September 4, 2018
    Date of Patent: March 16, 2021
    Assignee: GLOBALFOUNDRIES U.S. Inc.
    Inventors: Ruilong Xie, Vimal Kamineni, Shesh Mani Pandey, Hui Zang
  • Patent number: 10950610
    Abstract: Methods of forming a gate cut isolation for an SRAM include forming a first and second active nanostructures adjacent to each other and separated by a space; forming a sacrificial liner over at least a side of the first active nanostructure facing the space, causing a first distance between a remaining portion of the space and the first active nanostructure to be greater than a second distance between the remaining portion of the space and the second active nanostructure. A gate cut isolation is formed in the remaining portion of the space such that it is closer to the second active nanostructure than the first active nanostructure. The sacrificial liner is removed, and gates formed over the active nanostructures with the gates separated from each other by the gate cut isolation. An SRAM including the gate cut isolation and an IC structure including the SRAM are also included.
    Type: Grant
    Filed: July 18, 2019
    Date of Patent: March 16, 2021
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Bipul C. Paul, Ruilong Xie, Julien Frougier, Daniel Chanemougame, Hui Zang
  • Publication number: 20210066464
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a scaled gate contact and source/drain cap and methods of manufacture. The structure includes: a gate structure comprising an active region; source and drain contacts adjacent to the gate structure; a capping material over the source and drain contacts; a gate contact formed directly above the active region of the gate structure and over the capping material; a U-shape dielectric material around the gate contact, above the source and drain contacts; and a contact in direct electrical contact to the source and drain contacts.
    Type: Application
    Filed: November 13, 2020
    Publication date: March 4, 2021
    Inventors: Hui ZANG, Ruilong XIE, Jae Gon LEE
  • Patent number: 10937786
    Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to gate cut structures and methods of manufacture. The structure includes: a plurality of gate structures comprising source and drain regions and sidewall spacers comprised of different dielectric materials; and contacts connecting to the source and drain regions and isolated from the gate structures by the different dielectric materials.
    Type: Grant
    Filed: September 18, 2018
    Date of Patent: March 2, 2021
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Hui Zang, Ruilong Xie, Laertis Economikos
  • Patent number: 10937693
    Abstract: At least one method, apparatus and system disclosed herein involves forming local interconnect regions during semiconductor device manufacturing. A plurality of fins are formed on a semiconductor substrate. A gate region is over a portion of the fins. A trench silicide (TS) region is formed adjacent a portion of the gate region. The TS region comprises a first TS metal feature and a second TS metal feature. A bi-layer self-aligned contact (SAC) cap is formed over a first portion of the TS region and electrically coupled to a portion of the gate region. A portion of the bi-layer SAC cap is removed to form a first void. A first local interconnect feature is formed in the first void.
    Type: Grant
    Filed: October 2, 2018
    Date of Patent: March 2, 2021
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Ruilong Xie, Andreas Knorr, Haiting Wang, Hui Zang
  • Patent number: 10923469
    Abstract: An integrated circuit (IC) includes an active area including at least one active fin-type field effect transistor (FinFET), and a trench isolation adjacent to the active area. At least one inactive gate is positioned over the trench isolation. A vertically extending resistor body is positioned adjacent the at least one inactive gate over the trench isolation. A lower end of the resistor is below an upper surface of the trench isolation. The resistor reduces interconnect layer thickness to improve yield, and significantly reduces resistor footprint to enable scaling.
    Type: Grant
    Filed: January 10, 2019
    Date of Patent: February 16, 2021
    Assignee: GLOBALFOUNDRIES U.S. Inc.
    Inventors: Hui Zang, Guowei Xu, Jiehui Shu, Ruilong Xie, Yurong Wen, Garo J. Derderian, Shesh M. Pandey, Laertis Economikos
  • Patent number: 10911382
    Abstract: A system and method of automatically assigning a priority rank to messages. The system and method accesses a message data store and assigns a priority rank to each message. The priority rank is selected from a priority rank scale by, for each message, parsing the message for features present in the message and calculating a predicted intensity score for the message using a user-specific classifier. The classifier is trained from user training data which includes prior user messages on which a machine learning algorithm operates. The training data is labeled by scores calculated based on the actual activates performed by the user to each message. The priority rank of each message can be used to improve message processing in message processing systems.
    Type: Grant
    Filed: January 30, 2017
    Date of Patent: February 2, 2021
    Assignee: Futurewei Technologies, Inc.
    Inventors: Hui Zang, Jiangsheng Yu
  • Publication number: 20210020644
    Abstract: Methods of forming a gate cut isolation for an SRAM include forming a first and second active nanostructures adjacent to each other and separated by a space; forming a sacrificial liner over at least a side of the first active nanostructure facing the space, causing a first distance between a remaining portion of the space and the first active nanostructure to be greater than a second distance between the remaining portion of the space and the second active nanostructure. A gate cut isolation is formed in the remaining portion of the space such that it is closer to the second active nanostructure than the first active nanostructure. The sacrificial liner is removed, and gates formed over the active nanostructures with the gates separated from each other by the gate cut isolation. An SRAM including the gate cut isolation and an IC structure including the SRAM are also included.
    Type: Application
    Filed: July 18, 2019
    Publication date: January 21, 2021
    Inventors: Bipul C. Paul, Ruilong Xie, Julien Frougier, Daniel Chanemougame, Hui Zang
  • Patent number: 10896853
    Abstract: The present disclosure generally relates to semiconductor device fabrication and integrated circuits. More particularly, the present disclosure relates to replacement metal gate processes and structures for transistor devices having a short channel and a long channel component. The present disclosure also relates to processes and structures for multi-gates with dissimilar threshold voltages.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: January 19, 2021
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Jiehui Shu, Rinus Tek Po Lee, Wei Hong, Hui Zang, Hong Yu
  • Patent number: 10892338
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a scaled gate contact and source/drain cap and methods of manufacture. The structure includes: a gate structure comprising an active region; source and drain contacts adjacent to the gate structure; a capping material over the source and drain contacts; a gate contact formed directly above the active region of the gate structure and over the capping material; a U-shape dielectric material around the gate contact, above the source and drain contacts; and a contact in direct electrical contact to the source and drain contacts.
    Type: Grant
    Filed: October 24, 2018
    Date of Patent: January 12, 2021
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Hui Zang, Ruilong Xie, Jae Gon Lee
  • Patent number: 10886178
    Abstract: A device including a triple-layer EPI stack including SiGe, Ge, and Si, respectively, with Ga confined therein, and method of production thereof. Embodiments include an EPI stack including a SiGe layer, a Ge layer, and a Si layer over a plurality of fins, the EPI stack positioned between and over a portion of sidewall spacers, wherein the Si layer is a top layer capping the Ge layer, and wherein the Ge layer is a middle layer capping the SiGe layer underneath; and a Ga layer in a portion of the Ge layer between the SiGe layer and the Si layer.
    Type: Grant
    Filed: August 22, 2018
    Date of Patent: January 5, 2021
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Tek Po Rinus Lee, Annie Levesque, Qun Gao, Hui Zang, Rishikesh Krishnan, Bharat Krishnan, Curtis Durfee
  • Publication number: 20200411664
    Abstract: A method is provided for fabricating a semiconductor device structure with a short channel and long channel component having different gate dielectric layers without using lithography processes or masks. The method includes forming first and second openings having sidewalls and bottom surfaces in a dielectric layer, the first opening being narrower than the second opening. A first material layer is formed in the first and second openings. A protective layer is formed over the first material layer, wherein the protective layer covers the sidewalls and the bottom surface of the second opening. A block layer is formed to fill the second opening and cover the protective layer therein. The method further includes removing side portions of the protective layer to expose upper portions of the first material layer in the second opening. The block layer is removed from the second opening to expose the protective layer remaining in the second opening.
    Type: Application
    Filed: June 26, 2019
    Publication date: December 31, 2020
    Inventors: RINUS TEK PO LEE, HUI ZANG, JIEHUI SHU, HONG YU, WEI HONG
  • Patent number: 10879073
    Abstract: One integrated circuit product disclosed herein includes a first final gate structure for a first transistor device, a second final gate structure for a second transistor device, wherein the first and second transistor devices have a gate width that extends in a gate width direction and a gate length that extends in a gate length direction, and a gate separation structure positioned between the first and second final gate structures, the gate separation structure comprising at least one insulating material. The gate separation structure further has a substantially uniform width in the gate width direction for substantially an entire vertical height of the gate separation structure and a first side surface and a second side surface, wherein an end surface of the first final gate structure contacts the first side surface and an end surface of the second final gate structure contacts the second side surface.
    Type: Grant
    Filed: November 11, 2019
    Date of Patent: December 29, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Chanro Park, Ruilong Xie, Hui Zang, Laertis Economikos, Andre LaBonte
  • Patent number: 10879180
    Abstract: In the manufacture of a FinFET device, an isolation architecture is provided between gate and source/drain contact locations. The isolation architecture may include a low-k spacer layer and a contact etch stop layer. An upper portion of the isolation architecture is removed and replaced with a high-k, etch-selective spacer layer adapted to resist degradation during an etch to open the source/drain contact locations. The high-k spacer layer, in conjunction with a self-aligned contact (SAC) capping layer disposed over the gate and overlapping a sidewall of the isolation layer, forms an improved isolation structure that inhibits short circuits or parasitic capacitance between the gate and source/drain contacts.
    Type: Grant
    Filed: November 28, 2017
    Date of Patent: December 29, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Hui Zang, Guowei Xu, Scott Beasor, Ruilong Xie