Patents by Inventor Hui Zang

Hui Zang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10892338
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a scaled gate contact and source/drain cap and methods of manufacture. The structure includes: a gate structure comprising an active region; source and drain contacts adjacent to the gate structure; a capping material over the source and drain contacts; a gate contact formed directly above the active region of the gate structure and over the capping material; a U-shape dielectric material around the gate contact, above the source and drain contacts; and a contact in direct electrical contact to the source and drain contacts.
    Type: Grant
    Filed: October 24, 2018
    Date of Patent: January 12, 2021
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Hui Zang, Ruilong Xie, Jae Gon Lee
  • Patent number: 10886178
    Abstract: A device including a triple-layer EPI stack including SiGe, Ge, and Si, respectively, with Ga confined therein, and method of production thereof. Embodiments include an EPI stack including a SiGe layer, a Ge layer, and a Si layer over a plurality of fins, the EPI stack positioned between and over a portion of sidewall spacers, wherein the Si layer is a top layer capping the Ge layer, and wherein the Ge layer is a middle layer capping the SiGe layer underneath; and a Ga layer in a portion of the Ge layer between the SiGe layer and the Si layer.
    Type: Grant
    Filed: August 22, 2018
    Date of Patent: January 5, 2021
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Tek Po Rinus Lee, Annie Levesque, Qun Gao, Hui Zang, Rishikesh Krishnan, Bharat Krishnan, Curtis Durfee
  • Publication number: 20200411664
    Abstract: A method is provided for fabricating a semiconductor device structure with a short channel and long channel component having different gate dielectric layers without using lithography processes or masks. The method includes forming first and second openings having sidewalls and bottom surfaces in a dielectric layer, the first opening being narrower than the second opening. A first material layer is formed in the first and second openings. A protective layer is formed over the first material layer, wherein the protective layer covers the sidewalls and the bottom surface of the second opening. A block layer is formed to fill the second opening and cover the protective layer therein. The method further includes removing side portions of the protective layer to expose upper portions of the first material layer in the second opening. The block layer is removed from the second opening to expose the protective layer remaining in the second opening.
    Type: Application
    Filed: June 26, 2019
    Publication date: December 31, 2020
    Inventors: RINUS TEK PO LEE, HUI ZANG, JIEHUI SHU, HONG YU, WEI HONG
  • Patent number: 10879073
    Abstract: One integrated circuit product disclosed herein includes a first final gate structure for a first transistor device, a second final gate structure for a second transistor device, wherein the first and second transistor devices have a gate width that extends in a gate width direction and a gate length that extends in a gate length direction, and a gate separation structure positioned between the first and second final gate structures, the gate separation structure comprising at least one insulating material. The gate separation structure further has a substantially uniform width in the gate width direction for substantially an entire vertical height of the gate separation structure and a first side surface and a second side surface, wherein an end surface of the first final gate structure contacts the first side surface and an end surface of the second final gate structure contacts the second side surface.
    Type: Grant
    Filed: November 11, 2019
    Date of Patent: December 29, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Chanro Park, Ruilong Xie, Hui Zang, Laertis Economikos, Andre LaBonte
  • Patent number: 10879180
    Abstract: In the manufacture of a FinFET device, an isolation architecture is provided between gate and source/drain contact locations. The isolation architecture may include a low-k spacer layer and a contact etch stop layer. An upper portion of the isolation architecture is removed and replaced with a high-k, etch-selective spacer layer adapted to resist degradation during an etch to open the source/drain contact locations. The high-k spacer layer, in conjunction with a self-aligned contact (SAC) capping layer disposed over the gate and overlapping a sidewall of the isolation layer, forms an improved isolation structure that inhibits short circuits or parasitic capacitance between the gate and source/drain contacts.
    Type: Grant
    Filed: November 28, 2017
    Date of Patent: December 29, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Hui Zang, Guowei Xu, Scott Beasor, Ruilong Xie
  • Patent number: 10879171
    Abstract: One illustrative integrated circuit product disclosed herein includes a vertically oriented semiconductor (VOS) structure positioned above a semiconductor substrate, a conductive silicide vertically oriented e-fuse positioned along at least a portion of a vertical height of the VOS structure wherein the conductive silicide vertically oriented e-fuse comprises a metal silicide material that extends through at least a portion of an entire lateral width of the VOS structure, and a conductive metal silicide region in the semiconductor substrate that is conductively coupled to the conductive silicide vertically oriented e-fuse.
    Type: Grant
    Filed: September 23, 2019
    Date of Patent: December 29, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Chun Yu Wong, Kwan-Yong Lim, Seong Yeol Mun, Jagar Singh, Hui Zang
  • Publication number: 20200402861
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to middle of line structures and methods of manufacture. The structure includes: a plurality of gate structures; source and drain regions adjacent to respective gate structures of the plurality of gate structures; metallization features contacting selected source and drain regions; and recessed metallization features contacting other selected source and drain regions.
    Type: Application
    Filed: September 4, 2020
    Publication date: December 24, 2020
    Inventors: Hui ZANG, Ruilong XIE
  • Patent number: 10872979
    Abstract: An integrated circuit product is disclosed that includes a transistor device that includes a final gate structure, a gate cap, a low-k sidewall spacer positioned on and in contact with opposing sidewalls of the final gate structure, first and second contact etch stop layers (CESLs) located on opposite sides of the final gate structure, whereby the CESLs are positioned on and in contact with the low-k sidewall spacer, and a high-k spacer located on opposite sides of the final gate structure, wherein the high-k spacer is positioned in recesses formed in an upper portion of the CESLs.
    Type: Grant
    Filed: January 30, 2020
    Date of Patent: December 22, 2020
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Hui Zang, Chung Foong Tan, Guowei Xu, Haiting Wang, Yue Zhong, Ruilong Xie, Tek Po Rinus Lee, Scott Beasor
  • Publication number: 20200395356
    Abstract: The present disclosure generally relates to semiconductor devices and processing. The present disclosure also relates to semiconductor structures disposed over active regions, more particularly, via contact structures disposed over such active regions and to methods of forming such semiconductor structures.
    Type: Application
    Filed: June 11, 2019
    Publication date: December 17, 2020
    Inventors: JIEHUI SHU, HUI ZANG
  • Publication number: 20200388707
    Abstract: The present disclosure generally relates to semiconductor device fabrication and integrated circuits. More particularly, the present disclosure relates to replacement metal gate processes and structures for multi-gate transistor devices having a short channel and a long channel component.
    Type: Application
    Filed: June 6, 2019
    Publication date: December 10, 2020
    Inventors: YANPING SHEN, XIAOXIAO ZHANG, SHESH MANI PANDEY, HUI ZANG
  • Publication number: 20200357647
    Abstract: Structures for a field effect-transistor and methods of forming a structure for a field-effect transistor. A gate electrode arranged adjacent to an outer sidewall spacer and an inner sidewall spacer. The gate electrode has a top surface that is recessed relative to the outer sidewall spacer and the inner sidewall spacer. A gate cap includes a first section of a first width arranged over the first section of the gate electrode and a second section of a second width arranged over the first section of the gate cap and the inner sidewall spacer. The second width is greater than the first width, and the inner sidewall spacer is composed of a low-k dielectric material.
    Type: Application
    Filed: May 9, 2019
    Publication date: November 12, 2020
    Inventors: Yanping Shen, Haiting Wang, Hui Zang
  • Patent number: 10833171
    Abstract: Disclosed is a transistor that includes a sidewall spacer positioned adjacent a sidewall of a gate structure, wherein the sidewall spacer comprises a notch proximate the lower end and wherein the notch is defined by a substantially vertically oriented side surface and a substantially horizontally oriented upper surface. An epi cavity in the substrate includes a substantially vertically oriented cavity sidewall that is substantially vertically aligned with the substantially vertically oriented side surface of the notch and an epi semiconductor material positioned in the epi cavity and in the notch, wherein the epi semiconductor material contacts and engages the substantially vertically oriented side surface of the notch and the substantially horizontally oriented upper surface of the notch.
    Type: Grant
    Filed: April 16, 2019
    Date of Patent: November 10, 2020
    Inventors: Yanping Shen, Jiehui Shu, Hui Zang
  • Patent number: 10832967
    Abstract: Device structures and fabrication methods for a field-effect transistor. A semiconductor fin includes a first section and a second section in a lengthwise arrangement, a first gate structure overlapping the first section of the semiconductor fin, and a second gate structure overlapping the second section of the semiconductor fin. A pillar is arranged in the first section of the semiconductor fin. The pillar extends through a height of the semiconductor fin and across a width of the semiconductor fin.
    Type: Grant
    Filed: August 13, 2018
    Date of Patent: November 10, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Hui Zang, Ruilong Xie, Garo Jacques Derderian
  • Patent number: 10825913
    Abstract: A method, apparatus, and manufacturing system are disclosed for a fin field effect transistor having a reduced parasitic capacitance between a gate and a source/drain contact. In one embodiment, we disclose a semiconductor device including first and second fins; an isolation structure between the fins; first and second metal gates; a first dielectric body under the first metal gate and on the substrate between the first fin and the second fin, wherein a top of the first dielectric body is below a top of the first metal gate; and a second dielectric body in the second metal gate and on the substrate between the first fin and the second fin, wherein a top of the second dielectric body is at or above a top of the second metal gate.
    Type: Grant
    Filed: September 27, 2018
    Date of Patent: November 3, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Hui Zang, Haiting Wang, Ruilong Xie
  • Patent number: 10825741
    Abstract: One illustrative IC product disclosed herein includes an isolation structure that separates a fin into a first fin portion and a second fin portion, an epi semiconductor material positioned on the first fin portion in a source/drain region of a transistor device, wherein a lateral gap is present between a first sidewall of the epi semiconductor material and a second sidewall of the SDB isolation structure, and a conductive source/drain structure that is conductively coupled to the epi semiconductor material, wherein a gap portion of the conductive source/drain structure is positioned in the gap and physically contacts the first sidewall and the second sidewall.
    Type: Grant
    Filed: November 20, 2018
    Date of Patent: November 3, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Hui Zang, Ruilong Xie
  • Patent number: 10825910
    Abstract: Structures for field effect-transistors and methods of forming field-effect transistors. A gate structure includes a gate electrode and a gate dielectric layer that are arranged between a first sidewall spacer and a second sidewall spacer. The gate structure has a top surface that is recessed relative to the first and second sidewall spacers. A gate cap is arranged over a section of the gate structure and over the first and sidewall spacers. The gate cap has a first section of a first width arranged over the section of the gate structure and a second section of a second width arranged over the section of the gate cap, the first sidewall spacer, and the second sidewall spacer. A dielectric liner is arranged between the gate cap and the gate structure, between the gate cap and the first sidewall spacer, and between the gate cap and the second sidewall spacer.
    Type: Grant
    Filed: April 17, 2019
    Date of Patent: November 3, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Hui Zang, Shesh Mani Pandey
  • Patent number: 10825897
    Abstract: One illustrative method disclosed herein may include forming a first straight sidewall spacer adjacent a gate structure of a transistor, forming a recessed layer of sacrificial material adjacent the first straight sidewall spacer and forming a second straight sidewall spacer on a portion of the outer surface of the first straight sidewall spacer and above the recessed layer of sacrificial material. The method may also include removing the recessed layer of sacrificial material so as to expose a first vertical portion of the outer surface of the first straight sidewall spacer and forming an epi material on and above the substrate, wherein an edge of the epi material engages the first straight sidewall spacer.
    Type: Grant
    Filed: January 30, 2019
    Date of Patent: November 3, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Wei Hong, George R. Mulfinger, Hui Zang, Liu Jiang, Zhenyu Hu
  • Publication number: 20200343142
    Abstract: The present disclosure generally relates to semiconductor device fabrication and integrated circuits. More particularly, the present disclosure relates to replacement metal gate processes and structures for transistor devices having a short channel and a long channel component. The present disclosure also relates to processes and structures for multi-gates with dissimilar threshold voltages.
    Type: Application
    Filed: April 29, 2019
    Publication date: October 29, 2020
    Inventors: JIEHUI SHU, RINUS TEK PO LEE, WEI HONG, HUI ZANG, HONG YU
  • Patent number: 10818659
    Abstract: Processes form integrated circuit apparatuses that include parallel fins, wherein the fins are patterned in a first direction, and parallel gate structures intersect the fins in a second direction perpendicular to the first direction. Also, source/drain structures are positioned on the fins between the gate structures, source/drain contacts are positioned on the source/drain structures, sidewall insulators are positioned between the gate structures and the source/drain contacts (wherein the sidewall insulators have a lower portion adjacent to the fins and an upper portion distal to the fins), and upper sidewall spacers are positioned between the upper portion of the sidewall insulators and the source/drain contacts.
    Type: Grant
    Filed: October 16, 2018
    Date of Patent: October 27, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Haiting Wang, Hui Zang, Guowei Xu, Scott Beasor
  • Patent number: 10818498
    Abstract: Structures for a field effect-transistor and methods of forming a structure for a field-effect transistor. A gate electrode arranged adjacent to an outer sidewall spacer and an inner sidewall spacer. The gate electrode has a top surface that is recessed relative to the outer sidewall spacer and the inner sidewall spacer. A gate cap includes a first section of a first width arranged over the first section of the gate electrode and a second section of a second width arranged over the first section of the gate cap and the inner sidewall spacer. The second width is greater than the first width, and the inner sidewall spacer is composed of a low-k dielectric material.
    Type: Grant
    Filed: May 9, 2019
    Date of Patent: October 27, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Yanping Shen, Haiting Wang, Hui Zang