Patents by Inventor Hui Zang

Hui Zang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10763176
    Abstract: One illustrative device disclosed includes a gate structure and a sidewall spacer positioned adjacent the gate structure, the sidewall spacer having an upper surface, wherein an upper portion of the gate structure is positioned above a level of the upper surface of the sidewall spacer. In this illustrative example, the device also includes a tapered upper surface on the upper portion of the gate structure and a gate cap, the gate cap being positioned above the tapered upper surface of the gate structure and above the upper surface of the sidewall spacer.
    Type: Grant
    Filed: October 30, 2019
    Date of Patent: September 1, 2020
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Hui Zang, Scott Beasor, Haiting Wang
  • Patent number: 10756184
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to faceted epitaxial source/drain regions and methods of manufacture. The structure includes: a gate structure over a substrate; an L-shaped sidewall spacer located on sidewalls of the gate structure and extending over the substrate adjacent to the gate structure; and faceted diffusion regions on the substrate, adjacent to the L-shaped sidewall spacer.
    Type: Grant
    Filed: November 5, 2018
    Date of Patent: August 25, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: George R. Mulfinger, Timothy J. McArdle, Judson R. Holt, Steffen A. Sichler, Ömür I. Aydin, Wei Hong, Yi Qi, Hui Zang, Liu Jiang
  • Patent number: 10741451
    Abstract: Processes form integrated circuit apparatuses that include parallel fins, wherein the fins are patterned in a first direction. Parallel gate structures intersect the fins in a second direction perpendicular to the first direction, wherein the gate structures have a lower portion adjacent to the fins and an upper portion distal to the fins. Source/drain structures are positioned on the fins between the gate structures. Source/drain contacts are positioned on the source/drain structures and multiple insulator layers are positioned between the gate structures and the source/drain contacts. Additional upper sidewall spacers are positioned between the upper portion of the gate structures and the multiple insulator layers.
    Type: Grant
    Filed: October 3, 2018
    Date of Patent: August 11, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Hui Zang, Laertis Economikos, Shesh Mani Pandey, Chanro Park, Ruilong Xie
  • Patent number: 10741656
    Abstract: This disclosure is directed to an integrated circuit (IC) structure. The IC structure may include a semiconductor substrate having a first fin and a second fin spaced from the first fin; a first source/drain region in the first fin, the first source/drain region encompassing a top surface and two opposing lateral sides of the first fin; a second source/drain region in the second fin, the second source/drain encompassing a top surface and two opposing lateral sides of the second fin; and a metal contact extending over the first source/drain region and the second source/drain region and surrounding the top surface and at least a portion of the two opposing lateral sides of each of the first and the second source/drain regions.
    Type: Grant
    Filed: September 4, 2018
    Date of Patent: August 11, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Hui Zang, Ruilong Xie, Shesh M. Pandey, Laertis Economikos
  • Publication number: 20200251377
    Abstract: Structures that include a field effect-transistor and methods of forming a structure that includes a field-effect transistor. A semiconductor fin has an upper portion and a lower portion, and a trench isolation region surrounds the lower portion of the semiconductor fin. The trench isolation region has a top surface arranged above the lower portion of the semiconductor fin and arranged below the upper portion of the semiconductor fin. A dielectric layer arranged over the top surface of the trench isolation region. The dielectric layer is composed of a low-k dielectric material.
    Type: Application
    Filed: January 31, 2019
    Publication date: August 6, 2020
    Inventors: Haiting Wang, Guowei Xu, Hui Zang, Yue Zhong
  • Patent number: 10734233
    Abstract: In the manufacture of a FinFET device, an isolation architecture is provided between gate and source/drain contact locations. The isolation architecture may include a low-k spacer layer and a contact etch stop layer. The isolation architecture further includes a high-k, etch-selective layer that is adapted to resist degradation during an etch to open the source/drain contact locations. The high-k layer, in conjunction with a self-aligned contact (SAC) capping layer disposed over the gate, forms an improved isolation structure that inhibits short circuits or parasitic capacitance between the gate and source/drain contacts.
    Type: Grant
    Filed: February 22, 2018
    Date of Patent: August 4, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Hui Zang, Guowei Xu, Keith Tabakman
  • Publication number: 20200243645
    Abstract: One illustrative method disclosed herein may include forming a first straight sidewall spacer adjacent a gate structure of a transistor, forming a recessed layer of sacrificial material adjacent the first straight sidewall spacer and forming a second straight sidewall spacer on a portion of the outer surface of the first straight sidewall spacer and above the recessed layer of sacrificial material. The method may also include removing the recessed layer of sacrificial material so as to expose a first vertical portion of the outer surface of the first straight sidewall spacer and forming an epi material on and above the substrate, wherein an edge of the epi material engages the first straight sidewall spacer.
    Type: Application
    Filed: January 30, 2019
    Publication date: July 30, 2020
    Inventors: Wei Hong, George R. Mulfinger, Hui Zang, Liu Jiang, Zhenyu Hu
  • Publication number: 20200243643
    Abstract: One illustrative integrated circuit product disclosed herein includes a single diffusion break (SDB) isolation structure positioned between a first fin portion and a second fin portion, wherein the first fin portion comprises a first end surface and the second fin portion comprises a second end surface. In this example, the SDB structure includes a conformal liner layer that engages the first end surface of the first fin portion and the second end surface of the second fin portion, an insulating material positioned on the conformal liner layer, a cap structure positioned above an upper surface of the insulating material and an air gap positioned between a bottom surface of the cap structure and the upper surface of the insulating material.
    Type: Application
    Filed: January 24, 2019
    Publication date: July 30, 2020
    Inventors: Hong Yu, Jiehui Shu, Hui Zang
  • Publication number: 20200243646
    Abstract: One illustrative method disclosed herein may include forming a first straight sidewall spacer adjacent a gate structure of a transistor, forming a second straight sidewall spacer on the first straight sidewall spacer and forming a recessed layer of sacrificial material adjacent the second straight sidewall spacer such that the recessed layer of sacrificial material covers an outer surface of a first vertical portion of the second straight sidewall spacer while exposing a second vertical portion of the second straight sidewall spacer. In this example, the method may also include removing the second vertical portion of the second straight sidewall spacer, removing the recessed layer of sacrificial material and forming an epi material such that an edge of the epi material engages the outer surface of the first vertical portion of the second straight sidewall spacer.
    Type: Application
    Filed: January 30, 2019
    Publication date: July 30, 2020
    Inventors: Wei Hong, George R. Mulfinger, Hui Zang, Liu Jiang, Zhenyu Hu
  • Patent number: 10727067
    Abstract: Methods of forming a structure that includes a field-effect transistor and structures that include a field effect-transistor. A cut is formed that extends through a gate structure of the field-effect transistor such that a gate electrode of the gate structure is divided into a first section having a first surface and a second section having a second surface spaced across the cut from the first surface. After forming the cut, a first section of a conductive layer is selectively deposited on the first surface of the first section of the gate electrode and a second section of the conductive layer is selectively deposited on the second surface of the second section of the gate electrode to shorten the cut. A dielectric material is deposited in the cut between the first and second sections of the conductive layer on the first and second surfaces of the gate electrode to form a dielectric pillar.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: July 28, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Hui Zang, David P. Brunco
  • Patent number: 10727136
    Abstract: Methods of forming cross-coupling contacts for field-effect transistors and structures for field effect-transistors that include cross-coupling contacts. A dielectric cap is formed over a gate structure and a sidewall spacer adjacent to a sidewall of the gate structure. A portion of the dielectric cap is removed from over the sidewall spacer and the gate structure to expose a first portion of the gate electrode of the gate structure at a top surface of the gate structure. The sidewall spacer is then recessed relative to the gate structure to expose a portion of the gate dielectric layer at the sidewall of the gate structure, which is removed to expose a second portion of the gate electrode of the gate structure. A cross-coupling contact is formed that connects the first and second portions of the gate electrode of the gate structure with an epitaxial semiconductor layer adjacent to the sidewall spacer.
    Type: Grant
    Filed: November 9, 2018
    Date of Patent: July 28, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Hui Zang, Ruilong Xie, Chanro Park, Laertis Economikos
  • Publication number: 20200227323
    Abstract: A method of fabricating a semiconductor device is provided, which includes providing sacrificial gate structures over a plurality of fins, wherein the sacrificial gate structures include a first sacrificial gate structure and a second sacrificial gate structure. A fin cut process is performed to form a fin cut opening in the first sacrificial gate structure. A gate cut process is performed to form a gate cut opening in the second sacrificial gate structure. A first dielectric layer is deposited in the fin cut opening and the gate cut opening, and the first dielectric layer is recessed in the openings. A second dielectric layer is deposited over the first dielectric layer in the fin cut opening and the gate cut opening to concurrently form a diffusion break structure and a gate cut structure respectively.
    Type: Application
    Filed: January 13, 2019
    Publication date: July 16, 2020
    Inventors: HUI ZANG, RUILONG XIE, JESSICA MARY DECHENE
  • Publication number: 20200227404
    Abstract: An integrated circuit (IC) includes an active area including at least one active fin-type field effect transistor (FinFET), and a trench isolation adjacent to the active area. At least one inactive gate is positioned over the trench isolation. A vertically extending resistor body is positioned adjacent the at least one inactive gate over the trench isolation. A lower end of the resistor is below an upper surface of the trench isolation. The resistor reduces interconnect layer thickness to improve yield, and significantly reduces resistor footprint to enable scaling.
    Type: Application
    Filed: January 10, 2019
    Publication date: July 16, 2020
    Inventors: Hui Zang, Guowei Xu, Jiehui Shu, Ruilong Xie, Yurong Wen, Garo J. Derderian, Shesh M. Pandey, Laertis Economikos
  • Patent number: 10714577
    Abstract: Structures for a field-effect transistor and methods for fabricating a structure for a field-effect transistor. First and second device structure are respectively formed in first and second device regions, and a first dielectric layer is formed over the first and second device regions. The first dielectric layer includes a recess defining a step at a transition between the first and second device regions, and a second dielectric layer is arranged within the recess in the first dielectric layer. A third dielectric layer is arranged over the first dielectric layer in the first device region and over the second dielectric layer in the second device region. A contact, which is coupled with the second device structure, extends through the first, second, and third dielectric layers in the second device region.
    Type: Grant
    Filed: October 2, 2018
    Date of Patent: July 14, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Wei Hong, Hui Zang, Hsien-Ching Lo
  • Patent number: 10714591
    Abstract: One illustrative transistor device disclosed herein includes a final gate structure that includes a gate insulation layer comprising a high-k material and a conductive gate, wherein the gate structure has an axial length in a direction that corresponds to a gate width direction of the transistor device. The device also includes a sidewall spacer contacting opposing lateral sidewalls of the final gate structure and a pillar structure (comprised of a pillar material) positioned above at least a portion of the final gate structure, wherein, when the pillar structure is viewed in a cross-section taken through the pillar structure in a direction that corresponds to the gate width direction of the transistor device, the pillar structure comprises an outer perimeter and wherein a layer of the high-k material is positioned around the entire outer perimeter of the pillar material.
    Type: Grant
    Filed: January 30, 2020
    Date of Patent: July 14, 2020
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Ruilong Xie, Youngtag Woo, Hui Zang
  • Patent number: 10707207
    Abstract: A semiconductor device, comprising first and second sets of fins; first and second gate electrodes; first and second isolation structures each separating one of the gate electrodes into a first portion and a second portion; and first and second conductive structures wider than the corresponding isolation structure and disposed on an entirety of a top of the corresponding isolation structure and on a part of the top of each of the first and second portions of the corresponding gate electrode. A method for making the semiconductor device. A system configured to implement the method and manufacture the semiconductor device. The semiconductor device may have a low parasitic capacitance and high chip performance.
    Type: Grant
    Filed: February 15, 2019
    Date of Patent: July 7, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Hui Zang, Dali Shao
  • Patent number: 10707303
    Abstract: A semiconductor device, comprising a semiconductor substrate; an isolation layer disposed on the semiconductor substrate; a first active region and a second active region disposed at least partially above the isolation layer; a first gate structure and a second gate structure disposed on the isolation layer, the first active region, and the second active region; and an isolation pillar disposed on the isolation layer, between the first and second active regions, and between and in contact with the first and second gate structures, wherein the isolation pillar has an inverted-T shape. A method for making the semiconductor device. A system configured to implement the method and manufacture the semiconductor device.
    Type: Grant
    Filed: January 31, 2019
    Date of Patent: July 7, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Haiting Wang, Hui Zang, Zhenyu Owen Hu
  • Patent number: 10707206
    Abstract: A method of forming a gate cut isolation, a related structure and IC are disclosed. The method forms a dummy gate material mandrel having a sidewall positioned between and spaced from a first active region covered by the mandrel and a second active region not covered by the mandrel. A gate cut dielectric layer is formed against the sidewall of the mandrel, and may be trimmed. A dummy gate material may deposited to encase the remaining gate cut dielectric layer. Subsequent dummy gate formation and replacement metal gate processing forms a gate conductor with the gate cut isolation electrically isolating respective first and second portions of the gate conductor. The method creates a very thin, slightly non-vertical gate cut isolation, and eliminates the need to define a gate cut critical dimension or fill a small gate cut opening.
    Type: Grant
    Filed: November 19, 2018
    Date of Patent: July 7, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Hui Zang, Laertis Economikos, Ruilong Xie
  • Publication number: 20200211903
    Abstract: The present disclosure generally relates to semiconductor device fabrication and integrated circuits. More particularly, the present disclosure relates to methods of forming a two-part trench in a semiconductor device that includes one or more field-effect transistors (FETs). The present method includes forming a semiconductor layer above a substrate, forming a mask layer above the semiconductor layer, forming a mask opening with sidewalls in the mask layer and exposing the semiconductor layer, depositing a profile control layer on the sidewalls of the mask opening, and forming a trench in the semiconductor layer by simultaneously etching the profile control layer and the exposed semiconductor layer, where the etching of the profile control layer forms the trench with top and bottom sections having different widths.
    Type: Application
    Filed: January 2, 2019
    Publication date: July 2, 2020
    Inventors: JIEHUI SHU, JESSICA MARY DECHENE, HUI ZANG, NAVED AHMED SIDDIQUI
  • Patent number: 10699942
    Abstract: Methods and structures that include a vertical-transport field-effect transistor. First and second semiconductor fins are formed that project vertically from a bottom source/drain region. A first gate stack section is arranged to wrap around a portion of the first semiconductor fin, and a second gate stack section is arranged to wrap around a portion of the second semiconductor fin. The first gate stack section is covered with a placeholder structure. After covering the first gate stack section with the placeholder structure, a metal gate capping layer is deposited on the second gate stack section. After depositing the metal gate capping layer on the second gate stack section, the placeholder structure is replaced with a contact that is connected with the first gate stack section.
    Type: Grant
    Filed: April 24, 2018
    Date of Patent: June 30, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Ruilong Xie, Chanro Park, Daniel Chanemougame, Steven Soss, Lars Liebmann, Hui Zang, Shesh Mani Pandey