Patents by Inventor Hui Zang

Hui Zang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Isolation pillar first gate structures and methods of forming same
    Patent number: 10600914
    Abstract: A method of forming isolation pillars for a gate structure, the method including: providing a preliminary structure including a substrate having a plurality of fins thereon, an STI formed between adjacent fins, an upper surface of the STIs extending higher than an upper surface of the fins, and a hardmask over the upper surface of the fins and between adjacent STIs; forming a first trench in a first selected STI and between adjacent fins in a gate region, and forming a second trench in a second selected STI and between adjacent fins in a TS region; and filling the first and second trenches with an isolation fill thereby forming a first isolation pillar in the gate region and a second isolation pillar in the TS region, the first and second isolation pillars extending below the upper surface of the STIs.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: March 24, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Wei Zhao, Ming Hao Tang, Haiting Wang, Rui Chen, Yuping Ren, Hui Zang, Scott H. Beasor, Ruilong Xie
  • Methods for chamfering work function material layers in gate cavities having varying widths
    Patent number: 10600876
    Abstract: A method includes forming a first cavity having a first width and a second cavity having a second width greater than the first width in a dielectric material, forming a first conformal layer in the first and second cavities, forming spacers in the first and second cavities, the spacers covering a first portion of the first conformal layer positioned on sidewalls of the first and second cavities and exposing a second portion of the first conformal layer positioned on the sidewalls of the first and second cavities, forming a material layer in the first and second cavities to cover bottom portions of the first conformal layer, performing a first etch process to remove the second portion of the first conformal layer positioned on the sidewalls of the first and second cavities, removing the spacers and the material layer, and forming a fill material in the first and second cavities.
    Type: Grant
    Filed: May 8, 2018
    Date of Patent: March 24, 2020
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Guowei Xu, Hui Zang, Rongtao Lu
  • GATE CUT STRUCTURES
    Publication number: 20200091143
    Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to gate cut structures and methods of manufacture. The structure includes: a plurality of gate structures comprising source and drain regions and sidewall spacers comprised of different dielectric materials; and contacts connecting to the source and drain regions and isolated from the gate structures by the different dielectric materials.
    Type: Application
    Filed: September 18, 2018
    Publication date: March 19, 2020
    Inventors: Hui ZANG, Ruilong XIE, Laertis ECONOMIKOS
  • Integrated circuits having converted self-aligned epitaxial etch stop
    Patent number: 10593757
    Abstract: Methods form an integrated circuit structure that includes complementary transistors on a first layer. An isolation structure is between the complementary transistors. Each of the complementary transistors includes source/drain regions and a gate conductor between the source/drain regions, and insulating spacers are between the gate conductor and the source/drain regions in each of the complementary transistors. With these methods and structures, an etch stop layer is formed only on the source/drain regions.
    Type: Grant
    Filed: April 25, 2018
    Date of Patent: March 17, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Jiehui Shu, Ruilong Xie, Hui Zang, Haiting Wang
  • OXIDE SPACER IN A CONTACT OVER ACTIVE GATE FINFET AND METHOD OF PRODUCTION THEREOF
    Publication number: 20200083363
    Abstract: A device including oxide spacer in a contact over active gates (COAG) and method of production thereof. Embodiments include first gate structures over a fin of a substrate and second gate structures, each over an outer portion of the fin and a shallow trench isolation (STI) layer adjacent to the fin; a first raised source/drain (RSD) in a portion of the fin between the first gate structures and a second RSD in the portion of the fin between the first and second gate structures; a metal liner over the first and second RSD and on sidewall portions of the first and second gate structures; a metal layer over the metal liner; and an interlayer dielectric (ILD) over the metal liner and portions of the first and second gate structures.
    Type: Application
    Filed: September 10, 2018
    Publication date: March 12, 2020
    Inventors: Hui ZANG, Laertis ECONOMIKOS, Jiehui SHU, Ruilong XIE
  • Hybrid fin cut with improved fin profiles
    Patent number: 10586736
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a hybrid fin cut with improved fin profiles and methods of manufacture. The structure includes: a plurality of fin structures in a first region of a first density of fin structures; a plurality of fin structures in a second region of a second density of fin structures; and a plurality of fin structures in a third region of a third density of fin structures. The first density, second density and third density of fin structures are different densities of fin structures, and the plurality of fin structures in the first region, the second region and the third region have a substantially uniform profile.
    Type: Grant
    Filed: June 11, 2018
    Date of Patent: March 10, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Haiting Wang, Ruilong Xie, Shesh Mani Pandey, Hui Zang, Garo Jacques Derderian, Scott Beasor
  • Method of manufacturing finfet devices using narrow and wide gate cut openings in conjunction with a replacement metal gate process
    Patent number: 10586860
    Abstract: In conjunction with a replacement metal gate (RMG) process for forming a fin field effect transistor (FinFET), gate isolation methods and associated structures leverage the formation of distinct narrow and wide gate cut regions in a sacrificial gate. The formation of a narrow gate cut between closely-spaced fins can decrease the extent of etch damage to interlayer dielectric layers located adjacent to the narrow gate cut by delaying the deposition of such dielectric layers until after formation of the narrow gate cut opening. The methods and resulting structures also decrease the propensity for short circuits between later-formed, adjacent gates.
    Type: Grant
    Filed: May 3, 2018
    Date of Patent: March 10, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Jiehui Shu, Laertis Economikos, Xusheng Wu, John Zhang, Haigou Huang, Hui Zhan, Tao Han, Haiting Wang, Jinping Liu, Hui Zang
  • Spacer chamfering gate stack scheme
    Patent number: 10586855
    Abstract: A method of forming a gate structure for a semiconductor device that includes forming first spacers on the sidewalls of replacement gate structures that are present on a fin structure, wherein an upper surface of the first spacers is offset from an upper surface of the replacement gate structure, and forming at least second spacers on the first spacers and the exposed surfaces of the replacement gate structure. The method may further include substituting the replacement gate structure with a functional gate structure having a first width portion in a first space between adjacent first spacers, and a second width portion having a second width in a second space between adjacent second spacers, wherein the second width is greater than the first width.
    Type: Grant
    Filed: April 24, 2018
    Date of Patent: March 10, 2020
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES INC.
    Inventors: Hyun-Jin Cho, Tenko Yamashita, Hui Zang
  • WRAPAROUND CONTACT SURROUNDING SOURCE/DRAIN REGIONS OF INTEGRATED CIRCUIT STRUCTURES AND METHOD OF FORMING SAME
    Publication number: 20200075738
    Abstract: This disclosure is directed to an integrated circuit (IC) structure. The IC structure may include a semiconductor substrate having a first fin and a second fin spaced from the first fin; a first source/drain region in the first fin, the first source/drain region encompassing a top surface and two opposing lateral sides of the first fin; a second source/drain region in the second fin, the second source/drain encompassing a top surface and two opposing lateral sides of the second fin; and a metal contact extending over the first source/drain region and the second source/drain region and surrounding the top surface and at least a portion of the two opposing lateral sides of each of the first and the second source/drain regions.
    Type: Application
    Filed: September 4, 2018
    Publication date: March 5, 2020
    Inventors: Hui Zang, Ruilong Xie, Shesh M. Pandey, Laertis Economikos
  • METHODS OF FORMING AIR GAPS BETWEEN SOURCE/DRAIN CONTACTS AND THE RESULTING DEVICES
    Publication number: 20200075715
    Abstract: One device disclosed herein includes, among other things, first and second active regions, a first source/drain contact positioned above the first active region, a second source/drain contact positioned above the second active region, and a dielectric material disposed between the first and second source/drain contacts, wherein the dielectric material defines an air gap cavity positioned between the first and second source/drain contacts.
    Type: Application
    Filed: September 4, 2018
    Publication date: March 5, 2020
    Inventors: Ruilong Xie, Vimal Kamineni, Shesh Mani Pandey, Hui Zang
  • Methods of making a self-aligned gate contact structure and source/drain metallization structures on integrated circuit products
    Patent number: 10580701
    Abstract: A method of forming a gate structure in a gate cavity laterally defined by a sidewall spacer and recessing the sidewall spacer so as to form a recessed sidewall spacer with a recessed upper surface is disclosed. In this example, the method also includes performing at least one etching process to form a tapered upper surface on the exposed portion of the gate structure above the recessed upper surface of the spacer and forming a gate cap above the tapered upper surface of the gate structure and above the recessed upper surface of the recessed sidewall spacer.
    Type: Grant
    Filed: October 23, 2018
    Date of Patent: March 3, 2020
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Hui Zang, Scott Beasor, Haiting Wang
  • Middle of line structures
    Patent number: 10580875
    Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to middle of line structures and methods of manufacture. The structure includes: a plurality of gate structures comprising source and/or drain metallization features; spacers on sidewalls of the gate structures and composed of a first material and a second material; and contacts in electrical contact with the source and/or drain metallization features, and separated from the gate structures by the spacers.
    Type: Grant
    Filed: January 17, 2018
    Date of Patent: March 3, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Hui Zang, Guowei Xu, Keith Tabakman, Viraj Sardesai
  • Integrated single diffusion break
    Patent number: 10580685
    Abstract: A methodology for forming a fin field effect transistor (FinFET) includes the co-integration of various isolation structures, including gate cut and shallow diffusion break isolation structures that are formed with common masking and etching steps. Following an additional patterning step to provide segmentation for source/drain conductive contacts, a single deposition step is used to form an isolation dielectric layer within each of gate cut openings, shallow diffusion break openings and cavities over shallow trench isolation between device active areas.
    Type: Grant
    Filed: July 27, 2018
    Date of Patent: March 3, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Hui Zang, Haiting Wang, Hong Yu, Laertis Economikos
  • TRANSISTOR COMPRISING AN AIR GAP POSITIONED ADJACENT A GATE ELECTRODE
    Publication number: 20200066899
    Abstract: A transistor device disclosed herein includes, among other things, a gate electrode positioned above a semiconductor material region, a sidewall spacer positioned adjacent the gate electrode, a gate insulation layer having a first portion positioned between the gate electrode and the semiconductor material region and a second portion positioned between a lower portion of the sidewall spacer and the gate electrode along a portion of a sidewall of the gate electrode, an air gap cavity located between the sidewall spacer and the gate electrode and above the second portion of the gate insulation layer, and a gate cap layer positioned above the gate electrode, wherein the gate cap layer seals an upper end of the air gap cavity so as to define an air gap positioned adjacent the gate electrode.
    Type: Application
    Filed: October 25, 2019
    Publication date: February 27, 2020
    Inventors: Laertis Economikos, Shesh Mani Pandey, Hui Zang, Haiting Wang, Jinping Liu
  • FINFETS HAVING GATES PARALLEL TO FINS
    Publication number: 20200066883
    Abstract: Methods form devices by patterning a lower layer to form a fin, and forming a sacrificial gate along sidewalls of the fin. Such methods form a mask with cut openings on the sacrificial gate and remove sections of the fin and the sacrificial gate exposed through the cut openings to divide the fin into fin portions and create cut areas between the fin portions. Additionally, these methods remove the mask, epitaxially grow source/drains in the cut areas, replace the sacrificial gate with a gate conductor, and form a gate contact on the gate conductor over a center of the fin portions.
    Type: Application
    Filed: August 22, 2018
    Publication date: February 27, 2020
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Yanping Shen, Hui Zang, Bingwu Liu, Manoj Joshi, Jae Gon Lee, Hsien-Ching Lo, Zhaoying Hu
  • METHODS, APPARATUS, AND MANUFACTURING SYSTEM FOR SELF-ALIGNED PATTERNING OF CONTACTS IN A SEMICONDUCTOR DEVICE
    Publication number: 20200066588
    Abstract: A method, apparatus, and manufacturing system are disclosed for a fin field effect transistor having a reduced risk of short circuits between a gate and a source/drain contact. In one embodiment, we disclose a semiconductor device including a fin structure comprising a fin body, source/drain regions, and a metal formation disposed above the source/drain regions, wherein the metal formation has a first height; and a gate structure between the source/drain regions, wherein each gate structure comprises spacers in contact with the metal formation, wherein the spacers have a second height less than the first height, a metal plug between the spacers and below the second height, and a T-shaped cap above the metal plug and having the first height.
    Type: Application
    Filed: August 24, 2018
    Publication date: February 27, 2020
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Hui Zang, Guowei Xu, Haiting Wang
  • REPLACEMENT METAL GATE WITH REDUCED SHORTING AND UNIFORM CHAMFERING
    Publication number: 20200066879
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to replacement metal gate structures with reduced shorting and uniform chamfering, and methods of manufacture. The structure includes: a long channel device composed of a conductive gate material with a capping layer over the conductive gate material and extending to sides of the conductive gate material; and a short channel device composed of the conductive gate material and the capping layer over the conductive gate material.
    Type: Application
    Filed: August 22, 2018
    Publication date: February 27, 2020
    Inventors: Hui ZANG, Guowei XU
  • DEVICE WITH HIGHLY ACTIVE ACCEPTOR DOPING AND METHOD OF PRODUCTION THEREOF
    Publication number: 20200066593
    Abstract: A device including a triple-layer EPI stack including SiGe, Ge, and Si, respectively, with Ga confined therein, and method of production thereof. Embodiments include an EPI stack including a SiGe layer, a Ge layer, and a Si layer over a plurality of fins, the EPI stack positioned between and over a portion of sidewall spacers, wherein the Si layer is a top layer capping the Ge layer, and wherein the Ge layer is a middle layer capping the SiGe layer underneath; and a Ga layer in a portion of the Ge layer between the SiGe layer and the Si layer.
    Type: Application
    Filed: August 22, 2018
    Publication date: February 27, 2020
    Inventors: Tek Po Rinus LEE, Annie LEVESQUE, Qun GAO, Hui ZANG, Rishikesh KRISHNAN, Bharat KRISHNAN, Curtis DURFEE
  • Oxide spacer in a contact over active gate finFET and method of production thereof
    Patent number: 10573753
    Abstract: A device including oxide spacer in a contact over active gates (COAG) and method of production thereof. Embodiments include first gate structures over a fin of a substrate and second gate structures, each over an outer portion of the fin and a shallow trench isolation (STI) layer adjacent to the fin; a first raised source/drain (RSD) in a portion of the fin between the first gate structures and a second RSD in the portion of the fin between the first and second gate structures; a metal liner over the first and second RSD and on sidewall portions of the first and second gate structures; a metal layer over the metal liner; and an interlayer dielectric (ILD) over the metal liner and portions of the first and second gate structures.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: February 25, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Hui Zang, Laertis Economikos, Jiehui Shu, Ruilong Xie
  • Gate structures of FinFET semiconductor devices
    Patent number: 10566202
    Abstract: A method of fabricating a semiconductor device is provided, including providing sacrificial gate structures over a plurality of fins. The sacrificial gate structures include a sacrificial first gate structure and a sacrificial second gate structure. A first gate cut process is performed to form a first gate cut opening in the sacrificial first gate structure, and a second gate cut opening in the sacrificial second gate structure. A first dielectric layer is deposited in the first gate cut opening and the second gate cut opening. The first dielectric layer completely fills the first gate cut opening and partially fills the second gate cut opening. The first dielectric layer is removed from the second gate cut opening, and a second gate cut process is performed. A second dielectric layer is deposited in the second gate cut opening to form a gate cut structure.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: February 18, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Jiehui Shu, Hui Zang, Hong Yu