Patents by Inventor Hui Zang

Hui Zang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Gate cut method after source/drain metallization
    Patent number: 10566201
    Abstract: A method that includes forming a conductive source/drain structure that is conductively coupled to source/drain regions of first and second transistor devices, selectively forming a conductive source/drain metallization cap structure on and in contact with an upper surface of the conductive source/drain structure, forming a patterned etch mask that exposes a portion of the gate cap and a portion of the conductive source/drain metallization cap structure, and performing at least one etching process to remove the exposed portion of the gate cap and thereafter an exposed portion of the final gate structure so as to form a gate cut opening, wherein the conductive source/drain metallization cap structure protects the underlying conductive source/drain structure during the at least one etching process.
    Type: Grant
    Filed: October 30, 2018
    Date of Patent: February 18, 2020
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Chanro Park, Ruilong Xie, Hui Zang, Laertis Economikos, Andre LaBonte
  • TAPERED FIN-TYPE FIELD-EFFECT TRANSISTORS
    Publication number: 20200051868
    Abstract: Device structures and fabrication methods for a field-effect transistor. A semiconductor fin includes a first section and a second section in a lengthwise arrangement, a first gate structure overlapping the first section of the semiconductor fin, and a second gate structure overlapping the second section of the semiconductor fin. A pillar is arranged in the first section of the semiconductor fin. The pillar extends through a height of the semiconductor fin and across a width of the semiconductor fin.
    Type: Application
    Filed: August 13, 2018
    Publication date: February 13, 2020
    Inventors: Hui Zang, Ruilong Xie, Garo Jacques Derderian
  • METHODS, APPARATUS, AND SYSTEM TO CONTROL GATE HEIGHT AND CAP THICKNESS ACROSS MULTIPLE GATES
    Publication number: 20200052106
    Abstract: At least one method, apparatus, and system providing semiconductor devices comprising a first gate having a first width and comprising a first work function metal (WFM); a first liner disposed over the first WFM; a first gate metal having a first height; and a first pinch-off spacer over the first WFM, the first liner, and the first gate metal to above the first height; and a second gate having a second width greater than the first width, and comprising a second WFM; a second liner disposed over the second WFM; a second gate metal having substantially the first height; and a first conformal spacer over the second WFM and the second liner.
    Type: Application
    Filed: August 10, 2018
    Publication date: February 13, 2020
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Laertis Economikos, Hui Zang, Ruilong Xie, Neal Makela, Pei Liu, Jiehui Shu, Chih-chiang Chang
  • Methods of forming gate contact over active region for vertical FinFET, and structures formed thereby
    Patent number: 10559686
    Abstract: Methods of making a vertical FinFET device having an electrical path over a gate contact landing, and the resulting device including a substrate having a bottom S/D layer thereover and fins extending vertically therefrom; a bottom spacer layer over the bottom S/D layer; a HKMG layer over the bottom spacer layer; a top spacer layer over the HKMG layer; a top S/D layer on top of each fin; top S/D contacts formed over the top S/D layer; an upper ILD layer present in spaces around the top S/D contacts; an isolation dielectric within a portion of a recess of top S/D contacts located above adjacent fins; a gate contact landing within a remaining portion of the recess; a gate contact extending vertically from a bottom surface of the gate contact landing and contacting a portion of the HKMG layer; and an electrical path over at least the gate contact landing.
    Type: Grant
    Filed: June 26, 2018
    Date of Patent: February 11, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Ruilong Xie, Hui Zang, Steven R. Soss
  • Wrap-all-around contact for nanosheet-FET and method of forming same
    Patent number: 10559656
    Abstract: Described herein are nanosheet-FET structures having a wrap-all-around contact where the contact wraps entirely around the S/D epitaxy structure, thereby increasing contact area and ultimately allowing for improved S/D contact resistance. Other aspects described include nanosheet-FET structures having an air gap as a bottom isolation area to reduce parasitic S/D leakage to the substrate.
    Type: Grant
    Filed: May 2, 2018
    Date of Patent: February 11, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Emilie M. S. Bourjot, Julien Frougier, Yi Qi, Ruilong Xie, Hui Zang, Hsien-Ching Lo, Zhenyu Hu
  • IC STRUCTURE WITH METAL CAP ON COBALT LAYER AND METHODS OF FORMING SAME
    Publication number: 20200044034
    Abstract: The disclosure relates to methods of forming integrated circuit (IC) structures with a metal cap on a cobalt layer for source and drain regions of a transistor. An integrated circuit (IC) structure according to the disclosure may include: a semiconductor fin on a substrate; a gate structure over the substrate, the gate structure having a first portion extending transversely across the semiconductor fin; an insulator cap positioned on the gate structure above the semiconductor fin; a cobalt (Co) layer on the semiconductor fin adjacent to the gate structure, wherein an upper surface of the Co layer is below an upper surface of the gate structure; and a metal cap on the Co layer.
    Type: Application
    Filed: August 3, 2018
    Publication date: February 6, 2020
    Inventors: Laertis Economikos, Kevin J. Ryan, Ruilong Xie, Hui Zang
  • FIELD-EFFECT TRANSISTORS WITH IMPROVED DIELECTRIC GAP FILL
    Publication number: 20200043779
    Abstract: Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. A first dielectric layer is deposited over a first gate structure in a first device area and a second gate structure in a second device area, and then planarized. A second dielectric layer is deposited over the planarized first dielectric layer, and then removed from the first device area. After removing the second dielectric layer from the first device area, the first dielectric layer in the first device area is recessed to expose the first gate structure. A silicide is formed on the exposed first gate structure.
    Type: Application
    Filed: August 1, 2018
    Publication date: February 6, 2020
    Inventors: Wei Hong, Liu Jiang, Yongjun Shi, Yi Qi, Hsien-Ching Lo, Hui Zang
  • Field effect transistors with self-aligned metal plugs and methods
    Patent number: 10553486
    Abstract: Disclosed is a method of forming an integrated circuit (IC) and the resulting structure. The method includes forming a transistor with a sacrificial gate on a channel region, a gate sidewall spacer on the sacrificial gate, and sacrificial plugs on the source/drain regions. The sacrificial gate is replaced with a gate, a gate cap on the gate, and a sacrificial cap on the gate cap and the gate sidewall spacer (which was recessed). Thus, top surfaces of the gate cap and gate sidewall spacer are at a lower level than the top surfaces of the sacrificial plugs and, when the sacrificial plugs are replaced with metal plugs, the gate cap is protected. In the resulting structure, the gate cap has a desired thickness and the top surface of the gate cap is at a lower level than the top surfaces of the metal plugs to reduce the risk of shorts.
    Type: Grant
    Filed: July 27, 2018
    Date of Patent: February 4, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Hui Zang, Ruilong Xie, Laertis Economikos
  • Methods, apparatus and system for a self-aligned gate cut on a semiconductor device
    Patent number: 10553698
    Abstract: At least one method, apparatus and system disclosed herein involves adjusting for a misalignment of a gate cut region with respect to semiconductor processing. A plurality of fins are formed on a semiconductor substrate. A gate region is formed over a portion of the fins. The gate region comprises a first dummy gate and a second dummy gate. A gate cut region is formed over the first dummy gate. A conformal fill material is deposited into the gate cut region. At least one subsequent processing step is performed.
    Type: Grant
    Filed: April 12, 2018
    Date of Patent: February 4, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Hui Zang, Laertis Economikos, Ruilong Xie
  • FinFETs having gates parallel to fins
    Patent number: 10553707
    Abstract: Methods form devices by patterning a lower layer to form a fin, and forming a sacrificial gate along sidewalls of the fin. Such methods form a mask with cut openings on the sacrificial gate and remove sections of the fin and the sacrificial gate exposed through the cut openings to divide the fin into fin portions and create cut areas between the fin portions. Additionally, these methods remove the mask, epitaxially grow source/drains in the cut areas, replace the sacrificial gate with a gate conductor, and form a gate contact on the gate conductor over a center of the fin portions.
    Type: Grant
    Filed: August 22, 2018
    Date of Patent: February 4, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Yanping Shen, Hui Zang, Bingwu Liu, Manoj Joshi, Jae Gon Lee, Hsien-Ching Lo, Zhaoying Hu
  • INTEGRATED SINGLE DIFFUSION BREAK
    Publication number: 20200035543
    Abstract: A methodology for forming a fin field effect transistor (FinFET) includes the co-integration of various isolation structures, including gate cut and shallow diffusion break isolation structures that are formed with common masking and etching steps. Following an additional patterning step to provide segmentation for source/drain conductive contacts, a single deposition step is used to form an isolation dielectric layer within each of gate cut openings, shallow diffusion break openings and cavities over shallow trench isolation between device active areas.
    Type: Application
    Filed: July 27, 2018
    Publication date: January 30, 2020
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Hui ZANG, Haiting WANG, Hong YU, Laertis ECONOMIKOS
  • FIELD EFFECT TRANSISTORS WITH SELF-ALIGNED METAL PLUGS AND METHODS
    Publication number: 20200035555
    Abstract: Disclosed is a method of forming an integrated circuit (IC) and the resulting structure. The method includes forming a transistor with a sacrificial gate on a channel region, a gate sidewall spacer on the sacrificial gate, and sacrificial plugs on the source/drain regions. The sacrificial gate is replaced with a gate, a gate cap on the gate, and a sacrificial cap on the gate cap and the gate sidewall spacer (which was recessed). Thus, top surfaces of the gate cap and gate sidewall spacer are at a lower level than the top surfaces of the sacrificial plugs and, when the sacrificial plugs are replaced with metal plugs, the gate cap is protected. In the resulting structure, the gate cap has a desired thickness and the top surface of the gate cap is at a lower level than the top surfaces of the metal plugs to reduce the risk of shorts.
    Type: Application
    Filed: July 27, 2018
    Publication date: January 30, 2020
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Hui Zang, Ruilong Xie, Laertis Economikos
  • Metal resistors integrated into poly-open-chemical-mechanical-polishing (POC) module and method of production thereof
    Patent number: 10546853
    Abstract: A device including RM below the top surface of an HKMG structure, and method of production thereof. Embodiments include first and second HKMG structures over a portion of the substrate and on opposite sides of the STI region, the first and second HKMG structures having a top surface; and a RM over the STI region and between the first and second HKMG structures, wherein the RM is below the top surface of the first and second HKMG structures.
    Type: Grant
    Filed: June 22, 2018
    Date of Patent: January 28, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Laertis Economikos, Hui Zang, Ruilong Xie
  • Field-effect transistors with improved dielectric gap fill
    Patent number: 10546775
    Abstract: Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. A first dielectric layer is deposited over a first gate structure in a first device area and a second gate structure in a second device area, and then planarized. A second dielectric layer is deposited over the planarized first dielectric layer, and then removed from the first device area. After removing the second dielectric layer from the first device area, the first dielectric layer in the first device area is recessed to expose the first gate structure. A silicide is formed on the exposed first gate structure.
    Type: Grant
    Filed: August 1, 2018
    Date of Patent: January 28, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Wei Hong, Liu Jiang, Yongjun Shi, Yi Qi, Hsien-Ching Lo, Hui Zang
  • METHODS OF FORMING SPACERS ADJACENT GATE STRUCTURES OF A TRANSISTOR DEVICE
    Publication number: 20200027979
    Abstract: One illustrative method disclosed herein includes forming a low-k sidewall spacer adjacent opposing sidewalls of a gate structure, forming contact etch stop layers (CESLs) adjacent the low-k sidewall spacer in the source/drain regions of the transistor, and forming a first insulating material above the CESLs. In this example, the method also includes recessing the first insulating material so as to expose substantially vertically oriented portions of the CESLs, removing a portion of a lateral width of the substantially vertically oriented portions of the CESLs so as to form trimmed CESLs, and forming a high-k spacer on opposite sides of the gate structure, wherein at least a portion of the high-k spacer is positioned laterally adjacent the trimmed substantially vertically oriented portions of the trimmed CESLs.
    Type: Application
    Filed: July 18, 2018
    Publication date: January 23, 2020
    Inventors: Hui Zang, Chung Foong Tan, Guowei Xu, Haiting Wang, Yue Zhong, Ruilong Xie, Tek Po Rinus Lee, Scott Beasor
  • COMPOSITE SPACERS FOR TAILORING THE SHAPE OF THE SOURCE AND DRAIN REGIONS OF A FIELD-EFFECT TRANSISTOR
    Publication number: 20200020770
    Abstract: Structures for field-effect transistors and methods for forming field-effect transistors. A sidewall spacer is arranged adjacent to a sidewall of a gate structure. The sidewall spacer includes a first section and a second section arranged over the first section. The first section of the sidewall spacer is composed of a first dielectric material, and the second section of the sidewall spacer is composed of a second dielectric material different from the first dielectric material. A source/drain region includes a first section arranged adjacent to the first section of the sidewall spacer and a second section arranged adjacent to the second section of the sidewall spacer. The second section of the source/drain region is spaced by a gap from the second section of the sidewall spacer.
    Type: Application
    Filed: July 12, 2018
    Publication date: January 16, 2020
    Inventors: Yi Qi, Hsien-Ching Lo, Xusheng Wu, Hui Zang, Zhenyu Hu, George R. Mulfinger
  • VERTICALLY ORIENTED METAL SILICIDE CONTAINING E-FUSE DEVICE
    Publication number: 20200020631
    Abstract: One illustrative integrated circuit product disclosed herein includes a vertically oriented semiconductor (VOS) structure positioned above a semiconductor substrate, a conductive silicide vertically oriented e-fuse positioned along at least a portion of a vertical height of the VOS structure wherein the conductive silicide vertically oriented e-fuse comprises a metal silicide material that extends through at least a portion of an entire lateral width of the VOS structure, and a conductive metal silicide region in the semiconductor substrate that is conductively coupled to the conductive silicide vertically oriented e-fuse.
    Type: Application
    Filed: September 23, 2019
    Publication date: January 16, 2020
    Inventors: Chun Yu Wong, Kwan-Yong Lim, Seong Yeol Mun, Jagar Singh, Hui Zang
  • USING SOURCE/DRAIN CONTACT CAP DURING GATE CUT
    Publication number: 20200020687
    Abstract: Parallel fins are formed (in a first orientation), and source/drain structures are formed in or on the fins, where channel regions of the fins are between the source/drain structures. Parallel gate structures are formed to intersect the fins (in a second orientation perpendicular to the first orientation), source/drain contacts are formed on source/drain structures that are on opposite sides of the gate structures, and caps are formed on the source/drain contacts. After forming the caps, a gate cut structure is formed interrupting the portion of the gate structure that extends between adjacent fins. The upper portion of the gate cut structure includes extensions, where a first extension extends into one of the caps on a first side of the gate cut structure, and a second extension extends into the inter-gate insulator on a second side of the gate cut structure.
    Type: Application
    Filed: July 11, 2018
    Publication date: January 16, 2020
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Haiting Wang, Shesh Mani Pandey, Jiehui Shu, Laertis Economikos, Hui Zang, Ruilong Xie, Guowei Xu, Zhaoying Hu
  • Method for forming replacement air gap
    Patent number: 10535771
    Abstract: A method of forming transistor devices with an air gap in the replacement gate structure is disclosed including forming a placeholder gate structure above a semiconductor material region, forming a sidewall spacer adjacent the placeholder gate structure, removing the placeholder gate structure to define a gate cavity bounded by the sidewall spacer, forming a gate insulation layer in the gate cavity, the gate insulation layer including a first portion having a first thickness and a second portion having a second thickness greater than the first thickness, forming a gate electrode in the gate cavity above the gate insulation layer, removing at least a portion of the second portion of the gate insulation layer to define an air gap cavity adjacent the gate electrode, and forming a first gate cap layer above the gate electrode, wherein the first gate cap layer seals an upper end of the air gap cavity.
    Type: Grant
    Filed: June 25, 2018
    Date of Patent: January 14, 2020
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Laertis Economikos, Shesh Mani Pandey, Hui Zang, Haiting Wang, Jinping Liu
  • Method of manufacturing a vertical SRAM with cross-coupled contacts penetrating through common gate structures
    Patent number: 10529724
    Abstract: A vertical SRAM cell includes a first (1st) inverter having a 1st common gate structure operatively connecting channels of a 1st pull-up (PU) and a 1st pull-down (PD) transistor. A 1st metal contact electrically connects bottom source/drain (S/D) regions of the 1st PU and 1st PD transistors. A second (2nd) inverter has a 2nd common gate structure operatively connecting channels of a 2nd PU and a 2nd PD transistor. A 2nd metal contact electrically connects bottom S/D regions of the 2nd PU and 2nd PD transistors. A 1st cross-coupled contact electrically connects the 2nd common gate structure to the 1st metal contact. The 2nd common gate structure entirely surrounds a perimeter of the 1st cross-coupled contact. A 2nd cross-coupled contact electrically connects the 1st common gate structure to the 2nd metal contact. The 1st common gate structure entirely surrounds a perimeter of the 2nd cross-coupled contact.
    Type: Grant
    Filed: August 7, 2018
    Date of Patent: January 7, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Hui Zang, Manfred Eller, Kwan-Yong Lim