Abstract: There are provided a semiconductor device, a method of manufacturing the same, and an electronic device including the device. According to an embodiment, the semiconductor device may include a substrate, and a first device and a second device formed on the substrate. Each of the first device and the second device includes a first source/drain layer, a channel layer and a second source/drain layer stacked on the substrate in sequence, and also a gate stack surrounding a periphery of the channel layer. The channel layer of the first device and the channel layer of the second device are substantially co-planar.

Abstract: A semiconductor device and a method of manufacturing the same, and an electronic apparatus including the semiconductor device are provided. The semiconductor device includes: an active region, on a substrate, extending substantially in a vertical direction; a gate stack formed around at least a part of a periphery of the active region, the active region including a channel region opposite to the gate stack, and a first source/drain region and a second source/drain region, and the gate stack including a gate dielectric layer, a work function tuning layer and a gate electrode material layer, and the work function tuning layer being between the gate electrode material layer and the channel region; and a first low-k dielectric layer extending from a first end of the work function tuning layer to surround a first corner of an end portion, on a side facing the channel region, of the gate electrode material layer.

Abstract: A method of manufacturing a semiconductor memory device is provided. The method include: providing a stack of a sacrificial layer, a first source/drain layer, a channel layer, and a second source/drain layer on a substrate; defining a plurality of pillar-shaped active regions arranged in rows and columns in the first source/drain layer, the channel layer, and the second source/drain layer; removing the sacrificial layer and forming a plurality of bit lines extending below the respective columns of active regions in a space left by the removal of the sacrificial layer; forming gate stacks around peripheries of the channel layer in the respective active regions; and forming a plurality of word lines between the respective rows of active regions, wherein each of the word lines is electrically connected to the gate stacks of the respective memory cells in a corresponding one of the rows.

Abstract: A semiconductor device and a method for manufacturing the same. A substrate is provided. A first source-drain layer, a channel layer, and a second source-drain layer are sequentially stacked on the substrate. Both a gate dielectric layer and a gate structure surround the channel layer laterally. The gate structure includes a first portion extending laterally and a second portion extending upward from a periphery of the first portion. A second portion is located at a periphery of the second source-drain layer. A spacer layer is formed at an outer sidewall of the gate structure. The gate structure is etched to reduce a thickness of the gate structure. A sacrificial structure covering the gate structure is formed, and a capping layer covering the second source-drain layer, the sacrificial structure, and the spacer layer is formed. Thereby, the sacrificial structure is located at the periphery of the second source-drain layer and enclosed by the spacer layer.

Abstract: A semiconductor device including a substrate, a first source/drain layer, a channel layer and a second source/drain layer stacked on the substrate in sequence, and a gate stack surrounding a periphery of the channel layer. The channel layer includes a semiconductor material causing an increased ON current and/or a reduced OFF current as compared to Si.

Abstract: Provided are a semiconductor device with decreased source and drain resistance and a manufacturing method. The semiconductor device includes a substrate and multiple three-dimensional semiconductor device arrays. The three-dimensional semiconductor device arrays are on the substrate, and the three-dimensional semiconductor device arrays are separated by isolation grooves. Each three-dimensional semiconductor device array includes a plurality of device layers in a vertical direction, each device layer includes a stack of a source/drain layer, a channel layer and a source/drain layer, and an end face of the source/drain layer adjacent to the isolation groove is metallized. The three-dimensional semiconductor device array further includes a plurality of gate stacks arranged in an array, the gate stack penetrates each device layer in the vertical direction and includes a gate material and a gate dielectric layer, and a device unit is defined at an intersection of the gate stack and the device layer.

Abstract: A nanowire/nanosheet device with a crystal spacer, a method of manufacturing the nanowire/nanosheet device with the crystal spacer, and an electronic apparatus including the nanowire/nanosheet device are provided. The nanowire/nanosheet device includes: a substrate; a nanowire/nanosheet spaced apart from a surface of the substrate and extending in a first direction; source/drain layers located at opposite ends of the nanowire/nanosheet in the first direction and adjoining the nanowire/nanosheet; a gate stack extending in a second direction intersecting with the first direction to surround the nanowire/nanosheet; and a spacer provided on a sidewall of the gate stack, wherein the spacer has a crystal structure substantially identical to a crystal structure of the nanowire/nanosheet in at least a part of a region of the spacer adjacent to the nanowire/nanosheet.

Abstract: An interconnection structure for semiconductor devices formed on a substrate may be arranged under the semiconductor devices. The interconnection structure includes at least one via layer and at least one interconnection layer alternately arranged in a direction from the semiconductor device to the substrate, wherein each via layer includes via holes respectively arranged under at least a part of the semiconductor devices, and each interconnection layer includes conductive nodes respectively arranged under at least a part of the semiconductor devices, and in a same interconnection layer, a conductive channel is provided between at least one conductive node and at least another node; and the via holes in each via layer and the conductive nodes in each interconnection layer corresponding to the via holes at least partially overlap with each other in the direction from the semiconductor device to the substrate.

Abstract: A strained vertical channel semiconductor device, a method of manufacturing the same, and an electronic apparatus including the same are provided. The method includes: providing a vertical channel layer on a substrate, wherein the vertical channel layer is held by a first supporting layer on a first side in a lateral direction, and is held by a second supporting layer on a second side opposite to the first side; replacing the first supporting layer with a first gate stack while the vertical channel layer is held by the second supporting layer; and replacing the second supporting layer with a second gate stack while the vertical channel layer is held by the first gate stack.

Abstract: Provided are a self-aligned nanometer through-silicon-via structure and a method of preparing the same. According to the preset range and positions of the first and second trenches, the second preset pattern is formed, and then the first initial blind hole is formed by etching based on the second preset pattern, so that the position of the nanometer through-silicon-via is determined. The depth of the buried power rail may be determined by etching the silicon substrate with the first preset depth, and the depth of the self-aligned nanometer through-silicon-via may be determined by etching the silicon substrate with the second preset depth or thinning the fourth structure from a side of the silicon substrate.

Abstract: A semiconductor device and a method for manufacturing the same. A first electrode layer, a semiconductor layer, and a second electrode layer are formed on a substrate. The semiconductor layer is etched form a sidewall to form a cavity. A channel layer is formed at the cavity and sidewalls of the first electrode layer and the second electrode layer. The channel layer includes a first channel part located in the cavity and a second channel part located outside the cavity. The first channel part is filled with a dummy gate layer. The dummy gate layer is etched from a sidewall. The second channel part and the first channel part, which is in contact with upper and lower surfaces of the dummy gate layer are removed to form a recess. The recess is filled with a dielectric material to form an isolation sidewall.

Abstract: Provided are a nanowire/nanosheet device with a support portion, a method of manufacturing the same, and an electronic apparatus including the nanowire/nanosheet device.

Abstract: Provided are a NOR-type memory device, a manufacturing method, and an electronic device. The device includes: a plurality of gate stacks extending vertically on a substrate, wherein the gate stack includes a first gate conductor layer and a first filling layer; at least one device layer surrounding a periphery of the gate stack and extending along a sidewall of the gate stack; and a single-crystal vertical channel on a side of the device layer close to the gate stack and in contact with the first filling layer. At least one side surface of the gate stack in the vertical direction is a (100) or (110) crystal plane; and/or the body region includes a second filling layer or the body region includes a second gate conductor layer and a third filling layer, wherein at least one of first and third filling layers is a storage functional layer.

Abstract: A semiconductor device having a double-gate structure and a method of manufacturing the same, and an electronic apparatus including the semiconductor device are provided. The semiconductor device may include: a vertical channel portion on a substrate; source/drain portions respectively located at upper and lower ends of the channel portion relative to the substrate; and a first gate stack and a second gate stack on opposite sides of the channel portion in a first direction lateral to the substrate. A distance between an upper edge and/or a lower edge of an end of the first gate stack facing the channel portion in a vertical direction and a corresponding source/drain portion may be less than a distance between a corresponding upper edge and/or a corresponding lower edge of an end of the second gate stack facing the channel portion in the vertical direction and a corresponding source/drain portion.

Abstract: A method of manufacturing a semiconductor device is provided. The method includes: forming a channel defining layer and a source/drain layer sequentially on a substrate of a crystalline material; patterning the channel defining layer and the source/drain layer as a ridge protruding relative to the substrate; forming a channel layer on a sidewall of the ridge by deposition; and performing a crystallization process to recrystallize the channel layer.

Abstract: A memory device, including: device layers vertically stacked on a substrate, each device layer including an array of active regions of selection transistors, the array including rows in a first direction and columns in a second direction, the active region including a lower source/drain region, a channel portion, and an upper source/drain region; bit lines arranged in the second direction and extending in the first direction along rows; word line layers vertically stacked and corresponding to the device layers, and each including word lines arranged in the first direction and extending in the second direction to at least partially surround a channel portion in a column of a device layer; sub bit lines extending vertically from each bit line and each electrically connected to a lower source/drain region in a row in each device layer above the bit line; and a memory element electrically connected to the upper source/drain region.

Abstract: An interconnection structure and a method of manufacturing the same, and an electronic device including the interconnection structure are provided.

Abstract: A nanowire/nanosheet device and a method of manufacturing the same, and an electronic apparatus including the nanowire/nanosheet device. The nanowire/nanosheet device includes: a substrate; a nanowire/nanosheet spaced apart from a surface of the substrate and extending in a first direction; a source/drain layer at opposite ends of the nanowire/nanosheet in the first direction and adjoining the nanowire/nanosheet; a gate stack extending in a second direction intersecting with the first direction to surround the nanowire/nanosheet; and a first spacer on a sidewall of the gate stack, wherein the first spacer includes a continuously extending material layer which has a first part along a surface of the nanowire/nanosheet, a second part along a sidewall of the source/drain layer facing the gate stack, and a third part along a sidewall of the gate stack facing the source/drain layer, and the second part and the third part have a seam or an interface therebetween.

Abstract: The vertical MOSFET device includes: an active region including a first source/drain layer, a channel layer and a second source/drain layer vertically stacked on a substrate in sequence, wherein an outer periphery of the channel layer is recessed with respect to outer peripheries of the first source/drain layer and the second source/drain layer; a spacing layer including an upper spacing layer and a lower spacing layer, wherein the upper spacing layer and the lower spacing layer are both in contact with a side surface of the channel layer and are not in communication with each other; and a gate stack formed at least on a lateral outer periphery of the channel layer and embedded in a groove space between the upper spacing layer and the lower spacing layer.

Abstract: Disclosed are a semiconductor device, a method for manufacturing the same, an integrated circuit, and an electronic apparatus. The semiconductor device includes: a substrate; an active region on the substrate, the active region includes a first source and drain layer, a channel layer, and a second source and drain layer sequentially stacked on the substrate; a gate stack formed around an outer periphery of the channel layer; and an intermediate dielectric layer and a second conductive layer around an outer periphery of the gate stack and an outer periphery of the active region. The device and method provided by the present disclosure are used to solve the technical problem that the performances of the vertical device in the related art need to be improved. A semiconductor device with better performances is provided.