Patents by Inventor Huilong Zhu

Huilong Zhu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200203343
    Abstract: There are provided an Integrated Circuit (IC) unit, a method of manufacturing the same, and an electronic device including the IC unit. According to an embodiment, the IC unit includes a first source/drain layer, a channel layer and a second source/drain layer for a first device and a first source/drain layer, a channel layer and a second source/drain layer for a second device stacked in sequence on a substrate. In the first device, the channel layer includes a first portion and a second portion separated from each other. The first source/rain layer and the second source/drain layer each extend integrally to overlap both the first portion and the second portion of the channel layer. The IC unit further includes a first gate stack surrounding a periphery of the first portion and also a periphery of the second portion of the channel layer of the first device, and a second gate stack surrounding a periphery of the channel layer of the second device.
    Type: Application
    Filed: March 5, 2020
    Publication date: June 25, 2020
    Inventors: Huilong Zhu, Zhengyong Zhu
  • Patent number: 10643905
    Abstract: There are provided an Integrated Circuit (IC) unit, a method of manufacturing the same, and an electronic device including the IC unit. According to an embodiment, the IC unit includes a first source/drain layer, a channel layer and a second source/drain layer for a first device and a first source/drain layer, a channel layer and a second source/drain layer for a second device stacked in sequence on a substrate. In the first device, the channel layer includes a first portion and a second portion separated from each other. The first source/rain layer and the second source/drain layer each extend integrally to overlap both the first portion and the second portion of the channel layer. The IC unit further includes a first gate stack surrounding a periphery of the first portion and also a periphery of the second portion of the channel layer of the first device, and a second gate stack surrounding a periphery of the channel layer of the second device.
    Type: Grant
    Filed: May 23, 2019
    Date of Patent: May 5, 2020
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Huilong Zhu, Zhengyong Zhu
  • Patent number: 10644103
    Abstract: Provided are a semiconductor device having a charged punch-through stopper (PTS) layer to reduce punch-through and a method of manufacturing the same. In an embodiment, the semiconductor device may include a fin structure formed on a substrate; an isolation layer formed on the substrate, wherein a portion of the fin structure above the isolation layer acts as a fin of the semiconductor device; a charged PTS layer formed on side walls of a portion of the fin structure beneath the fin; and a gate stack formed on the isolation layer and intersecting the fin. The semiconductor device may be an n-type device or a p-type device. For the n-type device, the PTS layer may have net negative charges, and for the p-type device, the PTS layer may have net positive charges.
    Type: Grant
    Filed: October 18, 2016
    Date of Patent: May 5, 2020
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Huilong Zhu, Xing Wei
  • Patent number: 10629498
    Abstract: There are provided an Integrated Circuit (IC) unit, a method of manufacturing the same, and an electronic device including the IC unit. According to an embodiment, the IC unit includes a first source/drain layer, a channel layer and a second source/drain layer for a first device and a first source/drain layer, a channel layer and a second source/drain layer for a second device stacked in sequence on a substrate. In the first device, the channel layer includes a first portion and a second portion separated from each other. The first source/rain layer and the second source/drain layer each extend integrally to overlap both the first portion and the second portion of the channel layer. The IC unit further includes a first gate stack surrounding a periphery of the first portion and also a periphery of the second portion of the channel layer of the first device, and a second gate stack surrounding a periphery of the channel layer of the second device.
    Type: Grant
    Filed: October 2, 2017
    Date of Patent: April 21, 2020
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Huilong Zhu, Zhengyong Zhu
  • Patent number: 10600696
    Abstract: There are provided an Integrated Circuit (IC) unit, a method of manufacturing the same, and an electronic device including the IC unit. According to an embodiment, the IC unit includes a first source/drain layer, a channel layer and a second source/drain layer for a first device and a first source/drain layer, a channel layer and a second source/drain layer for a second device stacked in sequence on a substrate. In the first device, the channel layer includes a first portion and a second portion separated from each other. The first source/rain layer and the second source/drain layer each extend integrally to overlap both the first portion and the second portion of the channel layer. The IC unit further includes a first gate stack surrounding a periphery of the first portion and also a periphery of the second portion of the channel layer of the first device, and a second gate stack surrounding a periphery of the channel layer of the second device.
    Type: Grant
    Filed: May 23, 2019
    Date of Patent: March 24, 2020
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Huilong Zhu, Zhengyong Zhu
  • Publication number: 20200035696
    Abstract: A memory device may include first and second pillar-shaped active regions formed on a substrate and extending upward. The first and second active regions are arranged in a first array and a second array, respectively. Each of the first active regions comprises alternatively stacked source/drain layers and channel layers, wherein the channel layers of the respective first active regions at a corresponding level are substantially coplanar with each other, and the source/drain layers of the respective first active regions at a corresponding level are substantially coplanar with each other. Each of the second active regions comprises an active semiconductor layer extending integrally. The memory device may include multiple layers of first storage gate stacks surrounding peripheries of and being substantially coplanar with the respective levels of the channel layers, and multiple layers of second storage gate stacks which surround peripheries of the respective second active regions.
    Type: Application
    Filed: July 31, 2017
    Publication date: January 30, 2020
    Inventor: Huilong ZHU
  • Publication number: 20200027995
    Abstract: There are provided a nanometer semiconductor device with a high-quality epitaxial layer and a method of manufacturing the same. According to an embodiment, the semiconductor device may include: a substrate; at least one nanowire spaced apart from the substrate; at least one semiconductor layer, each formed around a periphery of respective one of the at least one nanowire to at least partially surround the corresponding nanowire, wherein the semiconductor layer(s) formed around the respective nanowire(s) are separated from each other; an isolation layer formed on the substrate, exposing the at least one semiconductor layer; and a gate stack formed on the isolation layer and intersecting the at least one semiconductor layer, wherein the gate stack includes a gate dielectric layer at least partially surrounding a periphery of respective one of the at least one semiconductor layer and a gate conductor layer.
    Type: Application
    Filed: September 27, 2019
    Publication date: January 23, 2020
    Inventor: Huilong Zhu
  • Publication number: 20200027950
    Abstract: A semiconductor device including a substrate, a first source/drain layer, a channel layer and a second source/drain layer stacked on the substrate in sequence, and a gate stack surrounding a periphery of the channel layer. The channel layer includes a semiconductor material causing an increased ON current and/or a reduced OFF current as compared to Si.
    Type: Application
    Filed: July 31, 2017
    Publication date: January 23, 2020
    Inventors: Huilong ZHU, Guilei WANG, Henry H. RADAMSON, Yanbo ZHANG, Zhengyong ZHU
  • Publication number: 20200027879
    Abstract: A semiconductor device including a first source/drain region at a lower portion thereof, a second source/drain region at an upper portion thereof, a channel region between the first source/drain region and the second source/drain region and close to peripheral surfaces thereof, and a body region inside the channel region. The semiconductor device may further include a gate stack formed around a periphery of the channel region.
    Type: Application
    Filed: July 31, 2017
    Publication date: January 23, 2020
    Inventor: Huilong Zhu
  • Publication number: 20200027994
    Abstract: There are provided a nanometer semiconductor device with a high-quality epitaxial layer and a method of manufacturing the same. According to an embodiment, the semiconductor device may include: a substrate; at least one nanowire spaced apart from the substrate; at least one semiconductor layer, each formed around a periphery of respective one of the at least one nanowire to at least partially surround the corresponding nanowire, wherein the semiconductor layer(s) formed around the respective nanowire(s) are separated from each other; an isolation layer formed on the substrate, exposing the at least one semiconductor layer; and a gate stack formed on the isolation layer and intersecting the at least one semiconductor layer, wherein the gate stack includes a gate dielectric layer at least partially surrounding a periphery of respective one of the at least one semiconductor layer and a gate conductor layer.
    Type: Application
    Filed: September 27, 2019
    Publication date: January 23, 2020
    Inventor: Huilong Zhu
  • Publication number: 20200027897
    Abstract: A memory device, a method of manufacturing the same, and an electronic device including the same are provided. According to embodiments, the memory device includes multiple layers of memory cells stacked on a substrate. Each of the multiple layers includes a first array of first memory cells and a second array of second memory cells, which are nested with each other. The respective first memory cells and the respective second memory cells in the respective layers are substantially aligned to each other in a stacking direction of the memory cell layers. Each of the first memory cells is a vertical device based on a first source/drain layer, a channel layer, and a second source/drain layer stacked in sequence. Each of the second memory cells is a vertical device based on an active semiconductor layer extending in the stacking direction. The first and second memory cells include respective storage gate stacks, which share a common gate conductor layer.
    Type: Application
    Filed: March 31, 2017
    Publication date: January 23, 2020
    Inventor: Huilong ZHU
  • Patent number: 10497809
    Abstract: There are provided a Fin Field Effect Transistor (FinFET), a method of manufacturing the same, and an electronic device including the same. According to embodiments, the FinFET may include a fin formed on a substrate, a gate stack formed on the substrate and intersecting the fin, and a gate spacer formed on sidewalls of the gate stack. The gate spacer may include a dielectric material and a negative capacitance material.
    Type: Grant
    Filed: June 27, 2016
    Date of Patent: December 3, 2019
    Assignee: Microelectronics, Chinese Academy of Sciences
    Inventor: Huilong Zhu
  • Patent number: 10475935
    Abstract: There are provided a nanometer semiconductor device with a high-quality epitaxial layer and a method of manufacturing the same. According to an embodiment, the semiconductor device may include: a substrate; at least one nanowire spaced apart from the substrate; at least one semiconductor layer, each formed around a periphery of respective one of the at least one nanowire to at least partially surround the corresponding nanowire, wherein the semiconductor layer(s) formed around the respective nanowire(s) are separated from each other; an isolation layer formed on the substrate, exposing the at least one semiconductor layer; and a gate stack formed on the isolation layer and intersecting the at least one semiconductor layer, wherein the gate stack includes a gate dielectric layer at least partially surrounding a periphery of respective one of the at least one semiconductor layer and a gate conductor layer.
    Type: Grant
    Filed: December 7, 2016
    Date of Patent: November 12, 2019
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventor: Huilong Zhu
  • Patent number: 10468312
    Abstract: There are provided an Integrated Circuit (IC) unit, a method of manufacturing the same, and an electronic device including the IC unit. According to an embodiment, the IC unit includes a first source/drain layer, a channel layer and a second source/drain layer for a first device and a first source/drain layer, a channel layer and a second source/drain layer for a second device stacked in sequence on a substrate. In the first device, the channel layer includes a first portion and a second portion separated from each other. The first source/rain layer and the second source/drain layer each extend integrally to overlap both the first portion and the second portion of the channel layer. The IC unit further includes a first gate stack surrounding a periphery of the first portion and also a periphery of the second portion of the channel layer of the first device, and a second gate stack surrounding a periphery of the channel layer of the second device.
    Type: Grant
    Filed: October 2, 2017
    Date of Patent: November 5, 2019
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Huilong Zhu, Zhengyong Zhu
  • Publication number: 20190304976
    Abstract: A semiconductor arrangement includes: a substrate; fins formed on the substrate and extending in a first direction; gate stacks formed on the substrate and each extending in a second direction crossing the first direction to intersect at least one of the fins, and dummy gates composed of a dielectric and extending in the second direction; spacers formed on sidewalls of the gate stacks and the dummy gates; and dielectric disposed between first and second ones of the gate stacks in the second direction to electrically isolate the first and second gate stacks. The dielectric is disposed in a space surrounded by respective spacers of the first and second gate stacks which extend integrally. At least a portion of an interval between the first and second gate stacks in the second direction is less than a line interval achievable by lithography in a process of manufacturing the semiconductor arrangement.
    Type: Application
    Filed: December 21, 2016
    Publication date: October 3, 2019
    Inventors: Huilong ZHU, Yanbo ZHANG, Huicai ZHONG
  • Publication number: 20190287865
    Abstract: There are provided an Integrated Circuit (IC) unit, a method of manufacturing the same, and an electronic device including the IC unit. According to an embodiment, the IC unit includes a first source/drain layer, a channel layer and a second source/drain layer for a first device and a first source/drain layer, a channel layer and a second source/drain layer for a second device stacked in sequence on a substrate. In the first device, the channel layer includes a first portion and a second portion separated from each other. The first source/rain layer and the second source/drain layer each extend integrally to overlap both the first portion and the second portion of the channel layer. The IC unit further includes a first gate stack surrounding a periphery of the first portion and also a periphery of the second portion of the channel layer of the first device, and a second gate stack surrounding a periphery of the channel layer of the second device.
    Type: Application
    Filed: May 23, 2019
    Publication date: September 19, 2019
    Inventors: Huilong Zhu, Zhengyong Zhu
  • Publication number: 20190279980
    Abstract: There are provided a semiconductor device, a method of manufacturing the same, and an electronic device including the device. According to an embodiment, the semiconductor device may include a substrate, and a first device and a second device formed on the substrate. Each of the first device and the second device includes a first source/drain layer, a channel layer and a second source/drain layer stacked on the substrate in sequence, and also a gate stack surrounding a periphery of the channel layer. The channel layer of the first device and the channel layer of the second device are substantially co-planar with each other, and the respective second source/drain layers of the first device and the second device are stressed differently.
    Type: Application
    Filed: July 31, 2017
    Publication date: September 12, 2019
    Inventor: Huilong ZHU
  • Publication number: 20190267466
    Abstract: A method of manufacturing a semiconductor device may include: forming a fin-shaped structure on a substrate; forming a supporting layer on the substrate having the fin-shaped structure formed thereon, and patterning the supporting layer into a supporting portion extending from a surface of the substrate to a surface of the fin-shaped structure and thus physically connecting them; removing a portion of the fin-shaped structure close to the substrate to form a first semiconductor layer spaced apart from the substrate; growing a second semiconductor layer with the first semiconductor layer as a seed layer; and in at least a fraction of the longitudinal extent, removing the first semiconductor layer, and cutting off the second semiconductor layer on sides of the first semiconductor layer away from the substrate and close to the substrate, respectively, so that the cut-off second semiconductor layer acts as a fin of the device.
    Type: Application
    Filed: June 27, 2016
    Publication date: August 29, 2019
    Inventor: Huilong ZHU
  • Publication number: 20190252538
    Abstract: There are provided a Fin Field Effect Transistor (FinFET), a method of manufacturing the same, and an electronic device including the same. According to embodiments, the FinFET may include a fin formed on a substrate, a gate stack formed on the substrate and intersecting the fin, and a gate spacer formed on sidewalls of the gate stack. The gate spacer may include a dielectric material and a negative capacitance material.
    Type: Application
    Filed: June 27, 2016
    Publication date: August 15, 2019
    Inventor: Huilong Zhu
  • Publication number: 20190189523
    Abstract: A semiconductor arrangement includes: a substrate; a plurality of fins formed on the substrate and extending in a first direction; a plurality of gate stacks formed on the substrate and extending in a second direction crossing the first direction and dummy gates composed of dielectric and extending in the second direction, wherein each of the gate stacks intersects at least one of the fins; and spacers formed on sidewalls of the gate stacks and sidewalls of the dummy gates, wherein spacers of at least a first one and a second one among the gate stacks and the dummy gates which are aligned in the second direction extend integrally, and at least some of the fins have ends abutting the dummy gates and substantially aligned with inner walls of corresponding ones of the spacers.
    Type: Application
    Filed: December 21, 2016
    Publication date: June 20, 2019
    Inventors: Huilong ZHU, Huicai ZHONG, Yanbo ZHANG