Patents by Inventor Huilong Zhu

Huilong Zhu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11081484
    Abstract: There are provided an Integrated Circuit (IC) unit, a method of manufacturing the same, and an electronic device including the IC unit. According to an embodiment, the IC unit includes a first source/drain layer, a channel layer and a second source/drain layer for a first device and a first source/drain layer, a channel layer and a second source/drain layer for a second device stacked in sequence on a substrate. In the first device, the channel layer includes a first portion and a second portion separated from each other. The first source/rain layer and the second source/drain layer each extend integrally to overlap both the first portion and the second portion of the channel layer. The IC unit further includes a first gate stack surrounding a periphery of the first portion and also a periphery of the second portion of the channel layer of the first device, and a second gate stack surrounding a periphery of the channel layer of the second device.
    Type: Grant
    Filed: March 5, 2020
    Date of Patent: August 3, 2021
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Huilong Zhu, Zhengyong Zhu
  • Publication number: 20210222303
    Abstract: An embodiment of the present disclosure provides an etching method, having the following steps: forming a modified layer having a thickness of one or several atom layers on a selected region of a surface of a semiconductor material layer by using a modifier; and removing the modified layer. When a semiconductor is processed, this method achieves precise control over the etching thickness and improves the etching rate at the same time.
    Type: Application
    Filed: September 21, 2018
    Publication date: July 22, 2021
    Inventors: Huilong ZHU, Xiaogen YIN, Chen LI, Anyan DU, Yongkui ZHANG
  • Publication number: 20210226004
    Abstract: The present disclosure discloses a semiconductor device with C-shaped channel portion, a method of manufacturing the same, and an electronic apparatus including the same. According to the embodiments, the semiconductor device may comprise a channel portion on a substrate, the channel portion including two or more curved nanosheets or nanowires spaced apart from each other in a lateral direction relative to the substrate and each having a C-shaped cross section; source/drain portions respectively located at upper and lower ends of the channel portion relative to the substrate; and a gate stack surrounding an outer circumference of each nanosheet or nanowire in the channel portion.
    Type: Application
    Filed: January 20, 2021
    Publication date: July 22, 2021
    Inventor: Huilong ZHU
  • Publication number: 20210226069
    Abstract: A semiconductor device with C-shaped channel portion and an electronic apparatus including the semiconductor device are disclosed. According to the embodiments, the semiconductor device may include a first semiconductor element and a second semiconductor element adjacent in a first direction. The first semiconductor element and the second semiconductor element may respectively include: a channel portion on a substrate, the channel portion including a curved nano-sheet or nano-wire with a C-shaped section; source/drain portions at upper and lower ends of the channel portion with respect to the substrate, respectively; and a gate stack surrounding a periphery of the channel portion. The channel portion of the first semiconductor element and the channel portion of the second semiconductor element may be substantially coplanar.
    Type: Application
    Filed: January 20, 2021
    Publication date: July 22, 2021
    Inventor: Huilong ZHU
  • Publication number: 20210226058
    Abstract: A nanowire semiconductor device having a high-quality epitaxial layer and a method of manufacturing the same are provided. According to an embodiment, the semiconductor device may include: a substrate; one or more nanowires spaced apart from the substrate, wherein the nanowires each extend along a curved longitudinal extending direction; and one or more semiconductor layers formed around peripheries of the respective nanowires to at least partially surround the respective nanowires, wherein the respective semiconductor layers around the respective nanowires are spaced apart from each other.
    Type: Application
    Filed: March 10, 2021
    Publication date: July 22, 2021
    Inventor: Huilong ZHU
  • Publication number: 20210193533
    Abstract: The disclosed technology provides a semiconductor device, a manufacturing method thereof, and an electronic device including the device. An example semiconductor device includes a substrate; a first device and a second device on the substrate. Each of the first device and the second device include a first source/drain layer, a channel layer, and a second source layer that are sequentially stacked, from bottom to top, on the substrate, and a gate stack around at least a part of an outer periphery of the channel layer, with sidewalls of the respective channel layers of the first device and the second device extending at least partially along different crystal planes or crystal plane families.
    Type: Application
    Filed: October 31, 2018
    Publication date: June 24, 2021
    Inventors: Huilong ZHU, Yongkui ZHANG, Xiaogen YIN, Chen Li, Yongbo LIU, Kunpeng JIA
  • Patent number: 11038057
    Abstract: A semiconductor device having a high-quality epitaxial layer and a method of manufacturing the same are provided. According to an embodiment, the semiconductor device may include: a substrate; a first fin-shaped semiconductor layer spaced apart from the substrate, wherein the first semiconductor layer extends along a curved longitudinal extending direction; and a second semiconductor layer at least partially surrounding a periphery of the first semiconductor layer.
    Type: Grant
    Filed: June 27, 2016
    Date of Patent: June 15, 2021
    Assignee: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
    Inventor: Huilong Zhu
  • Publication number: 20210175365
    Abstract: A C-shaped active area semiconductor device and a method of manufacturing the same and electronic device including the semiconductor device are provided. According to embodiments, the semiconductor device includes: a channel portion extending vertically on a substrate; source/drain portions located at upper and lower ends of the channel portion relative to the substrate and along the channel portion, wherein the source/drain portion extends toward a side of the channel portion in a lateral direction relative to the substrate, so that the source/drain portions and the channel portion constitute a C-shaped structure; and a gate stack that overlaps the channel portion on an inner sidewall of the C-shaped structure, wherein the gate stack has a portion surrounded by the C-shaped structure.
    Type: Application
    Filed: December 4, 2020
    Publication date: June 10, 2021
    Inventor: Huilong ZHU
  • Publication number: 20210175332
    Abstract: A semiconductor device with U-shaped channel and electronic apparatus including the same are disclosed. the semiconductor device includes a first device and a second device opposite to each other on a substrate. The two devices each include: a channel portion vertically extending on the substrate and having a U-shape in a plan view; source/drain portions respectively located at upper and lower ends of the channel portion and along the U-shaped channel portion; and a gate stack overlapping the channel portion on an inner side of the U-shape. An opening of the U-shape of the first device and an opening of the U-shape of the second device are opposite to each other. At least a portion of the gate stack of the first device close to the channel portion and at least a portion of the gate stack of the second device close to the channel portion are substantially coplanar.
    Type: Application
    Filed: December 4, 2020
    Publication date: June 10, 2021
    Inventor: Huilong ZHU
  • Publication number: 20210175333
    Abstract: A semiconductor device with a C-shaped active area and an electronic apparatus including the same is disclosed. The semiconductor device may include a first device and a second device opposite to each other on a substrate, each of which includes: a channel portion extending vertically on the substrate; source/drain portions located at the upper and lower ends of the channel portion and along the channel portion, the source/drain portions and the channel portion constitute a C-shaped structure; and a gate stack overlapping the channel portion on an inner sidewall of C-shaped structure, the gate stack has a portion surrounded by the C-shaped structure. The openings of the C-shaped structures of the two devices are opposite to each other. At least a portion of the gate stack of the first device close to the channel portion and that of the second device close to the channel portion are substantially coplanar.
    Type: Application
    Filed: December 4, 2020
    Publication date: June 10, 2021
    Inventor: Huilong ZHU
  • Publication number: 20210175366
    Abstract: A C-shaped active area semiconductor device and a method of manufacturing the same and electronic device including the semiconductor device are provided. According to embodiments, the semiconductor device includes: a channel portion extending vertically on a substrate; source/drain portions located at upper and lower ends of the channel portion relative to the substrate and along the channel portion, wherein the source/drain portion extends toward a side of the channel portion in a lateral direction relative to the substrate, so that the source/drain portions and the channel portion constitute a C-shaped structure; a gate stack that overlaps the channel portion on an inner sidewall of the C-shaped structure, wherein the gate stack has a portion surrounded by the C-shaped structure; and a back gate stack overlapping the channel portion on an outer sidewall of the C-shaped structure.
    Type: Application
    Filed: December 4, 2020
    Publication date: June 10, 2021
    Inventor: Huilong Zhu
  • Publication number: 20210175356
    Abstract: The present disclosure provides a semiconductor device and a manufacturing method thereof, and an electronic device including the semiconductor device. The semiconductor device may include: a substrate; a first source/drain region, a channel region and a second source/drain region stacked sequentially on the substrate and adjacent to each other, and a gate stack formed around an outer periphery of the channel region; wherein the gate stack has a thickness varying in a direction perpendicular to a top surface of the substrate.
    Type: Application
    Filed: December 4, 2020
    Publication date: June 10, 2021
    Inventor: Huilong ZHU
  • Publication number: 20210175344
    Abstract: The present disclosure provides a semiconductor device and a manufacturing method thereof, and an electronic device including the semiconductor device. The semiconductor device includes: a substrate; an active region including a first source/drain region, a channel region and a second source/drain region stacked sequentially on the substrate and adjacent to each other; a gate stack formed around an outer periphery of the channel region; and spacers formed around the outer periphery of the channel region, respectively between the gate stack and the first source/drain region and between the gate stack and the second source/drain region; wherein the spacers each have a thickness varying in a direction parallel to a top surface of the substrate.
    Type: Application
    Filed: December 4, 2020
    Publication date: June 10, 2021
    Inventor: Huilong ZHU
  • Publication number: 20210175355
    Abstract: A semiconductor device with a U-shaped channel and a manufacturing method thereof and an electronic apparatus including the semiconductor device are disclosed. According to embodiments, the semiconductor device may include: a channel portion extending vertically on a substrate and having a U-shape in a plan view; source/drain portions located at upper and lower ends of the channel portion and along the U-shaped channel portion; and a gate stack overlapping the channel portion on an inner side of the U shape.
    Type: Application
    Filed: December 3, 2020
    Publication date: June 10, 2021
    Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
    Inventor: Huilong ZHU
  • Patent number: 11031469
    Abstract: A semiconductor device, a manufacturing method thereof, and an electronic device including the same are provided. According to an embodiment, the semiconductor device may include a substrate; a first source/drain region, a channel region and a second source/drain region stacked on the substrate in sequence and contiguous to each other, and a gate stack formed surrounding a periphery of the channel region; wherein spacers are respectively provided between the gate stack and the first source/drain region and between the gate stack and the second source/drain region in a form of surrounding the periphery of the channel region.
    Type: Grant
    Filed: January 31, 2020
    Date of Patent: June 8, 2021
    Assignee: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
    Inventor: Huilong Zhu
  • Patent number: 10978470
    Abstract: The memory device includes multiple stacked layers of memory cells. Each of the layers includes a first array of first memory cells and a second array of second memory cells, which are nested with each other. The first memory cells and the second memory cells in the respective layers are substantially aligned to each other in a stacking direction of the memory cell layers. Each of the first memory cells is a vertical device based on a first source/drain layer, a channel layer, and a second source/drain layer stacked. Each of the second memory cells is a vertical device based on an active semiconductor layer extending in the stacking direction. The first and second memory cells include respective storage gate stacks, which share a common gate conductor layer. Gate conductor layers in the same memory cell layer are integral with each other.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: April 13, 2021
    Assignee: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
    Inventor: Huilong Zhu
  • Patent number: 10978591
    Abstract: A nanowire semiconductor device having a high-quality epitaxial layer. The semiconductor device may include: a substrate; one or more nanowires spaced apart from the substrate, wherein the nanowires each extend along a curved longitudinal extending direction; and one or more semiconductor layers formed around peripheries of the respective nanowires to at least partially surround the respective nanowires, wherein the respective semiconductor layers around the respective nanowires are spaced apart from each other.
    Type: Grant
    Filed: June 27, 2016
    Date of Patent: April 13, 2021
    Assignee: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
    Inventor: Huilong Zhu
  • Publication number: 20210074334
    Abstract: A semiconductor memory device including a substrate; an array of memory cells arranged in rows and columns on the substrate, each memory cell comprising a vertical pillar-shaped active region having upper and lower source/drain regions and a channel region, and a gate stack formed around the channel region; a plurality of bit lines on the substrate, each bit line located below a column of memory cells and electrically connected to the lower source/drain regions of the memory cells; and a plurality of word lines on the substrate, each word line extending in a row direction and connected to gate conductors of the memory cells in a row of memory cells, each word line comprising first portions extending along peripheries of the memory cells and second portions extending between the first portions, the first portions of the word line extending in a conformal manner with sidewalls of the upper source/drain regions.
    Type: Application
    Filed: September 21, 2018
    Publication date: March 11, 2021
    Inventor: Huilong ZHU
  • Publication number: 20210074857
    Abstract: There are provided a semiconductor device, a method of manufacturing the same, and an electronic device including the device. According to an embodiment, the semiconductor device may include a substrate, and a first device and a second device formed on the substrate. Each of the first device and the second device includes a first source/drain layer, a channel layer and a second source/drain layer stacked on the substrate in sequence, and also a gate stack surrounding a periphery of the channel layer. The channel layer of the first device and the channel layer of the second device are substantially co-planar.
    Type: Application
    Filed: September 25, 2020
    Publication date: March 11, 2021
    Inventor: Huilong ZHU
  • Publication number: 20210043762
    Abstract: There are provided a vertical semiconductor device, a method of manufacturing the same, and an electronic device including the same.
    Type: Application
    Filed: October 31, 2018
    Publication date: February 11, 2021
    Inventor: Huilong ZHU