Patents by Inventor Huilong Zhu

Huilong Zhu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220367628
    Abstract: Provided are a nanowire/nanosheet device with a support portion, a method of manufacturing the same, and an electronic apparatus including the nanowire/nanosheet device.
    Type: Application
    Filed: April 26, 2022
    Publication date: November 17, 2022
    Inventor: Huilong ZHU
  • Patent number: 11502184
    Abstract: The present disclosure provides a semiconductor device and a manufacturing method thereof, and an electronic device including the semiconductor device. The semiconductor device includes: a substrate; an active region including a first source/drain region, a channel region and a second source/drain region stacked sequentially on the substrate and adjacent to each other; a gate stack formed around an outer periphery of the channel region; and spacers formed around the outer periphery of the channel region, respectively between the gate stack and the first source/drain region and between the gate stack and the second source/drain region; wherein the spacers each have a thickness varying in a direction parallel to a top surface of the substrate.
    Type: Grant
    Filed: December 4, 2020
    Date of Patent: November 15, 2022
    Assignee: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
    Inventor: Huilong Zhu
  • Publication number: 20220352335
    Abstract: Provided are a nanowire/nanosheet device with a support portion, a method of manufacturing the nanowire/nanosheet device, and an electronic apparatus including the nanowire/nanosheet device. According to the embodiments, the nanowire/nanosheet device may include: a substrate; a first source/drain layer and a second source/drain layer opposite to each other in a first direction on the substrate; a first nanowire/nanosheet spaced apart from a surface of the substrate and extending from the first source/drain layer to the second source/drain layer; one or more support portions penetrating the first nanowire/nanosheet in a direction perpendicular to the surface of the substrate; and a gate stack extending in a second direction to surround the first nanowire/nanosheet, wherein the second direction intersects the first direction.
    Type: Application
    Filed: April 28, 2022
    Publication date: November 3, 2022
    Inventor: Huilong ZHU
  • Publication number: 20220352310
    Abstract: A semiconductor apparatus with an isolation portion between vertically adjacent elements and an electronic device including the semiconductor apparatus are provided. The semiconductor apparatus may include: a substrate; a first vertical semiconductor element and a second vertical semiconductor element stacked on the substrate sequentially, each of the first vertical semiconductor element and the second vertical semiconductor element including a first source/drain region, a channel region and a second source/drain region stacked sequentially in a vertical direction; and an isolation structure configured to electrically isolate the first vertical semiconductor element from the second vertical semiconductor element, and the isolation structure including a pn junction.
    Type: Application
    Filed: April 28, 2022
    Publication date: November 3, 2022
    Inventor: Huilong ZHU
  • Publication number: 20220352351
    Abstract: Provided are a semiconductor device, a method of manufacturing the semiconductor device, and an electronic apparatus including the device. According to the embodiments, the semiconductor device may include: an active region extending substantially in a vertical direction on a substrate; a gate stack formed around at least a portion of an outer periphery of a middle section of the active region in the vertical direction, wherein the active region comprises a channel region opposite to the gate stack, and a first source/drain region and a second source/drain region located on two opposite sides of the channel region in the vertical direction; a first spacer located between a conductor layer of the gate stack and the first source/drain region, and a second spacer located between the conductor layer of the gate stack and the second source/drain region.
    Type: Application
    Filed: April 28, 2022
    Publication date: November 3, 2022
    Inventor: Huilong Zhu
  • Patent number: 11482279
    Abstract: A Static Random Access Memory (SRAM) cell that may include a first pull-up transistor, a second pull-up transistor, a first pull-down transistor, a second pull-down transistor, a first pass-gate transistor and a second pass-gate transistor provided at two levels on a substrate. The respective transistors may be vertical transistors. The first pull-up transistor and the second pull-up transistor may be provided at a first level, and the first pull-down transistor, the second pull-down transistor, the first pass-gate transistor and the second pass-gate transistor may be provided at a second level different from the first level. A region where the first pull-up transistor and the second pull-up transistor are located and a region where the first pull-down transistor, the second pull-down transistor, the first pass-gate transistor and the second pass-gate transistor are located may at least partially overlap in a vertical direction with respect to an upper surface of the substrate.
    Type: Grant
    Filed: October 31, 2019
    Date of Patent: October 25, 2022
    Assignee: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
    Inventor: Huilong Zhu
  • Patent number: 11482627
    Abstract: A C-shaped active area semiconductor device and a method of manufacturing the same and electronic device including the semiconductor device are provided. According to embodiments, the semiconductor device includes: a channel portion extending vertically on a substrate; source/drain portions located at upper and lower ends of the channel portion relative to the substrate and along the channel portion, wherein the source/drain portion extends toward a side of the channel portion in a lateral direction relative to the substrate, so that the source/drain portions and the channel portion constitute a C-shaped structure; and a gate stack that overlaps the channel portion on an inner sidewall of the C-shaped structure, wherein the gate stack has a portion surrounded by the C-shaped structure.
    Type: Grant
    Filed: December 4, 2020
    Date of Patent: October 25, 2022
    Assignee: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
    Inventor: Huilong Zhu
  • Publication number: 20220328628
    Abstract: The present disclosure provides a semiconductor device and a method of manufacturing the same thereof, and an electronic apparatus including the semiconductor device. According to embodiments of the present disclosure, the semiconductor device includes a channel portion, source/drain portions connected to the channel portion on two opposite sides of the channel portion, and a gate stack intersecting with the channel portion. The channel portion includes a first portion extending in a vertical direction with respect to a substrate and a second portion extending from the first portion to two opposite sides in a lateral direction with respect to the substrate, respectively.
    Type: Application
    Filed: October 29, 2020
    Publication date: October 13, 2022
    Inventor: Huilong Zhu
  • Publication number: 20220310510
    Abstract: An interconnection structure and a method of manufacturing the same, and an electronic device including the interconnection structure are provided.
    Type: Application
    Filed: June 9, 2022
    Publication date: September 29, 2022
    Inventor: Huilong ZHU
  • Patent number: 11447876
    Abstract: An embodiment of the present disclosure provides an etching method, having the following steps: forming a modified layer having a thickness of one or several atom layers on a selected region of a surface of a semiconductor material layer by using a modifier; and removing the modified layer. When a semiconductor is processed, this method achieves precise control over the etching thickness and improves the etching rate at the same time.
    Type: Grant
    Filed: September 21, 2018
    Date of Patent: September 20, 2022
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Huilong Zhu, Xiaogen Yin, Chen Li, Anyan Du, Yongkui Zhang
  • Patent number: 11440740
    Abstract: A frictional force monitoring system for middle troughs of a scraper conveyor, comprising a scraper conveyor system and a sensing detection system. The scraper conveyor system consists of a machine body, middle troughs, thrust lugs, scrapers, a double chain, a sprocket, a speed reducer, an electric motor and a frequency converter. The sensing monitoring system consists of force receiving modules, a three-dimensional force sensor, and a pre-embedded temperature sensor. The frictional force monitoring system is able to monitor impact loads, frictional forces, friction coefficients, temperature, etc. between an annular chain, coal bulk, and middle troughs of the scraper conveyor under complex and severe operating conditions, and to provide the technical means for the design, safety early-warning and health evaluation of the scraper conveyor, and can provide a data basis for studying friction wear and fatigue breaking mechanism of middle troughs of a scraper machine.
    Type: Grant
    Filed: November 26, 2019
    Date of Patent: September 13, 2022
    Assignee: China University of Mining and Technology
    Inventors: Dagang Wang, Ruixin Wang, Zhencai Zhu, Huilong Zhu, Gang Shen, Xiang Li, Yu Tang
  • Publication number: 20220285506
    Abstract: A NOR-type storage device, a method of manufacturing the same, and an electronic apparatus including the same are provided. The NOR-type storage device includes: a gate stack extending vertically on a substrate; an active region surrounding a periphery of the gate stack, the active region including first and second source/drain regions, a first channel region between the first and second source/drain regions, third and fourth source/drain regions, and a second channel region between the third and fourth source/drain regions; first, second, third and fourth interconnection layers extending laterally from the first to fourth source/drain regions, respectively; and a source line contact part extending vertically with respect to the substrate to pass through the first to fourth interconnection layers and electrically connected to one of the first interconnection layer and the second interconnection layer, and to one of the third interconnection layer and the fourth interconnection layer.
    Type: Application
    Filed: March 7, 2022
    Publication date: September 8, 2022
    Inventor: Huilong Zhu
  • Publication number: 20220285559
    Abstract: A vertical storage device, a method of manufacturing the same, and an electronic apparatus including the storage device are provided. The storage device includes: a first source/drain layer located at a first height with respect to a substrate and a second source/drain layer located at a second height different from the first height; a channel layer connecting the first source/drain layer and the second source/drain layer; and a gate stack including a storage function layer, the storage function layer extending on a sidewall of the channel layer and extending in-plane from the sidewall of the channel layer onto a sidewall of the first source/drain layer and a sidewall of the second source/drain layer.
    Type: Application
    Filed: March 7, 2022
    Publication date: September 8, 2022
    Inventor: Huilong ZHU
  • Patent number: 11424323
    Abstract: A semiconductor device with a C-shaped active area and an electronic apparatus including the same is disclosed. The semiconductor device may include a first device and a second device opposite to each other on a substrate, each of which includes: a channel portion extending vertically on the substrate; source/drain portions located at the upper and lower ends of the channel portion and along the channel portion, the source/drain portions and the channel portion constitute a C-shaped structure; and a gate stack overlapping the channel portion on an inner sidewall of C-shaped structure, the gate stack has a portion surrounded by the C-shaped structure. The openings of the C-shaped structures of the two devices are opposite to each other. At least a portion of the gate stack of the first device close to the channel portion and that of the second device close to the channel portion are substantially coplanar.
    Type: Grant
    Filed: December 4, 2020
    Date of Patent: August 23, 2022
    Assignee: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
    Inventor: Huilong Zhu
  • Publication number: 20220254702
    Abstract: A semiconductor apparatus with a heat dissipation conduit in a sidewall interconnection structure, a method of manufacturing the semiconductor apparatus, and an electronic device including the semiconductor apparatus. According to the embodiments, the semiconductor apparatus includes: a carrier substrate having a first region and a second region adjacent to each other; a semiconductor device on the first region; and an interconnection structure on the second region, wherein the interconnection structure includes: an electrical isolation layer; a conductive structure in the electrical isolation layer, wherein at least a part of components require to be electrically connected in the semiconductor device is in contact with and therefore electrically connected to the conductive structure in a lateral direction, wherein the conductive structure is located at a corresponding height in the interconnection structure; and a heat dissipation conduit in the electrical isolation layer.
    Type: Application
    Filed: February 8, 2022
    Publication date: August 11, 2022
    Inventors: Huilong ZHU, Tianchun YE
  • Publication number: 20220246520
    Abstract: An interconnection structure for semiconductor devices formed on a substrate may be arranged under the semiconductor devices. The interconnection structure includes at least one via layer and at least one interconnection layer alternately arranged in a direction from the semiconductor device to the substrate, wherein each via layer includes via holes respectively arranged under at least a part of the semiconductor devices, and each interconnection layer includes conductive nodes respectively arranged under at least a part of the semiconductor devices, and in a same interconnection layer, a conductive channel is provided between at least one conductive node and at least another node; and the via holes in each via layer and the conductive nodes in each interconnection layer corresponding to the via holes at least partially overlap with each other in the direction from the semiconductor device to the substrate.
    Type: Application
    Filed: May 30, 2019
    Publication date: August 4, 2022
    Inventor: Huilong Zhu
  • Patent number: 11404568
    Abstract: A semiconductor device, including: a substrate; a first source/drain layer, a channel layer, and a second source/drain layer sequentially stacked on the substrate and adjacent to each other, and a gate stack formed around an outer circumference of the channel layer; wherein at least one interface structure is formed in at least one of the first source/drain layer and the second source/drain layer, the conduction band energy levels at both sides of the interface structure are different and/or the valence band energy levels are different.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: August 2, 2022
    Assignee: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
    Inventors: Huilong Zhu, Zhenhua Wu
  • Patent number: 11380689
    Abstract: A semiconductor memory device, a method of manufacturing the same, and an electronic device including the semiconductor memory device are disclosed.
    Type: Grant
    Filed: September 21, 2018
    Date of Patent: July 5, 2022
    Assignee: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
    Inventor: Huilong Zhu
  • Publication number: 20220208258
    Abstract: A Static Random Access Memory (SRAM) cell that may include a first pull-up transistor, a second pull-up transistor, a first pull-down transistor, a second pull-down transistor, a first pass-gate transistor and a second pass-gate transistor provided at two levels on a substrate. The respective transistors may be vertical transistors. The first pull-up transistor and the second pull-up transistor may be provided at a first level, and the first pull-down transistor, the second pull-down transistor, the first pass-gate transistor and the second pass-gate transistor may be provided at a second level different from the first level. A region where the first pull-up transistor and the second pull-up transistor are located and a region where the first pull-down transistor, the second pull-down transistor, the first pass-gate transistor and the second pass-gate transistor are located may at least partially overlap in a vertical direction with respect to an upper surface of the substrate.
    Type: Application
    Filed: October 31, 2019
    Publication date: June 30, 2022
    Applicant: INSTITUTE OF MICROELECTRONICS CHINESE ACADEMY OF SCIENCES
    Inventor: Huilong ZHU
  • Patent number: 11373948
    Abstract: An interconnection structure and a method of manufacturing the same, and an electronic device including the interconnection structure are provided.
    Type: Grant
    Filed: April 13, 2018
    Date of Patent: June 28, 2022
    Assignee: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
    Inventor: Huilong Zhu