Abstract: Provided are a semiconductor arrangement and a method for manufacturing the same. An example arrangement may comprise: a bulk semiconductor substrate; a fin formed on the substrate; a first FinFET and a second FinFET formed on the substrate, wherein the first FinFET comprises a first gate stack intersecting the fin and a first gate spacer disposed on sidewalls of the first gate stack, the second FinFET comprises a second gate stack intersecting the fin and a second gate spacer disposed on sidewalls of the second gate stack; a dummy gate spacer formed between the first FinFET and the second FinFET and intersecting the fin; a first isolation section self-aligned to a space defined by the dummy gate spacer, wherein the isolation section electrically isolates the first FinFET from the second FinFET; and a second isolation layer disposed under a bottom surface of the first isolation section.

Abstract: The present disclosure provides a semiconductor device and a manufacturing method thereof, and an electronic device including the semiconductor device. The method includes: forming a first material layer and a second material layer sequentially on a substrate; defining an active region of the semiconductor device on the substrate, the first material layer and the second material layer, wherein the active region includes a channel region; forming spacers around an outer periphery of the channel region, respectively at set positions of the substrate and the second material layer; forming a first source/drain region and a second source/drain region on the substrate and the second material layer respectively; and forming a gate stack around the outer periphery of the channel region; wherein the spacers each have a thickness varying in a direction perpendicular to a direction from the first source/drain region pointing to the second source/drain region.

Abstract: An embodiment of the present disclosure provides an etching method, having the following steps: forming a modified layer having a thickness of one or several atom layers on a selected region of a surface of a semiconductor material layer by using a modifier; and removing the modified layer. When a semiconductor is processed, this method achieves precise control over the etching thickness and improves the etching rate at the same time.

Abstract: Disclosed are a memory device, a method of manufacturing the same, and an electronic apparatus. The memory device includes: first to fourth connection line layers sequentially disposed in a vertical direction relative to a substrate. The first connection line layer includes a plurality of first conductive lines extending parallel in a first direction. One of the second and third connection line layers includes a plurality of conductive lines extending parallel in a second direction intersecting the first direction. The fourth connection line layer includes a plurality of fourth conductive lines extending parallel in a third direction. A memory cell is provided at an intersection of conductive lines. Each memory cell includes first to third transistors stacked in the vertical direction. A fifth connection line layer is provided above the memory cell, and includes a plurality of fifth conductive lines extending in a fourth direction intersecting the third direction.

Abstract: Disclosed are a memory device, a method of manufacturing the same, and an electronic apparatus. The memory device includes: first to fourth connection line layers sequentially disposed in a vertical direction, and adjacent connection line layers respectively include conductive lines extending in directions intersected; a plurality of memory cells respectively including first and second transistors stacked. A first active layer of the first transistor includes first and second source/drain regions respectively electrically connected with conductive lines in the first and second connection line layers. A second active layer of the second transistor includes a first source/drain region electrically connected with a gate conductor layer of the first transistor, and a second source/drain region electrically connected with a conductive line in the third connection line layer.

Abstract: There are provided a semiconductor device, a method of manufacturing the same, and an electronic device including the device. According to an embodiment, the semiconductor device may include a substrate, and a first device and a second device formed on the substrate. Each of the first device and the second device includes a first source/drain layer, a channel layer and a second source/drain layer stacked on the substrate in sequence, and also a gate stack surrounding a periphery of the channel layer. The channel layer of the first device and the channel layer of the second device are substantially co-planar.

Abstract: A semiconductor device with U-shaped channel and electronic apparatus including the same are disclosed. the semiconductor device includes a first device and a second device opposite to each other on a substrate. The two devices each include: a channel portion vertically extending on the substrate and having a U-shape in a plan view; source/drain portions respectively located at upper and lower ends of the channel portion and along the U-shaped channel portion; and a gate stack overlapping the channel portion on an inner side of the U-shape. An opening of the U-shape of the first device and an opening of the U-shape of the second device are opposite to each other. At least a portion of the gate stack of the first device close to the channel portion and at least a portion of the gate stack of the second device close to the channel portion are substantially coplanar.

Abstract: Disclosed are a NOR-type memory device, a method of manufacturing the NOR-type memory device, and an electronic apparatus. The NOR-type memory device includes a plurality of device layers. Each device layer includes a first source/drain region and a second source/drain region at opposite ends of the device layer in a vertical direction, and a channel region between the first source/drain region and the second source/drain region; and a gate stack that extends vertically with respect to the substrate. The gate stack includes a gate conductor layer and a memory functional layer disposed between the gate conductor layer and the device layer. A memory cell is defined at an intersection of the gate stack and the device layer. The memory functional layer includes a first layer having a plurality of portions that correspond to the plurality of device layers respectively and are discontinuous with each other in the vertical direction.

Abstract: Semiconductor arrangements and methods of manufacturing the same. The semiconductor arrangement may include: a substrate including a base substrate, a first semiconductor layer on the substrate, and a second semiconductor layer on the first semiconductor layer; first and second fin structures formed on the substrate and extending in the same straight line, each of the first and second fin structures including at least portions of the second semiconductor layer; a first isolation part formed around the first and second fin structures on opposite sides of the straight line; first and second FinFETs formed on the substrate based on the first and second fin structures respectively; and a second isolation part between the first and second fin structures and intersecting the first and second fin structures to isolate the first and second fin structures from each other.

Abstract: A semiconductor device, a method of manufacturing the semiconductor device, and an electronic apparatus including the semiconductor device are provided. The semiconductor device may include: a plurality of element stacks, wherein each element stack includes a plurality of stacked layers of semiconductor elements, each semiconductor element includes a gate electrode and source/drain regions on opposite sides of the gate electrode; and an interconnection structure between the plurality of element stacks. The interconnection structure includes an electrical isolation layer, and a conductive structure in the electrical isolation layer. At least one of the gate electrode and the source/drain regions of each of at least a part of the semiconductor elements is in contact with and therefore electrically connected to the conductive structure of the interconnection structure at a corresponding height in a lateral direction.

Abstract: Disclosed are a semiconductor device with a ferroelectric or negative capacitance material layer on a sidewall of a gate electrode, a method of manufacturing the semiconductor device, and an electronic apparatus including the semiconductor device. According to embodiments, the semiconductor device may include: a substrate; a gate electrode formed on the substrate; a ferroelectric or negative capacitance material layer formed on a sidewall of the gate electrode; and a source region and a drain region that are located on opposite sides of the gate electrode on the substrate.

Abstract: A semiconductor device and a method for manufacturing the same. A first electrode layer, a semiconductor layer, and a second electrode layer are sequentially formed on a substrate. Then, a part of the semiconductor layer is removed through etching a sidewall of the semiconductor layer to form a cavity. Afterwards, a channel layer is formed at the cavity, a sidewall of the first electrode layer, and a sidewall of the second electrode layer. The channel layer includes a first channel part located in the cavity and a second channel part located outside the cavity. The first channel part is filled with a dummy gate layer. Then, a part of the dummy gate layer is removed through etching a sidewall of the dummy gate layer with the second channel part serving as a shield. Afterwards, the second channel part and the first channel part, which is in contact with an upper surface and a lower surface of the dummy gate layer, are removed to form a recess.

Abstract: Disclosed are a NOR-type memory device and an electronic apparatus. The NOR-type memory device includes a NOR cell array and a peripheral circuit. The NOR cell array includes: a first substrate; an array of memory cells on the first substrate, wherein each memory cell includes a first gate stack extending vertically with respect to the first substrate and an active region surrounding a periphery of the first gate stack; first bonding pads electrically connected to the first gate stacks; and second bonding pads electrically connected to the active regions. The peripheral circuit includes: a second substrate; peripheral circuit elements on the second substrate; and third bonding pads, wherein at least some of the third bonding pads are electrically connected to the peripheral circuit elements. At least some of the first bonding pads and the second bonding pads are opposite to at least some of the third bonding pads.

Abstract: Disclosed are a NOR-type memory device, a method of manufacturing the NOR-type memory device, and an electronic apparatus. The NOR-type memory device may include: a plurality of device layers stacked on a substrate, wherein each device layer includes a first source/drain region and a second source/drain region at opposite ends of the device layer in a vertical direction, and a channel region between the first and second source/drain region; and a gate stack that extends vertically with respect to the substrate to pass through each device layer. The gate stack includes a gate conductor layer and a memory functional layer between the gate conductor layer and the device layer. A memory cell is defined at an intersection of the gate stack and the device layer. A doping concentration in each of the first and second source/drain regions decreases towards the channel region in the vertical direction.

Abstract: A nanowire/nanosheet device having a self-aligned isolation portion and a method of manufacturing the same, and an electronic apparatus including the nanowire/nanosheet device are provided. According to embodiments, the nanowire/nanosheet device includes: a substrate; a nanowire/nanosheet spaced apart from a surface of the substrate and extending in a first direction; a gate stack extending in a second direction to surround the nanowire/nanosheet, where the second direction intersects the first direction; a spacer formed on a sidewall of the gate stack; source/drain layers at opposite ends of the nanowire/nanosheet in the first direction and adjoining the nanowire/nanosheet; and a first isolation portion between the gate stack and the substrate, where the first isolation portion is self-aligned with the gate stack.

Abstract: Disclosed are a NOR-type memory device, a method of manufacturing the NOR-type memory device, and an electronic apparatus. The NOR-type memory device includes: a memory device layer, including a first source/drain region, a second source/drain region and a first channel region; a first gate stack extending vertically to pass through the memory device layer and including a first gate conductor layer and a memory functional layer, and a memory cell is defined at an intersection of the first gate stack and the memory device layer; a selection device layer on the memory device layer, including a third source/drain region, a fourth source/drain region and a second channel region; a second gate stack above the first gate stack and extending vertically to pass through the selection device layer; and a connecting portion electrically connecting the third source/drain region to the first gate conductor layer.

Abstract: A vertical storage device, a method of manufacturing the same, and an electronic apparatus including the storage device are provided. The storage device includes: a first source/drain layer located at a first height with respect to a substrate and a second source/drain layer located at a second height different from the first height; a channel layer connecting the first source/drain layer and the second source/drain layer; and a gate stack including a storage function layer, the storage function layer extending on a sidewall of the channel layer and extending in-plane from the sidewall of the channel layer onto a sidewall of the first source/drain layer and a sidewall of the second source/drain layer.

Abstract: Disclosed is a semiconductor device comprising: a substrate; a vertical active region formed on the substrate and comprising a first source/drain region, a channel region, and a second source/drain region sequentially disposed in a vertical direction, the first source/drain region including a laterally extending portion extending beyond a portion of the active region above the laterally extending portion; a gate stack formed around the periphery of the channel region, the gate stack including a laterally extending portion; and a stack contact portion from above the laterally extending portion of the first source/drain region to the laterally extending portion of the first source/drain region. The stack contact portion comprises a three-layer structure sequentially disposed in the vertical direction: a lower layer portion, a middle layer portion, and an upper layer portion.

Abstract: A compact vertical semiconductor device and a manufacturing method thereof, and an electronic apparatus including the semiconductor device are provided. According to the embodiments, the vertical semiconductor device may include: a plurality of vertical unit devices stacked on each other, in which the unit devices include respective gate stacks extending in a lateral direction, and each of the gate stacks includes a main body, an end portion, and a connection portion located between the main body and the end portion, and in a top view, a periphery of the connection portion is recessed relative to peripheries of the main body and the end portion; and a contact portion located on the end portion of each of the gate stacks, in which the contact portion is in contact with the end portion.

Abstract: A method of manufacturing a semiconductor device includes: providing an element stack on a carrier substrate; forming an interconnection structure connecting the element stack laterally in an area on the carrier substrate adjacent to the element stack, wherein the interconnection structure includes an electrical isolation layer and a conductive structure in the electrical isolation layer; and controlling a height of the conductive structure in the interconnection structure, so that at least a part of components to be electrically connected in the element stack are in contact and therefore electrically connected to the conductive structure at the corresponding height. Forming the conductive structure includes: forming a conductive material layer in the area; forming a mask layer covering the conductive material layer; patterning the mask layer into a pattern corresponding to the conductive structure; and using the mask layer as an etching mask to selectively etch the conductive material layer.