Abstract: A transistor has a channel region in a substrate and source and drain regions in the substrate on opposite sides of the channel region. A gate stack is formed on the substrate above the channel region. This gate stack comprises an interface layer contacting the channel region of the substrate, and a high-k dielectric layer (having a dielectric constant above 4.0) contacting (on) the interface layer. A Nitrogen rich first metal Nitride layer contacts (is on) the dielectric layer, and a metal rich second metal Nitride layer contacts (is on) the first metal Nitride layer. Finally, a Polysilicon cap contacts (is on) the second metal Nitride layer.

Abstract: In one embodiment, the present invention provides a method of manufacturing a semiconducting device that includes providing a silicon containing substrate having PFET device and NFET device, wherein the NFET device includes an amorphous silicon containing region; depositing a tensile strain silicon nitride layer atop the NFET device and the PFET device, wherein the silicon nitride tensile strain layer induces a tensile strain in a channel of the NFET device region; annealing to crystallize the amorphous silicon containing region, wherein the tensile strain silicon nitride layer positioned atop the PFET device confines oxygen within a channel positioned within the silicon containing substrate underlying the PFET device, wherein the oxygen within the channel shifts a threshold voltage of the PFET device towards a valence band of silicon of the silicon containing substrate; and removing the tensile strain silicon nitride layer.

Abstract: An NFET containing a first high-k dielectric portion and a PFET containing a second high-k gate dielectric portion are formed on a semiconductor substrate. A gate sidewall nitride is formed on the gate of the NFET, while the sidewalls of the PFET remain free of the gate sidewall nitride. An oxide spacer is formed directly on the sidewalls of a PFET gate stack and on the gate sidewall nitride on the NFET. After high temperature processing, the first and second dielectric portions contain a non-stoichiometric oxygen deficient high-k dielectric material. The semiconductor structure is subjected to an anneal in an oxygen environment, during which oxygen diffuses through the oxide spacer into the second high-k dielectric portion. The PFET comprises a more stoichiometric high-k dielectric material and the NFET comprises a less stoichiometric high-k dielectric material. Threshold voltages of the PFET and the NFET are optimized by the present invention.