Patents by Inventor Huiming Bu
Huiming Bu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8288218Abstract: A semiconductor device and method for fabricating a semiconductor device include providing a strained semiconductor layer having a first strained axis, forming an active region within a surface of the strained semiconductor layer where the active region has a longitudinal axis along the strained axis and forming gate structures over the active region. Raised source/drain regions are formed on the active regions above and over the surface of the strained semiconductor layer and adjacent to the gate structures to form transistor devices.Type: GrantFiled: January 19, 2010Date of Patent: October 16, 2012Assignee: International Business Machines CorporationInventors: Stephen W. Bedell, Huiming Bu, Kangguo Cheng, Bruce B. Doris, Johnathan E. Faltermeier, Ali Khakifirooz, Devendra K. Sadana, Chun-Chen Yeh
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Publication number: 20120256294Abstract: Techniques for incorporating nanotechnology into decoupling capacitor designs are provided. In one aspect, a decoupling capacitor is provided. The decoupling capacitor comprises a first electrode; an intermediate layer adjacent to the first electrode having a plurality of nanochannels therein; a conformal dielectric layer formed over the intermediate layer and lining the nanochannels; and a second electrode at least a portion of which is formed from an array of nanopillars that fill the nanochannels in the intermediate layer. Methods for fabricating the decoupling capacitor are also provided, as are semiconductor devices incorporating the decoupling capacitor design.Type: ApplicationFiled: June 22, 2012Publication date: October 11, 2012Applicant: International Business Machines CorporationInventors: Satya N. Chakravarti, Dechao Guo, Huiming Bu, Keith Kwong Hon Wong
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Patent number: 8258037Abstract: Techniques for incorporating nanotechnology into decoupling capacitor designs are provided. In one aspect, a decoupling capacitor is provided. The decoupling capacitor comprises a first electrode; an intermediate layer adjacent to the first electrode having a plurality of nanochannels therein; a conformal dielectric layer formed over the intermediate layer and lining the nanochannels; and a second electrode at least a portion of which is formed from an array of nanopillars that fill the nanochannels in the intermediate layer. Methods for fabricating the decoupling capacitor are also provided, as are semiconductor devices incorporating the decoupling capacitor design.Type: GrantFiled: August 26, 2009Date of Patent: September 4, 2012Assignee: International Business Machines CorporationInventors: Satya N. Chakravarti, Dechao Guo, Huiming Bu, Keith Kwong Hon Wong
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Publication number: 20120193712Abstract: A semiconductor device which includes fins of a semiconductor material formed on a semiconductor substrate and then a gate electrode formed over and in contact with the fins. An insulator layer is deposited over the gate electrode and the fins. A trench opening is then etched in the insulator layer. The trench opening exposes the fins and extends between the fins. The fins are then silicided through the trench opening. Then, the trench opening is filled with a metal in contact with the silicided fins to form a local interconnect connecting the fins.Type: ApplicationFiled: January 27, 2011Publication date: August 2, 2012Applicant: International Business Machines CorporationInventors: Andres Bryant, Huiming Bu, Dechao Guo, Wilfried E. Haensch, Chun-Chen Yeh
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Publication number: 20120070947Abstract: A method of forming a fin-shaped field effect transistor (fin-FET) is disclosed. In one embodiment, the method comprises: partially amorphizing a fin overlying a substrate; forming a stress layer over a portion of the partially amorphized fin; annealing to impart stress in the partially amorphized fin to form a stressed fin; removing the stress layer from over the portion of stressed fin; and forming a gate over the stressed fin after the removing of the stress layer.Type: ApplicationFiled: September 16, 2010Publication date: March 22, 2012Applicants: GLOBALFOUNDRIES INC., INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Veeraraghavan S. Basker, Huiming Bu, Effendi Leobandung, Theodorus E. Standaert, Kingsuk Maitra
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Patent number: 8097520Abstract: A passive device structure includes an unpatterned metal gate layer formed in a passive device region of a semiconductor device; an insulator layer formed upon the unpatterned metal gate layer; a semiconductor layer formed upon the insulator layer; and one or more metal contact regions formed in the semiconductor layer; wherein the insulator layer prevents the metal gate layer as serving as a leakage current path for current flowing through a passive device defined by the semiconductor layer and the one or more metal contact regions.Type: GrantFiled: August 19, 2009Date of Patent: January 17, 2012Assignee: International Business Machines CorporationInventors: Huiming Bu, Satya N. Chakravarti, Dechao Guo, Keith Kwong Hon Wong
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Patent number: 8035173Abstract: An NFET containing a first high-k dielectric portion and a PFET containing a second high-k gate dielectric portion are formed on a semiconductor substrate. A gate sidewall nitride is formed on the gate of the NFET, while the sidewalls of the PFET remain free of the gate sidewall nitride. An oxide spacer is formed directly on the sidewalls of a PFET gate stack and on the gate sidewall nitride on the NFET. After high temperature processing, the first and second dielectric portions contain a non-stoichiometric oxygen deficient high-k dielectric material. The semiconductor structure is subjected to an anneal in an oxygen environment, during which oxygen diffuses through the oxide spacer into the second high-k dielectric portion. The PFET comprises a more stoichiometric high-k dielectric material and the NFET comprises a less stoichiometric high-k dielectric material. Threshold voltages of the PFET and the NFET are optimized by the present invention.Type: GrantFiled: February 25, 2010Date of Patent: October 11, 2011Assignee: International Business Machines CorporationInventors: Huiming Bu, Eduard A. Cartier, Bruce B. Doris, Young-Hee Kim, Barry Linder, Vijay Narayanan, Vamsi K. Paruchuri, Michelle L. Steen
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Publication number: 20110221012Abstract: Methods for fabricating gate electrode/high-k dielectric gate structures having an improved resistance to the growth of silicon dioxide (oxide) at the dielectric/silicon-based substrate interface. In an embodiment, a method of forming a transistor gate structure comprises: incorporating nitrogen into a silicon-based substrate proximate a surface of the substrate; depositing a high-k gate dielectric across the silicon-based substrate; and depositing a gate electrode across the high-k dielectric to form the gate structure. In one embodiment, the gate electrode comprises titanium nitride rich in titanium for inhibiting diffusion of oxygen.Type: ApplicationFiled: March 11, 2010Publication date: September 15, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Huiming Bu, Michael P. Chudzik, Wei He, William K. Henson, Siddarth A. Krishnan, Unoh Kwon, Naim Moumen, Wesley C. Natzle
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Publication number: 20110175164Abstract: A semiconductor device and method for fabricating a semiconductor device include providing a strained semiconductor layer having a first strained axis, forming an active region within a surface of the strained semiconductor layer where the active region has a longitudinal axis along the strained axis and forming gate structures over the active region. Raised source/drain regions are formed on the active regions above and over the surface of the strained semiconductor layer and adjacent to the gate structures to form transistor devices.Type: ApplicationFiled: January 19, 2010Publication date: July 21, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Stephen W. Bedell, Huiming Bu, Kangguo Cheng, Bruce B. Doris, Johnathan E. Faltermeier, Ali Khakifirooz, Devendra K. Sadana, Chun-chen Yeh
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Publication number: 20110156158Abstract: A method of forming a semiconductor device is provided that includes forming a Ge-containing layer atop a p-type device regions of the substrate. Thereafter, a first dielectric layer is formed in a second portion of a substrate, and a second dielectric layer is formed overlying the first dielectric layer in the second portion of the substrate and overlying a first portion of the substrate. Gate structures may then formed atop the p-type device regions and n-type device regions of the substrate, in which the gate structures to the n-type device regions include a rare earth metal.Type: ApplicationFiled: March 15, 2011Publication date: June 30, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Renee T. Mo, Huiming Bu, Michael P. Chudzik, William K. Henson, Mukesh V. Khare, Vijay Narayanan
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Publication number: 20110127637Abstract: Techniques for incorporating nanotechnology into electronic fuse (e-fuse) designs are provided. In one aspect, an e-fuse structure is provided. The e-fuse structure includes a first electrode; a dielectric layer on the first electrode having a plurality of nanochannels therein; an array of metal silicide nanopillars that fill the nanochannels in the dielectric layer, each nanopillar in the array serving as an e-fuse element; and a second electrode in contact with the array of metal silicide nanopillars opposite the first electrode. Methods for fabricating the e-fuse structure are also provided as are semiconductor devices incorporating the e-fuse structure.Type: ApplicationFiled: November 30, 2009Publication date: June 2, 2011Applicant: International Business Machines CorporationInventors: Satya N. Chakravarti, Dechao Guo, Huiming Bu, Keith Kwong Hon Wong
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Patent number: 7943460Abstract: A method of forming a semiconductor device is provided that includes forming a Ge-containing layer atop a p-type device regions of the substrate. Thereafter, a first dielectric layer is formed in a second portion of a substrate, and a second dielectric layer is formed overlying the first dielectric layer in the second portion of the substrate and overlying a first portion of the substrate. Gate structures may then formed atop the p-type device regions and n-type device regions of the substrate, in which the gate structures to the n-type device regions include a rare earth metal.Type: GrantFiled: April 20, 2009Date of Patent: May 17, 2011Assignee: International Business Machines CorporationInventors: Renee T. Mo, Huiming Bu, Michael P. Chudzik, William K. Henson, Mukesh V. Khare, Vijay Narayanan
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Publication number: 20110049673Abstract: Techniques for incorporating nanotechnology into decoupling capacitor designs are provided. In one aspect, a decoupling capacitor is provided. The decoupling capacitor comprises a first electrode; an intermediate layer adjacent to the first electrode having a plurality of nanochannels therein; a conformal dielectric layer formed over the intermediate layer and lining the nanochannels; and a second electrode at least a portion of which is formed from an array of nanopillars that fill the nanochannels in the intermediate layer. Methods for fabricating the decoupling capacitor are also provided, as are semiconductor devices incorporating the decoupling capacitor design.Type: ApplicationFiled: August 26, 2009Publication date: March 3, 2011Applicant: International Business Machines CorporationInventors: Satya N. Chakravarti, Dechao Guo, Huiming Bu, Keith Kwon Hon Wong
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Publication number: 20110042786Abstract: A passive device structure includes an unpatterned metal gate layer formed in a passive device region of a semiconductor device; an insulator layer formed upon the unpatterned metal gate layer; a semiconductor layer formed upon the insulator layer; and one or more metal contact regions formed in the semiconductor layer; wherein the insulator layer prevents the metal gate layer as serving as a leakage current path for current flowing through a passive device defined by the semiconductor layer and the one or more metal contact regions.Type: ApplicationFiled: August 19, 2009Publication date: February 24, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Huiming Bu, Satya N. Chakravarti, Dechao Guo, Keith Kwong Hon Wong
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Patent number: 7863123Abstract: A low resistance contact is formed to a metal gate or a transistor including a High-? gate dielectric in a high integration density integrated circuit by applying a liner over a gate stack, applying a fill material between the gate stacks, planarizing the fill material to support high-resolution lithography, etching the fill material and the liner selectively to each other to form vias and filling the vias with a metal, metal alloy or conductive metal compound such as titanium nitride.Type: GrantFiled: January 19, 2009Date of Patent: January 4, 2011Assignee: International Business Machines CorporationInventors: Huiming Bu, Michael P. Chudzik, Ricardo A. Donaton, Naim Moumen, Hongwen Yan
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Publication number: 20100264495Abstract: A method of forming a semiconductor device is provided that includes forming a Ge-containing layer atop a p-type device regions of the substrate. Thereafter, a first dielectric layer is formed in a second portion of a substrate, and a second dielectric layer is formed overlying the first dielectric layer in the second portion of the substrate and overlying a first portion of the substrate. Gate structures may then formed atop the p-type device regions and n-type device regions of the substrate, in which the gate structures to the n-type device regions include a rare earth metal.Type: ApplicationFiled: April 20, 2009Publication date: October 21, 2010Applicant: International Business Machines CorporationInventors: Renee T. Mo, Huiming Bu, Michael P. Chudzik, William K. Henson, Mukesh V. Khare, Vijay Narayanan
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Publication number: 20100244206Abstract: A method of forming a device includes providing a substrate, forming an interfacial layer on the substrate, depositing a high-k dielectric layer on the interfacial layer, depositing an oxygen scavenging layer on the high-k dielectric layer and performing an anneal. A high-k metal gate transistor includes a substrate, an interfacial layer on the substrate, a high-k dielectric layer on the interfacial layer and an oxygen scavenging layer on the high-k dielectric layer.Type: ApplicationFiled: March 31, 2009Publication date: September 30, 2010Applicant: International Business Machines CorporationInventors: Huiming Bu, Michael P. Chudzik, Wei He, Rashmi Jha, Young-Hee Kim, Siddarth A. Krishnan, Renee T. Mo, Naim Moumen, Wesley C. Natzle
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Publication number: 20100181630Abstract: A low resistance contact is formed to a metal gate or a transistor including a High-K gate dielectric in a high integration density integrated circuit by applying a liner over a gate stack, applying a fill material between the gate stacks, planarizing the fill material to support high-resolution lithography, etching the fill material and the liner selectively to each other to form vias and filling the vias with a metal, metal alloy or conductive metal compound such as titanium nitride.Type: ApplicationFiled: January 19, 2009Publication date: July 22, 2010Applicant: International Business Machines CorporationInventors: Huiming Bu, Michael P. Chudzik, Ricardo A. Donaton, Naim Moumen, Hongwen Yan
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Publication number: 20100148273Abstract: An NFET containing a first high-k dielectric portion and a PFET containing a second high-k gate dielectric portion are formed on a semiconductor substrate. A gate sidewall nitride is formed on the gate of the NFET, while the sidewalls of the PFET remain free of the gate sidewall nitride. An oxide spacer is formed directly on the sidewalls of a PFET gate stack and on the gate sidewall nitride on the NFET. After high temperature processing, the first and second dielectric portions contain a non-stoichiometric oxygen deficient high-k dielectric material. The semiconductor structure is subjected to an anneal in an oxygen environment, during which oxygen diffuses through the oxide spacer into the second high-k dielectric portion. The PFET comprises a more stoichiometric high-k dielectric material and the NFET comprises a less stoichiometric high-k dielectric material. Threshold voltages of the PFET and the NFET are optimized by the present invention.Type: ApplicationFiled: February 25, 2010Publication date: June 17, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Huiming Bu, Eduard A. Cartier, Bruce B. Doris, Young-Hee Kim, Barry Linder, Vijay Narayanan, Vamsi K. Paruchuri, Michelle L. Steen
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Patent number: 7696036Abstract: An NFET containing a first high-k dielectric portion and a PFET containing a second high-k gate dielectric portion are formed on a semiconductor substrate. A gate sidewall nitride is formed on the gate of the NFET, while the sidewalls of the PFET remain free of the gate sidewall nitride. An oxide spacer is formed directly on the sidewalls of a PFET gate stack and on the gate sidewall nitride on the NFET. After high temperature processing, the first and second dielectric portions contain a non-stoichiometric oxygen deficient high-k dielectric material. The semiconductor structure is subjected to an anneal in an oxygen environment, during which oxygen diffuses through the oxide spacer into the second high-k dielectric portion. The PFET comprises a more stoichiometric high-k dielectric material and the NFET comprises a less stoichiometric high-k dielectric material. Threshold voltages of the PFET and the NFET are optimized by the present invention.Type: GrantFiled: June 14, 2007Date of Patent: April 13, 2010Assignee: International Business Machines CorporationInventors: Huiming Bu, Eduard A. Cartier, Bruce B. Doris, Young-Hee Kim, Barry Linder, Vijay Narayanan, Vamsi K. Paruchuri, Michelle L. Steen