Patents by Inventor Huixiong Dai

Huixiong Dai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200075422
    Abstract: Methods of forming and processing semiconductor devices which utilize a three-color hardmask process are described. Certain embodiments relate to the formation of self-aligned contacts for metal gate applications. More particularly, certain embodiments relate to the formation of self-aligned gate contacts through the selective deposition of a fill material.
    Type: Application
    Filed: August 26, 2019
    Publication date: March 5, 2020
    Inventors: Wenhui Wang, Huixiong Dai, Christopher S. Ngai
  • Publication number: 20200075408
    Abstract: Methods of forming and processing semiconductor devices which utilize a three-color process are described. Certain embodiments relate to the formation of self-aligned contacts for metal gate applications. More particularly, certain embodiments relate to the formation of self-aligned gate contacts utilizing selective deposition of overlapping masks in a three-color process.
    Type: Application
    Filed: September 3, 2019
    Publication date: March 5, 2020
    Inventors: Wenhui Wang, Huixiong Dai, Christopher S. Ngai
  • Publication number: 20200075409
    Abstract: Methods of forming and processing semiconductor devices which utilize a three-color hardmask process are described. Certain embodiments relate to the formation of self-aligned contacts for metal gate applications. More particularly, certain embodiments relate to the formation of self-aligned gate contacts utilizing selective deposition of masks in a three-color process.
    Type: Application
    Filed: September 3, 2019
    Publication date: March 5, 2020
    Inventors: Wenhui Wang, Huixiong Dai, Christopher S. Ngai
  • Patent number: 10545408
    Abstract: A method of patterning a substrate may include providing a blanket photoresist layer on the substrate; performing an ion implantation procedure of an implant species into the blanket photoresist layer, the implant species comprising an enhanced absorption efficiency at a wavelength in the extreme ultraviolet (EUV) range; and subsequent to the performing the ion implantation procedure, performing a patterned exposure to expose the blanket photoresist layer to EUV radiation.
    Type: Grant
    Filed: October 18, 2017
    Date of Patent: January 28, 2020
    Assignee: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.
    Inventors: Tristan Y. Ma, Huixiong Dai, Anthony Renau, John Hautala, Joseph Olson
  • Patent number: 10381232
    Abstract: A method may include providing a surface feature on a substrate, the surface feature comprising a feature shape a feature location, and a dimension along a first direction within a substrate plane; depositing a layer comprising a layer material on the surface feature; and directing ions in an ion exposure at an angle of incidence toward the substrate, the angle of incidence forming a non-zero angle with respect to a perpendicular to the substrate plane, wherein the ion exposure comprises the ions and reactive neutral species, the ion exposure reactively etching the layer material, wherein the ions impact a first portion of the surface feature and do not impact a second portion of the surface feature, and wherein an altered surface feature is generated, the altered surface feature differing from the surface feature in at least one of: the dimension along the first direction, the feature shape, or the feature location.
    Type: Grant
    Filed: May 11, 2018
    Date of Patent: August 13, 2019
    Assignee: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.
    Inventors: Simon Ruffell, Huixiong Dai, Jun Lang, John Hautala
  • Publication number: 20190212656
    Abstract: Methods for depositing an EUV hardmask film on a substrate by physical vapor deposition which allow for reduced EUV dose. Certain embodiments relate to metal oxide hardmasks which require smaller amounts of EUV energy for processing and allow for higher throughput. A silicon or metal target can be sputtered onto a substrate in the presence of an oxygen and or doping gas containing plasma.
    Type: Application
    Filed: January 10, 2019
    Publication date: July 11, 2019
    Inventors: Huixiong Dai, Weimin Zeng, Daniel Lee Diehl, Yong Cao, Hsiang Ning Wu, Khoi Phan, Christopher S. Ngai, Mingwei Zhu, Michael Stolfi, Nelson M. Felix, Ekmini Anuja DeSilva, Xianmin Tang
  • Patent number: 10234772
    Abstract: A calibration curve for a wafer comprising a layer on a substrate is determined. The calibration curve represents a local parameter change as a function of a treatment parameter associated with a wafer exposure to a light. The local parameter of the wafer is measured. An overlay error is determined based on the local parameter of the wafer. A treatment map is computed based on the calibration curve to correct the overlay error for the wafer. The treatment map represents the treatment parameter as a function of a location on the wafer.
    Type: Grant
    Filed: December 1, 2017
    Date of Patent: March 19, 2019
    Assignee: Applied Materials, Inc.
    Inventors: Mangesh Bangar, Bruce E. Adams, Kelly E. Hollar, Abhilash J. Mayur, Huixiong Dai, Jaujiun Chen
  • Publication number: 20190056914
    Abstract: A method of patterning a substrate may include providing a blanket photoresist layer on the substrate; performing an ion implantation procedure of an implant species into the blanket photoresist layer, the implant species comprising an enhanced absorption efficiency at a wavelength in the extreme ultraviolet (EUV) range; and subsequent to the performing the ion implantation procedure, performing a patterned exposure to expose the blanket photoresist layer to EUV radiation.
    Type: Application
    Filed: October 18, 2017
    Publication date: February 21, 2019
    Applicant: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Tristan Y. Ma, Huixiong Dai, Anthony Renau, John Hautala, Joseph Olson
  • Publication number: 20180330944
    Abstract: A method of patterning a substrate. The method may include providing a surface feature on the substrate, the surface feature having a first dimension along a first direction within a substrate plane, and a second dimension along a second direction within the substrate plane, wherein the second direction is perpendicular to the first direction; and directing first ions in a first exposure to the surface feature along the first direction at a non-zero angle of incidence with respect to a perpendicular to the substrate plane, in a presence of a reactive ambient containing a reactive species; wherein the first exposure etches the surface feature along the first direction, wherein after the directing, the surface feature retains the second dimension along the second direction, and wherein the surface feature has a third dimension along the first direction different than the first dimension.
    Type: Application
    Filed: May 14, 2018
    Publication date: November 15, 2018
    Applicant: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Simon Ruffell, John Hautala, Adam Brand, Huixiong Dai
  • Publication number: 20180261463
    Abstract: A method may include providing a surface feature on a substrate, the surface feature comprising a feature shape a feature location, and a dimension along a first direction within a substrate plane; depositing a layer comprising a layer material on the surface feature; and directing ions in an ion exposure at an angle of incidence toward the substrate, the angle of incidence forming a non-zero angle with respect to a perpendicular to the substrate plane, wherein the ion exposure comprises the ions and reactive neutral species, the ion exposure reactively etching the layer material, wherein the ions impact a first portion of the surface feature and do not impact a second portion of the surface feature, and wherein an altered surface feature is generated, the altered surface feature differing from the surface feature in at least one of: the dimension along the first direction, the feature shape, or the feature location.
    Type: Application
    Filed: May 11, 2018
    Publication date: September 13, 2018
    Applicant: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Simon Ruffell, Huixiong Dai, Jun Lang, John Hautala
  • Patent number: 10008384
    Abstract: A method of patterning a substrate. The method may include providing a surface feature on the substrate, the surface feature having a first dimension along a first direction within a substrate plane, and a second dimension along a second direction within the substrate plane, wherein the second direction is perpendicular to the first direction; and directing first ions in a first exposure to the surface feature along the first direction at a non-zero angle of incidence with respect to a perpendicular to the substrate plane, in a presence of a reactive ambient containing a reactive species; wherein the first exposure etches the surface feature along the first direction, wherein after the directing, the surface feature retains the second dimension along the second direction, and wherein the surface feature has a third dimension along the first direction different than the first dimension.
    Type: Grant
    Filed: June 25, 2015
    Date of Patent: June 26, 2018
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Simon Ruffell, John Hautala, Adam Brand, Huixiong Dai
  • Patent number: 9984889
    Abstract: A method may include providing a surface feature on a substrate, the surface feature comprising a feature shape a feature location, and a dimension along a first direction within a substrate plane; depositing a layer comprising a layer material on the surface feature; and directing ions in an ion exposure at an angle of incidence toward the substrate, the angle of incidence forming a non-zero angle with respect to a perpendicular to the substrate plane, wherein the ion exposure comprises the ions and reactive neutral species, the ion exposure reactively etching the layer material, wherein the ions impact a first portion of the surface feature and do not impact a second portion of the surface feature, and wherein an altered surface feature is generated, the altered surface feature differing from the surface feature in at least one of: the dimension along the first direction, the feature shape, or the feature location.
    Type: Grant
    Filed: April 29, 2016
    Date of Patent: May 29, 2018
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Simon Ruffell, Huixiong Dai, Jun Lang, John Hautala
  • Publication number: 20180142343
    Abstract: In some embodiments, a method of processing a substrate disposed atop a substrate support in a physical vapor deposition process chamber includes: (a) forming a plasma from a process gas within a processing region of the physical vapor deposition chamber, wherein the process gas comprises an inert gas and a hydrogen-containing gas to sputter silicon from a surface of a target within the processing region of the physical vapor deposition chamber; and (b) depositing an amorphous silicon layer atop a first layer on the substrate, wherein adjusting the flow rate of the hydrogen containing gas tunes the optical properties of the deposited amorphous silicon layer.
    Type: Application
    Filed: November 16, 2017
    Publication date: May 24, 2018
    Inventors: Weimin ZENG, Yong CAO, Daniel Lee DIEHL, Huixiong DAI, Khoi PHAN, Christopher NGAI, Rongjun WANG, Xianmin TANG
  • Publication number: 20180135183
    Abstract: Processing methods comprising depositing an initial hardmask film on a substrate by physical vapor deposition and exposing the initial hardmask film to a treatment plasma comprising a silane compound to form the hardmask.
    Type: Application
    Filed: November 8, 2017
    Publication date: May 17, 2018
    Inventors: Weimin Zeng, Yong Cao, Daniel Lee Diehl, Khoi Phan, Huixiong Dai, Christopher S. Ngai
  • Publication number: 20180101103
    Abstract: A calibration curve for a wafer comprising a layer on a substrate is determined. The calibration curve represents a local parameter change as a function of a treatment parameter associated with a wafer exposure to a light. The local parameter of the wafer is measured. An overlay error is determined based on the local parameter of the wafer. A treatment map is computed based on the calibration curve to correct the overlay error for the wafer. The treatment map represents the treatment parameter as a function of a location on the wafer.
    Type: Application
    Filed: December 1, 2017
    Publication date: April 12, 2018
    Inventors: Mangesh BANGAR, Bruce E. ADAMS, Kelly E. HOLLAR, Abhilash J. MAYUR, Huixiong DAI, Jaujiun CHEN
  • Patent number: 9864280
    Abstract: A calibration curve for a wafer comprising a layer on a substrate is determined. The calibration curve represents a local parameter change as a function of a treatment parameter associated with a wafer exposure to a light. The local parameter of the wafer is measured. An overlay error is determined based on the local parameter of the wafer. A treatment map is computed based on the calibration curve to correct the overlay error for the wafer. The treatment map represents the treatment parameter as a function of a location on the wafer.
    Type: Grant
    Filed: October 2, 2015
    Date of Patent: January 9, 2018
    Assignee: Applied Materials, Inc.
    Inventors: Mangesh Bangar, Bruce E. Adams, Kelly E. Hollar, Abhilash J Mayur, Huixiong Dai, Jaujiun Chen
  • Publication number: 20170372960
    Abstract: A method of forming an interconnect structure for semiconductor or MEMS structures at a 10 nm Node (16 nm HPCD) down to 5 nm Node (7 nm HPCD), or lower, where the conductive contacts of the interconnect structure are fabricated using solely subtractive techniques applied to conformal layers of conductive materials.
    Type: Application
    Filed: September 11, 2017
    Publication date: December 28, 2017
    Inventors: Bencherki Mebarki, Huixiong Dai, Yongmei Chen, He Ren, Mehul Naik
  • Patent number: 9815091
    Abstract: Particulate cleaning assemblies and methods for cleaning are disclosed. In one example, a device for removing particles from a backside surface of a substrate is described. The device includes a chamber body with a substrate chucking device, a particulate cleaning article positioned over the substrate supporting surface, an optical sensing device positioned under the particulate cleaning article and a substrate positioning device separates the particulate cleaning article and a substrate. In another example, a method for removing particles from a substrate is disclosed. The method includes positioning a substrate with a processing surface and a supporting surface in a process chamber. At least a portion of the substrate can be chucked to a substrate chucking device, the substrate chucking device having a substrate supporting surface with a particulate cleaning article positioned thereon. The substrate is then separated from the particulate cleaning article leaving particles behind.
    Type: Grant
    Filed: September 3, 2014
    Date of Patent: November 14, 2017
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Christopher S. Ngai, Huixiong Dai, Ludovic Godet, Ellie Y. Yieh
  • Publication number: 20170263460
    Abstract: A method may include providing a surface feature on a substrate, the surface feature comprising a feature shape a feature location, and a dimension along a first direction within a substrate plane; depositing a layer comprising a layer material on the surface feature; and directing ions in an ion exposure at an angle of incidence toward the substrate, the angle of incidence forming a non-zero angle with respect to a perpendicular to the substrate plane, wherein the ion exposure comprises the ions and reactive neutral species, the ion exposure reactively etching the layer material, wherein the ions impact a first portion of the surface feature and do not impact a second portion of the surface feature, and wherein an altered surface feature is generated, the altered surface feature differing from the surface feature in at least one of: the dimension along the first direction, the feature shape, or the feature location.
    Type: Application
    Filed: April 29, 2016
    Publication date: September 14, 2017
    Inventors: Simon Ruffell, Huixiong Dai, Jun Lang, John Hautala
  • Patent number: 9761489
    Abstract: A method of forming an interconnect structure for semiconductor or MEMS structures at a 10 nm Node (16 nm HPCD) down to 5 nm Node (7 nm HPCD), or lower, where the conductive contacts of the interconnect structure are fabricated using solely subtractive techniques applied to conformal layers of conductive materials.
    Type: Grant
    Filed: August 20, 2013
    Date of Patent: September 12, 2017
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Bencherki Mebarki, Huixiong Dai, Yongmei Chen, He Ren, Mehul Naik