Patents by Inventor Huixiong Dai

Huixiong Dai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210041785
    Abstract: Methods and apparatuses for minimizing line edge/width roughness in lines formed by photolithography are provided. A method of processing a substrate is provided. The method includes applying a photoresist layer that includes a photoacid generator to a multi-layer disposed on the substrate. The multi-layer includes an underlayer. Further, the method includes exposing a first portion of the photoresist layer unprotected by a photomask to a radiation light in a lithographic exposure process. A thermal energy is provided to the photoresist layer and the multi-layer in a post-exposure baking process. The multi-layer is disposed beneath the photoresist layer. An electric field or a magnetic field is applied to photoresist layer and the multi-layer while performing the post-exposure baking process. An additive within the underlayer is driven in a vertical direction into the photoresist layer. The additive assist in distribution of a photoacid throughout the photoresist layer during the post-exposure baking process.
    Type: Application
    Filed: August 10, 2020
    Publication date: February 11, 2021
    Inventors: Huixiong DAI, Mangesh Ashok BANGAR, Pinkesh Rohit SHAH, Christopher Siu Wing NGAI, Srinivas D. NEMANI, Ellie Y. YIEH
  • Patent number: 10825665
    Abstract: Embodiments of the disclosure include apparatus and methods for modifying a surface of a substrate using a surface modification process. The process of modifying a surface of a substrate generally includes the alteration of a physical or chemical property and/or redistribution of a portion of an exposed material on the surface of the substrate by use of one or more energetic particle beams while the substrate is disposed within a particle beam modification apparatus. Embodiments of the disclosure also provide a surface modification process that includes one or more pre-modification processing steps and/or one or more post-modification processing steps that are all performed within one processing system.
    Type: Grant
    Filed: May 5, 2015
    Date of Patent: November 3, 2020
    Assignee: Applied Materials, Inc.
    Inventors: Ludovic Godet, Huixiong Dai, Srinivas D. Nemani, Ellie Y. Yieh, Nitin Krishnarao Ingle
  • Publication number: 20200255937
    Abstract: Methods and apparatus for processing a substrate. The method, for example, includes directing a stream of material from a PVD source at a first non-perpendicular angle to selectively deposit the material on a top portion of one or more features on the substrate and form a first overhang and a second overhang extending beyond a third sidewall and a fourth sidewall that are arranged parallel and opposite to each other and at non-zero angles to a first sidewall and a second sidewall, the first sidewall and the second sidewall defining a length of the one or more features, and the third sidewall and fourth sidewall defining a width of the one or more features; performing an etch process to selectively remove some of the first sidewall and the second sidewall while keeping the third sidewall and fourth sidewall in intact and maintaining the width of the one or more features.
    Type: Application
    Filed: August 15, 2019
    Publication date: August 13, 2020
    Inventors: BENCHERKI MEBARKI, BYEONG CHAN LEE, HUIXIONG DAI, TEJINDER SINGH, JOUNG JOO LEE, XIANMIN TANG
  • Publication number: 20200233307
    Abstract: Methods and apparatuses for minimizing line edge/width roughness in lines formed by photolithography are provided. In one example, a method of processing a substrate includes applying a photoresist layer comprising a photoacid generator to on a multi-layer disposed on a substrate, wherein the multi-layer comprises an underlayer formed from an organic material, inorganic material, or a mixture of organic and inorganic materials, exposing a first portion of the photoresist layer unprotected by a photomask to a radiation light in a lithographic exposure process, and applying an electric field or a magnetic field to alter movement of photoacid generated from the photoacid generator substantially in a vertical direction.
    Type: Application
    Filed: October 11, 2019
    Publication date: July 23, 2020
    Inventors: Huixiong DAI, Mangesh BANGAR, Christopher S. NGAI, Srinivas D. NEMANI, Ellie Y. YIEH, Steven Hiloong WELCH
  • Publication number: 20200199741
    Abstract: Methods and apparatus for processing a substrate are provided herein. In some embodiments, a method for processing a substrate includes: directing a stream of material from a PVD source toward a surface of a substrate at a first non-perpendicular angle to the plane of the surface to deposit the material on one or more features on the substrate and form a first overhang; etching the layer of the substrate beneath the features selective to the deposited material to form a first part of a pattern; removing the material from the features; directing the stream of material from the PVD source toward the surface of the substrate at a second non-perpendicular angle to the plane of the surface to deposit the material on the features on the substrate and form a second overhang; and etching the layer of the substrate beneath the features selective to the deposited material to form a second part of the pattern.
    Type: Application
    Filed: December 19, 2018
    Publication date: June 25, 2020
    Inventors: BENCHERKI MEBARKI, WENHUI WANG, HUIXIONG DAI, CHRISTOPHER NGAI, JOUNG JOO LEE, XIANMIN TANG
  • Publication number: 20200161181
    Abstract: Implementations of the present disclosure generally relate to the fabrication of integrated circuits, and more particularly, to methods for forming a layer. The layer may be a mask used in lithography process to pattern and form a trench. The mask is formed over a substrate having at least two distinct materials by a selective deposition process. The edges of the mask are disposed on an intermediate layer formed on at least one of the two distinct materials. The method includes removing the intermediate layer to form a gap between edges of the mask and the substrate and filling the gap with a different material than the mask or with the same material as the mask. By filling the gap with the same or different material as the mask, electrical paths are improved.
    Type: Application
    Filed: October 30, 2019
    Publication date: May 21, 2020
    Inventors: Wenhui WANG, Huixiong DAI, Christopher S. NGAI, Liqi WU, Wenyu ZHANG, Yongmei CHEN, Hao CHEN, Keith Tatseun WONG, Ke CHANG
  • Patent number: 10643895
    Abstract: A method of forming an interconnect structure for semiconductor or MEMS structures at a 10 nm Node (16 nm HPCD) down to 5 nm Node (7 nm HPCD), or lower, where the conductive contacts of the interconnect structure are fabricated using solely subtractive techniques applied to conformal layers of conductive materials.
    Type: Grant
    Filed: September 11, 2017
    Date of Patent: May 5, 2020
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Bencherki Mebarki, Huixiong Dai, Yongmei Chen, He Ren, Mehul Naik
  • Publication number: 20200096870
    Abstract: A method of patterning a substrate may include providing a blanket photoresist layer on the substrate; performing an ion implantation procedure of an implant species into the blanket photoresist layer, the implant species comprising an enhanced absorption efficiency at a wavelength in the extreme ultraviolet (EUV) range; and subsequent to the performing the ion implantation procedure, performing a patterned exposure to expose the blanket photoresist layer to EUV radiation.
    Type: Application
    Filed: November 22, 2019
    Publication date: March 26, 2020
    Applicant: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Tristan Y. Ma, Huixiong Dai, Anthony Renau, John Hautala, Joseph Olson
  • Publication number: 20200075408
    Abstract: Methods of forming and processing semiconductor devices which utilize a three-color process are described. Certain embodiments relate to the formation of self-aligned contacts for metal gate applications. More particularly, certain embodiments relate to the formation of self-aligned gate contacts utilizing selective deposition of overlapping masks in a three-color process.
    Type: Application
    Filed: September 3, 2019
    Publication date: March 5, 2020
    Inventors: Wenhui Wang, Huixiong Dai, Christopher S. Ngai
  • Publication number: 20200075409
    Abstract: Methods of forming and processing semiconductor devices which utilize a three-color hardmask process are described. Certain embodiments relate to the formation of self-aligned contacts for metal gate applications. More particularly, certain embodiments relate to the formation of self-aligned gate contacts utilizing selective deposition of masks in a three-color process.
    Type: Application
    Filed: September 3, 2019
    Publication date: March 5, 2020
    Inventors: Wenhui Wang, Huixiong Dai, Christopher S. Ngai
  • Publication number: 20200075422
    Abstract: Methods of forming and processing semiconductor devices which utilize a three-color hardmask process are described. Certain embodiments relate to the formation of self-aligned contacts for metal gate applications. More particularly, certain embodiments relate to the formation of self-aligned gate contacts through the selective deposition of a fill material.
    Type: Application
    Filed: August 26, 2019
    Publication date: March 5, 2020
    Inventors: Wenhui Wang, Huixiong Dai, Christopher S. Ngai
  • Patent number: 10545408
    Abstract: A method of patterning a substrate may include providing a blanket photoresist layer on the substrate; performing an ion implantation procedure of an implant species into the blanket photoresist layer, the implant species comprising an enhanced absorption efficiency at a wavelength in the extreme ultraviolet (EUV) range; and subsequent to the performing the ion implantation procedure, performing a patterned exposure to expose the blanket photoresist layer to EUV radiation.
    Type: Grant
    Filed: October 18, 2017
    Date of Patent: January 28, 2020
    Assignee: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.
    Inventors: Tristan Y. Ma, Huixiong Dai, Anthony Renau, John Hautala, Joseph Olson
  • Patent number: 10381232
    Abstract: A method may include providing a surface feature on a substrate, the surface feature comprising a feature shape a feature location, and a dimension along a first direction within a substrate plane; depositing a layer comprising a layer material on the surface feature; and directing ions in an ion exposure at an angle of incidence toward the substrate, the angle of incidence forming a non-zero angle with respect to a perpendicular to the substrate plane, wherein the ion exposure comprises the ions and reactive neutral species, the ion exposure reactively etching the layer material, wherein the ions impact a first portion of the surface feature and do not impact a second portion of the surface feature, and wherein an altered surface feature is generated, the altered surface feature differing from the surface feature in at least one of: the dimension along the first direction, the feature shape, or the feature location.
    Type: Grant
    Filed: May 11, 2018
    Date of Patent: August 13, 2019
    Assignee: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.
    Inventors: Simon Ruffell, Huixiong Dai, Jun Lang, John Hautala
  • Publication number: 20190212656
    Abstract: Methods for depositing an EUV hardmask film on a substrate by physical vapor deposition which allow for reduced EUV dose. Certain embodiments relate to metal oxide hardmasks which require smaller amounts of EUV energy for processing and allow for higher throughput. A silicon or metal target can be sputtered onto a substrate in the presence of an oxygen and or doping gas containing plasma.
    Type: Application
    Filed: January 10, 2019
    Publication date: July 11, 2019
    Inventors: Huixiong Dai, Weimin Zeng, Daniel Lee Diehl, Yong Cao, Hsiang Ning Wu, Khoi Phan, Christopher S. Ngai, Mingwei Zhu, Michael Stolfi, Nelson M. Felix, Ekmini Anuja DeSilva, Xianmin Tang
  • Patent number: 10234772
    Abstract: A calibration curve for a wafer comprising a layer on a substrate is determined. The calibration curve represents a local parameter change as a function of a treatment parameter associated with a wafer exposure to a light. The local parameter of the wafer is measured. An overlay error is determined based on the local parameter of the wafer. A treatment map is computed based on the calibration curve to correct the overlay error for the wafer. The treatment map represents the treatment parameter as a function of a location on the wafer.
    Type: Grant
    Filed: December 1, 2017
    Date of Patent: March 19, 2019
    Assignee: Applied Materials, Inc.
    Inventors: Mangesh Bangar, Bruce E. Adams, Kelly E. Hollar, Abhilash J. Mayur, Huixiong Dai, Jaujiun Chen
  • Publication number: 20190056914
    Abstract: A method of patterning a substrate may include providing a blanket photoresist layer on the substrate; performing an ion implantation procedure of an implant species into the blanket photoresist layer, the implant species comprising an enhanced absorption efficiency at a wavelength in the extreme ultraviolet (EUV) range; and subsequent to the performing the ion implantation procedure, performing a patterned exposure to expose the blanket photoresist layer to EUV radiation.
    Type: Application
    Filed: October 18, 2017
    Publication date: February 21, 2019
    Applicant: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Tristan Y. Ma, Huixiong Dai, Anthony Renau, John Hautala, Joseph Olson
  • Publication number: 20180330944
    Abstract: A method of patterning a substrate. The method may include providing a surface feature on the substrate, the surface feature having a first dimension along a first direction within a substrate plane, and a second dimension along a second direction within the substrate plane, wherein the second direction is perpendicular to the first direction; and directing first ions in a first exposure to the surface feature along the first direction at a non-zero angle of incidence with respect to a perpendicular to the substrate plane, in a presence of a reactive ambient containing a reactive species; wherein the first exposure etches the surface feature along the first direction, wherein after the directing, the surface feature retains the second dimension along the second direction, and wherein the surface feature has a third dimension along the first direction different than the first dimension.
    Type: Application
    Filed: May 14, 2018
    Publication date: November 15, 2018
    Applicant: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Simon Ruffell, John Hautala, Adam Brand, Huixiong Dai
  • Publication number: 20180261463
    Abstract: A method may include providing a surface feature on a substrate, the surface feature comprising a feature shape a feature location, and a dimension along a first direction within a substrate plane; depositing a layer comprising a layer material on the surface feature; and directing ions in an ion exposure at an angle of incidence toward the substrate, the angle of incidence forming a non-zero angle with respect to a perpendicular to the substrate plane, wherein the ion exposure comprises the ions and reactive neutral species, the ion exposure reactively etching the layer material, wherein the ions impact a first portion of the surface feature and do not impact a second portion of the surface feature, and wherein an altered surface feature is generated, the altered surface feature differing from the surface feature in at least one of: the dimension along the first direction, the feature shape, or the feature location.
    Type: Application
    Filed: May 11, 2018
    Publication date: September 13, 2018
    Applicant: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Simon Ruffell, Huixiong Dai, Jun Lang, John Hautala
  • Patent number: 10008384
    Abstract: A method of patterning a substrate. The method may include providing a surface feature on the substrate, the surface feature having a first dimension along a first direction within a substrate plane, and a second dimension along a second direction within the substrate plane, wherein the second direction is perpendicular to the first direction; and directing first ions in a first exposure to the surface feature along the first direction at a non-zero angle of incidence with respect to a perpendicular to the substrate plane, in a presence of a reactive ambient containing a reactive species; wherein the first exposure etches the surface feature along the first direction, wherein after the directing, the surface feature retains the second dimension along the second direction, and wherein the surface feature has a third dimension along the first direction different than the first dimension.
    Type: Grant
    Filed: June 25, 2015
    Date of Patent: June 26, 2018
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Simon Ruffell, John Hautala, Adam Brand, Huixiong Dai
  • Patent number: 9984889
    Abstract: A method may include providing a surface feature on a substrate, the surface feature comprising a feature shape a feature location, and a dimension along a first direction within a substrate plane; depositing a layer comprising a layer material on the surface feature; and directing ions in an ion exposure at an angle of incidence toward the substrate, the angle of incidence forming a non-zero angle with respect to a perpendicular to the substrate plane, wherein the ion exposure comprises the ions and reactive neutral species, the ion exposure reactively etching the layer material, wherein the ions impact a first portion of the surface feature and do not impact a second portion of the surface feature, and wherein an altered surface feature is generated, the altered surface feature differing from the surface feature in at least one of: the dimension along the first direction, the feature shape, or the feature location.
    Type: Grant
    Filed: April 29, 2016
    Date of Patent: May 29, 2018
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Simon Ruffell, Huixiong Dai, Jun Lang, John Hautala