Abstract: A method of forming an interconnect structure for semiconductor or MEMS structures at a 10 nm Node (16 nm HPCD) down to 5 nm Node (7 nm HPCD), or lower, where the conductive contacts of the interconnect structure are fabricated using solely subtractive techniques applied to conformal layers of conductive materials.

Abstract: The embodiments herein provides methods for forming a PVD silicon oxide or silicon rich oxide, or PVD SiN or silicon rich SiN, or SiC or silicon rich SiC, or combination of the preceding including a variation which includes controlled doping of hydrogen into the compounds heretofore referred to as SiOxNyCz:Hw, where w, x, y, and z can vary in concentration from 0% to 100%, is produced as a hardmask with optical properties that are substantially matched to the photo-resists at the exposure wavelength. Thus making the hardmask optically planarized with respect to the photo-resist. This allows for multiple sequences of litho and etches in the hardmask while the photo-resist maintains essentially no optical topography or reflectivity variations.

Abstract: In some embodiments, a method of forming an etch mask on a substrate is provided that includes (1) forming a resist layer on a substrate; (2) exposing one or more regions of the resist layer to an energy source so as to alter at least one of a physical property and a chemical property of the exposed regions; (3) performing a hardening process on the resist layer to increase the etch resistance of first regions of the resist layer relative to second regions of the resist layer, the hardening process including exposing the resist layer to one or more reactive species within an atomic layer deposition (ALD) chamber; and (4) dry etching the resist layer to remove the one or more second regions and to form a pattern in the resist layer. Other embodiments are provided.

Abstract: Embodiments of the present invention relate to lithographic processes used in integrated circuit fabrication for improving line edge roughness (LER) and reduced critical dimensions (CD) for lines and/or trenches. Embodiments use the combinations of polarized light lithography, shrink coating processes, and double exposure processes to produce synergetic effects in the formation of trench structures having good resolution, reduced CDs, reduced pitch, and reduced LER in the lines and/or trenches of the patterned interconnect structures.

Abstract: A method for doubling the frequency of a lithographic process using a photo-resist template mask is described. A device layer having a photo-resist layer formed thereon is first provided. The photo-resist layer is patterned to form a photo-resist template mask. A spacer-forming material layer is deposited over the photo-resist template mask. The spacer-forming material layer is etched to form a spacer mask and to expose the photo-resist template mask. The photo-resist template mask is then removed and an image of the spacer mask is finally transferred to the device layer.

Abstract: Methods to pattern features in a substrate layer by exposing a photoresist layer more than once. In one embodiment, a single reticle may be exposed more than once with an overlay offset implemented between successive exposures to reduce the half pitch of the reticle. In particular embodiments, these methods may be employed to reduce the half pitch of the features printed with 65 nm generation lithography equipment to achieve 45 nm lithography generation CD and pitch performance.

Abstract: The present invention comprises a method of reducing photoresist mask collapse when the photoresist mask is dried after immersion development. As feature sizes continue to shrink, the capillary force of water used to rinse a photoresist mask approaches the point of being greater than adhesion force of the photoresist to the ARC. When the capillary force exceeds the adhesion force, the features of the mask may collapse because the water pulls adjacent features together as the water dries. By depositing a hermetic oxide layer over the ARC before depositing the photoresist, the adhesion force may exceed the capillary force and the features of the photoresist mask may not collapse.

Abstract: Methods to etch features in a substrate with a multi-layered double patterning mask. The multi-layered double patterning mask includes a carbonaceous mask layer, a first cap layer on the carbonaceous mask layer and a second cap layer on the first cap layer. After forming the multi-layered mask, a first lithographically defined pattern is etched into the second cap layer. A double pattern that is a composition of the first lithographically defined pattern etched in the second cap layer and a second lithographically defined pattern is then etched into the first cap layer and the carbonaceous mask layer. The double pattern formed in the carbonaceous mask layer is then transferred to a substrate layer and any portion of the multi-layered mask remaining is then removed.

Abstract: In one aspect, a method is provided which includes (1) providing a substrate including a photoresist layer and an additional layer which may be a potential source of contaminants, and (2) preventing a release of contaminants from the additional layer, wherein preventing the release of contaminants from the additional layer protects the photoresist layer from exposure to contaminants from the additional layer. Numerous other aspects are provided.

Abstract: Methods to pattern features in a substrate layer by exposing a photoresist layer more than once. In one embodiment, a single reticle may be exposed more than once with an overlay offset implemented between successive exposures to reduce the half pitch of the reticle. In particular embodiments, these methods may be employed to reduce the half pitch of the features printed with 65 nm generation lithography equipment to achieve 45 nm lithography generation CD and pitch performance.

Abstract: Embodiments of the present invention relate to lithographic processes used in integrated circuit fabrication for improving line edge roughness (LER) and reduced critical dimensions (CD) for lines and/or trenches. Embodiments use the combinations of polarized light lithography, shrink coating processes, and double exposure processes to produce synergetic effects in the formation of trench structures having good resolution, reduced CDs, reduced pitch, and reduced LER in the lines and/or trenches of the patterned interconnect structures.

Abstract: A method for doubling the frequency of a lithographic process using a photo-resist template mask is described. A device layer having a photo-resist layer formed thereon is first provided. The photo-resist layer is patterned to form a photo-resist template mask. A spacer-forming material layer is deposited over the photo-resist template mask. The spacer-forming material layer is etched to form a spacer mask and to expose the photo-resist template mask. The photo-resist template mask is then removed and an image of the spacer mask is finally transferred to the device layer.

Abstract: The present invention comprises a method of reducing photoresist mask collapse when the photoresist mask is dried after immersion development. As feature sizes continue to shrink, the capillary force of water used to rinse a photoresist mask approaches the point of being greater than adhesion force of the photoresist to the ARC. When the capillary force exceeds the adhesion force, the features of the mask may collapse because the water pulls adjacent features together as the water dries. By depositing a hermetic oxide layer over the ARC before depositing the photoresist, the adhesion force may exceed the capillary force and the features of the photoresist mask may not collapse.

Abstract: Methods to etch features in a substrate with a multi-layered double patterning mask. The multi-layered double patterning mask includes a carbonaceous mask layer, a first cap layer on the carbonaceous mask layer and a second cap layer on the first cap layer. After forming the multi-layered mask, a first lithographically defined pattern is etched into the second cap layer. A double pattern that is a composition of the first lithographically defined pattern etched in the second cap layer and a second lithographically defined pattern is then etched into the first cap layer and the carbonaceous mask layer. The double pattern formed in the carbonaceous mask layer is then transferred to a substrate layer and any portion of the multi-layered mask remaining is then removed.