Patents by Inventor Huixiong Dai

Huixiong Dai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9748148
    Abstract: Embodiments of the disclosure provide apparatus and methods for localized stress modulation for overlay and edge placement error (EPE) using electron or ion implantation. In one embodiment, a process for correcting overlay error on a substrate generally includes performing a measurement process in a metrology tool on a substrate to obtain a substrate distortion or an overlay error map, determining doping parameters to correct overlay error or substrate distortion based on the overlay error map, and providing a doping recipe to a doping apparatus based on the doping parameters determined to correct substrate distortion or overlay error. Embodiments may also provide performing a doping treatment process on the substrate using the determined doping repair recipe, for example, by comparing the overlay error map or substrate distortion with a database library stored in a computing system.
    Type: Grant
    Filed: June 10, 2015
    Date of Patent: August 29, 2017
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Ellie Y. Yieh, Huixiong Dai, Srinivas D. Nemani, Ludovic Godet, Christopher Dennis Bencher
  • Patent number: 9728406
    Abstract: Embodiments described herein generally relate to methods for device patterning. In various embodiments, a plurality of protrusions and gaps are formed on a substrate, and each gap is formed between adjacent protrusions. Each protrusion includes a first line, a second line and a third line. The first and third lines include a first material, and the second lines include a second material that is different from the first material. A fourth line is deposited in each gap and the fourth line includes a third material that is different than the first and second materials. Because the first, second and third materials are different, one or more lines can be removed by selective etching while adjacent lines that are made of a different material may not be covered by a mask. The critical dimensions (CD) and the edge displacement errors (EPE) of the mask are increased.
    Type: Grant
    Filed: August 4, 2015
    Date of Patent: August 8, 2017
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Huixiong Dai, Christopher S. Ngai
  • Patent number: 9716012
    Abstract: Provided are methods for selective deposition. Certain methods describe providing a first substrate surface; providing a second substrate surface; depositing a first layer of film over the first and second substrate surfaces, wherein the deposition has an incubation delay over the second substrate surface such that the first layer of film over the first substrate surface is thicker than the first layer of film deposited over the second substrate surface; and etching the first layer of film over the first and second substrate surfaces, wherein the first layer of film over the second substrate surface is at least substantially removed, but the first layer of film over the first substrate is only partially removed.
    Type: Grant
    Filed: December 4, 2014
    Date of Patent: July 25, 2017
    Assignee: Applied Materials, Inc.
    Inventors: David Thompson, Huixiong Dai, Patrick M. Martin, Timothy Michaelson, Kadthala R. Narendrnath, Robert Jan Visser, Jingjing Xu, Lin Zhang
  • Publication number: 20170097576
    Abstract: A calibration curve for a wafer comprising a layer on a substrate is determined. The calibration curve represents a local parameter change as a function of a treatment parameter associated with a wafer exposure to a light. The local parameter of the wafer is measured. An overlay error is determined based on the local parameter of the wafer. A treatment map is computed based on the calibration curve to correct the overlay error for the wafer. The treatment map represents the treatment parameter as a function of a location on the wafer.
    Type: Application
    Filed: October 2, 2015
    Publication date: April 6, 2017
    Inventors: Mangesh Bangar, Bruce E. Adams, Kelly E. Hollar, Abhilash J. Mayur, Huixiong Dai, Jaujiun Chen
  • Publication number: 20160379816
    Abstract: A method of patterning a substrate. The method may include providing a surface feature on the substrate, the surface feature having a first dimension along a first direction within a substrate plane, and a second dimension along a second direction within the substrate plane, wherein the second direction is perpendicular to the first direction; and directing first ions in a first exposure to the surface feature along the first direction at a non-zero angle of incidence with respect to a perpendicular to the substrate plane, in a presence of a reactive ambient containing a reactive species; wherein the first exposure etches the surface feature along the first direction, wherein after the directing, the surface feature retains the second dimension along the second direction, and wherein the surface feature has a third dimension along the first direction different than the first dimension.
    Type: Application
    Filed: June 25, 2015
    Publication date: December 29, 2016
    Inventors: Simon Ruffell, John Hautala, Adam Brand, Huixiong Dai
  • Publication number: 20160329222
    Abstract: In some embodiments, a method of forming an etch mask on a substrate is provided that includes (1) forming a resist layer on a substrate; (2) exposing one or more regions of the resist layer to an energy source so as to alter at least one of a physical property and a chemical property of the exposed regions; (3) performing a hardening process on the resist layer to increase the etch resistance of first regions of the resist layer relative to second regions of the resist layer, the hardening process including exposing the resist layer to one or more reactive species within an atomic layer deposition (ALD) chamber; and (4) dry etching the resist layer to remove the one or more second regions and to form a pattern in the resist layer. Other embodiments are provided.
    Type: Application
    Filed: July 21, 2016
    Publication date: November 10, 2016
    Inventors: Peng Xie, Christopher Dennis Bencher, Huixiong Dai, Timothy Michaelson, Subhash Deshmukh
  • Patent number: 9478421
    Abstract: The embodiments herein provides methods for forming a PVD silicon oxide or silicon rich oxide, or PVD SiN or silicon rich SiN, or SiC or silicon rich SiC, or combination of the preceding including a variation which includes controlled doping of hydrogen into the compounds heretofore referred to as SiOxNyCz:Hw, where w, x, y, and z can vary in concentration from 0% to 100%, is produced as a hardmask with optical properties that are substantially matched to the photo-resists at the exposure wavelength. Thus making the hardmask optically planarized with respect to the photo-resist. This allows for multiple sequences of litho and etches in the hardmask while the photo-resist maintains essentially no optical topography or reflectivity variations.
    Type: Grant
    Filed: October 8, 2015
    Date of Patent: October 25, 2016
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Christopher Dennis Bencher, Daniel Lee Diehl, Huixiong Dai, Yong Cao, Tingjun Xu, Weimin Zeng, Peng Xie
  • Patent number: 9411237
    Abstract: In some embodiments, a method of forming an etch mask on a substrate is provided that includes (1) forming a resist layer on a substrate; (2) exposing one or more regions of the resist layer to an energy source so as to alter at least one of a physical property and a chemical property of the exposed regions; (3) performing a hardening process on the resist layer to increase the etch resistance of first regions of the resist layer relative to second regions of the resist layer, the hardening process including exposing the resist layer to one or more reactive species within an atomic layer deposition (ALD) chamber; and (4) dry etching the resist layer to remove the one or more second regions and to form a pattern in the resist layer. Other embodiments are provided.
    Type: Grant
    Filed: March 11, 2014
    Date of Patent: August 9, 2016
    Assignee: Applied Materials, Inc.
    Inventors: Peng Xie, Christopher Dennis Bencher, Huixiong Dai, Timothy Michaelson, Subhash Deshmukh
  • Patent number: 9343309
    Abstract: Methods of laterally oxidizing features of a patterned substrate are described. A capping layer may be disposed above lateral features to laterally confine the oxidation. The oxidizable features may be material patterned near the optical resolution of a photolithography system using a high-resolution photomask. The oxidizable features may be wider than the spaces between the oxidizable features and may be about three times the width of the spaces. Oxidized portions may be formed on either side of repeated oxidizable features. The unoxidized portions may then be removed as part of a self-aligned double patterning (SADP) process. A gapfill layer deposited thereon may be etched or polished back to form alternating fill and non-sacrificial features.
    Type: Grant
    Filed: March 13, 2015
    Date of Patent: May 17, 2016
    Assignee: Applied Materials, Inc.
    Inventors: Mangesh Bangar, Liyan Miao, Huixiong Dai
  • Patent number: 9337051
    Abstract: Embodiments of the disclosure generally provide a method of forming a reduced dimension pattern in a hardmask that is optically matched to an overlying photoresist layer. The method generally comprises of application of a dimension shrinking conformal carbon layer over the field region, sidewalls, and bottom portion of the patterned photoresist and the underlying hardmask at temperatures below the decomposition temperature of the photoresist. The methods and embodiments herein further involve removal of the conformal carbon layer from the bottom portion of the patterned photoresist and the hardmask by an etch process to expose the hardmask, etching the exposed hardmask substrate at the bottom portion, followed by the simultaneous removal of the conformal carbon layer, the photoresist, and other carbonaceous components. A hardmask with reduced dimension features for further pattern transfer is thus yielded.
    Type: Grant
    Filed: July 14, 2015
    Date of Patent: May 10, 2016
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Bencherki Mebarki, Bok Hoen Kim, Deenesh Padhi, Li Yan Miao, Pramit Manna, Christopher Dennis Bencher, Mehul B. Naik, Huixiong Dai, Christopher S. Ngai, Daniel Lee Diehl
  • Publication number: 20160049305
    Abstract: Embodiments of the disclosure generally provide a method of forming a reduced dimension pattern in a hardmask that is optically matched to an overlying photoresist layer. The method generally comprises of application of a dimension shrinking conformal carbon layer over the field region, sidewalls, and bottom portion of the patterned photoresist and the underlying hardmask at temperatures below the decomposition temperature of the photoresist. The methods and embodiments herein further involve removal of the conformal carbon layer from the bottom portion of the patterned photoresist and the hardmask by an etch process to expose the hardmask, etching the exposed hardmask substrate at the bottom portion, followed by the simultaneous removal of the conformal carbon layer, the photoresist, and other carbonaceous components. A hardmask with reduced dimension features for further pattern transfer is thus yielded.
    Type: Application
    Filed: July 14, 2015
    Publication date: February 18, 2016
    Inventors: Bencherki MEBARKI, Bok Hoen KIM, Deenesh PADHI, Li Yan MIAO, Pramit MANNA, Christopher Dennis BENCHER, Mehul B. NAIK, Huixiong DAI, Christopher S. NGAI, Daniel Lee DIEHL
  • Publication number: 20160042951
    Abstract: The embodiments herein provides methods for forming a PVD silicon oxide or silicon rich oxide, or PVD SiN or silicon rich SiN, or SiC or silicon rich SiC, or combination of the preceding including a variation which includes controlled doping of hydrogen into the compounds heretofore referred to as SiOxNyCz:Hw, where w, x, y, and z can vary in concentration from 0% to 100%, is produced as a hardmask with optical properties that are substantially matched to the photo-resists at the exposure wavelength. Thus making the hardmask optically planarized with respect to the photo-resist. This allows for multiple sequences of litho and etches in the hardmask while the photo-resist maintains essentially no optical topography or reflectivity variations.
    Type: Application
    Filed: October 8, 2015
    Publication date: February 11, 2016
    Inventors: Christopher Dennis BENCHER, Daniel Lee DIEHL, Huixiong DAI, Yong CAO, Tingjun XU, Weimin (Wilson) ZENG, Peng XIE
  • Publication number: 20160042950
    Abstract: Embodiments described herein generally relate to methods for device patterning. In various embodiments, a plurality of protrusions and gaps are formed on a substrate, and each gap is formed between adjacent protrusions. Each protrusion includes a first line, a second line and a third line. The first and third lines include a first material, and the second lines include a second material that is different from the first material. A fourth line is deposited in each gap and the fourth line includes a third material that is different than the first and second materials. Because the first, second and third materials are different, one or more lines can be removed by selective etching while adjacent lines that are made of a different material may not be covered by a mask. The critical dimensions (CD) and the edge displacement errors (EPE) of the mask are increased.
    Type: Application
    Filed: August 4, 2015
    Publication date: February 11, 2016
    Inventors: Huixiong DAI, Christopher S. NGAI
  • Publication number: 20160005662
    Abstract: Embodiments of the disclosure provide apparatus and methods for localized stress modulation for overlay and edge placement error (EPE) using electron or ion implantation. In one embodiment, a process for correcting overlay error on a substrate generally includes performing a measurement process in a metrology tool on a substrate to obtain a substrate distortion or an overlay error map, determining doping parameters to correct overlay error or substrate distortion based on the overlay error map, and providing a doping recipe to a doping apparatus based on the doping parameters determined to correct substrate distortion or overlay error. Embodiments may also provide performing a doping treatment process on the substrate using the determined doping repair recipe, for example, by comparing the overlay error map or substrate distortion with a database library stored in a computing system.
    Type: Application
    Filed: June 10, 2015
    Publication date: January 7, 2016
    Inventors: Ellie Y. YIEH, Huixiong DAI, Srinivas D. NEMANI, Ludovic GODET, Christopher Dennis BENCHER
  • Publication number: 20150371879
    Abstract: Particulate cleaning assemblies and methods for cleaning are disclosed. In one example, a device for removing particles from a backside surface of a substrate is described. The device includes a chamber body with a substrate chucking device, a particulate cleaning article positioned over the substrate supporting surface, an optical sensing device positioned under the particulate cleaning article and a substrate positioning device separates the particulate cleaning article and a substrate. In another example, a method for removing particles from a substrate is disclosed. The method includes positioning a substrate with a processing surface and a supporting surface in a process chamber. At least a portion of the substrate can be chucked to a substrate chucking device, the substrate chucking device having a substrate supporting surface with a particulate cleaning article positioned thereon. The substrate is then separated from the particulate cleaning article leaving particles behind.
    Type: Application
    Filed: September 3, 2014
    Publication date: December 24, 2015
    Inventors: Christopher S. NGAI, Huixiong DAI, Ludovic GODET, Ellie Y. YIEH
  • Publication number: 20150325411
    Abstract: Embodiments of the disclosure include apparatus and methods for modifying a surface of a substrate using a surface modification process. The process of modifying a surface of a substrate generally includes the alteration of a physical or chemical property and/or redistribution of a portion of an exposed material on the surface of the substrate by use of one or more energetic particle beams while the substrate is disposed within a particle beam modification apparatus. Embodiments of the disclosure also provide a surface modification process that includes one or more pre-modification processing steps and/or one or more post-modification processing steps that are all performed within one processing system.
    Type: Application
    Filed: May 5, 2015
    Publication date: November 12, 2015
    Inventors: Ludovic GODET, Huixiong DAI, Srinivas D. NEMANI, Ellie Y. YIEH, Nitin Krishnarao INGLE
  • Patent number: 9177796
    Abstract: The embodiments herein provides methods for forming a PVD silicon oxide or silicon rich oxide, or PVD SiN or silicon rich SiN, or SiC or silicon rich SiC, or combination of the preceding including a variation which includes controlled doping of hydrogen into the compounds heretofore referred to as SiOxNyCz:Hw, where w, x, y, and z can vary in concentration from 0% to 100%, is produced as a hardmask with optical properties that are substantially matched to the photo-resists at the exposure wavelength. Thus making the hardmask optically planarized with respect to the photo-resist. This allows for multiple sequences of litho and etches in the hardmask while the photo-resist maintains essentially no optical topography or reflectivity variations.
    Type: Grant
    Filed: May 2, 2014
    Date of Patent: November 3, 2015
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Christopher Dennis Bencher, Daniel Lee Diehl, Huixiong Dai, Yong Cao, Tingjun Xu, Weimin Zeng, Peng Xie
  • Publication number: 20150275364
    Abstract: Provided are apparatus and methods for the sequential deposition and annealing of a film within a single processing chamber. An energy source positioned within the processing chamber in an area isolated from process gases can be used to rapidly form and decompose a film on the substrate without damaging underlying layers due to exceeding the thermal budget of the device being formed.
    Type: Application
    Filed: March 24, 2015
    Publication date: October 1, 2015
    Inventors: David Thompson, Huixiong Dai, Patrick M. Martin, Timothy Michaelson, Kadthala R. Narendrnath, Robert Jan Visser, Jingjing Xu, Lin Zhang
  • Publication number: 20150162214
    Abstract: Provided are methods for selective deposition. Certain methods describe providing a first substrate surface; providing a second substrate surface; depositing a first layer of film over the first and second substrate surfaces, wherein the deposition has an incubation delay over the second substrate surface such that the first layer of film over the first substrate surface is thicker than the first layer of film deposited over the second substrate surface; and etching the first layer of film over the first and second substrate surfaces, wherein the first layer of film over the second substrate surface is at least substantially removed, but the first layer of film over the first substrate is only partially removed.
    Type: Application
    Filed: December 4, 2014
    Publication date: June 11, 2015
    Inventors: David Thompson, Huixiong Dai, Patrick M. Martin, Timothy Michaelson, Kadthala R. Narendrnath, Robert Jan Visser, Jingjing Xu, Lin Zhang
  • Publication number: 20150118832
    Abstract: Embodiments of the present invention provide a methods for patterning a hardmask layer with good process control for an ion implantation process, particularly suitable for manufacturing the fin field effect transistor (FinFET) for semiconductor chips. In one embodiment, a method of patterning a hardmask layer disposed on a substrate includes forming a planarization layer over a hardmask layer disposed on a substrate, disposing a patterned photoresist layer over the planarization layer, patterning the planarization layer and the hardmask layer uncovered by the patterned photoresist layer in a processing chamber, exposing a first portion of the underlying substrate, and removing the planarization layer from the substrate.
    Type: Application
    Filed: October 24, 2013
    Publication date: April 30, 2015
    Inventors: Bingxi Sun WOOD, Li Yan MIAO, Huixiong DAI, Adam BRAND, Yongmei CHEN, Mandar B. PANDIT, Qingjun ZHOU