Abstract: A semiconductor wafer is disclosed that includes a plurality of fields, including a plurality of alignment fields. Each alignment field includes a plurality of intra-field small scribe lane primary mark (SSPM) overlay mark pairs there around. The SSPM mark pairs allow for in-situ, non-passive intra-field alignment correction. In one embodiment, there may be between two and four alignment fields, and between two and four SSPM mark pairs around each alignment field. The SSPM marks of each mark pair may be extra scribe-lane marks.

Abstract: A method of fabricating a photomask having improved critical dimension (CD) uniformity that meets or exceeds 90 nanometer technology requirements. The method includes the steps of: providing a transparent substrate covered with a layer of opaque material and a layer of photoresist; patterning the layer of photoresist to expose an area of the layer of opaque material that has a shape that follows a contour of a main pattern area to be defined by the layer of opaque material; removing the exposed area to define the layer of opaque material into the main pattern area and an area that surrounds the main pattern area; removing the patterned layer of photoresist; and removing the surrounding area of the layer of opaque material.

Abstract: A heat-dissipating fan module of an electronic apparatus is disclosed. The heat-dissipating fan module includes a casing having an opening, the opening having a guiding device along an edge thereof, and a heat-dissipating fan fixed to one side of the casing and correspondingly disposed on the opening.

Abstract: A semiconductor wafer is disclosed that includes a plurality of fields, including a plurality of alignment fields. Each alignment field includes a plurality of intra-field small scribe lane primary mark (SSPM) overlay mark pairs there around. The SSPM mark pairs allow for in-situ, non-passive intra-field alignment correction. In one embodiment, there may be between two and four alignment fields, and between two and four SSPM mark pairs around each alignment field. The SSPM marks of each mark pair may be extra scribe-lane marks.

Abstract: A heat-dispersing module of an electronic device is disclosed.

Abstract: A new method is provided for the creation of a seal ring or fuse ring over the surface of a Phase Shift Mask. A seal ring pattern is created over the surface of a phase shift mask through a layer of phase shift material and a layer of opaque material. The seal ring is surrounded by a layer of opaque material by etching the layer of opaque material.

Abstract: A method of fabricating a photomask having improved critical dimension (CD) uniformity that meets or exceeds 90 nanometer technology requirements. The method includes the steps of: providing a transparent substrate covered with a layer of opaque material and a layer of photoresist; patterning the layer of photoresist to expose an area of the layer of opaque material that has a shape that follows a contour of a main pattern area to be defined by the layer of opaque material; removing the exposed area to define the layer of opaque material into the main pattern area and an area that surrounds the main pattern area; removing the patterned layer of photoresist; and removing the surrounding area of the layer of opaque material.

Abstract: A heat-dispersing module of an electronic device is disclosed.

Abstract: A method and system is disclosed for examining mask pattern fidelity. First, a mask picture is generated from a first mask with a first OPC model applied to a mask design thereon. The mask picture is then converted into a mask based simulation file. A first simulation is conducted under a first set of predetermined lithography processing conditions using the converted simulation file to generate one or more files of a first set representing wafer photo resist profile thereof. On the other hand, a mask design in a database mask file is identified which was used for generating the first mask. The first OPC model is applied to the mask design in the database mask file. A second simulation is then conducted under the first set of predetermined lithography processing conditions using the OPCed mask design to generate one or more files of a second set representing wafer photo resist profile thereof. The first and second sets of files are then evaluated together for the purpose of inspecting mask fidelity.

Abstract: A heat-dissipating fan module of an electronic apparatus is disclosed. The heat-dissipating fan module includes a casing having an opening, the opening having a guiding device along an edge thereof, and a heat-dissipating fan fixed to one side of the casing and correspondingly disposed on the opening.

Abstract: A method and system is disclosed for inspecting defects on a wafer. After acquiring at least one digitized image of at least one portion of a wafer, at least one design database file corresponding to the portion of the wafer is converted into at least one inspection file. After setting one or more error detection thresholds, the digitized image and the inspection file are compared by an inspection tool for detecting defects with regard to the portion of the wafer based on the set error detection thresholds.

Abstract: A tool for placing an identifying mark on a semiconductor wafer has a bundle of optical fibers that can be illuminated in a pattern representing an identifying character. Light from the fibers is focused on a photoresist layer during wafer manufacture and a pattern of dots is etched into the wafer to represent the character. The dots are too small to be seen with the human eye but the character can be read by a human or by a machine. The character is etched as part of a conventional etch step in manufacturing the wafer and it is easily repeated as a series of manufacturing steps obscure the original mark.

Abstract: A method for forming through a microelectronic layer a via contiguous with a trench. There is first provided a substrate. There is then formed over the substrate a first microelectronic layer. There is then formed upon the first microelectronic layer an etch stop layer. There is then formed upon the etch stop layer a second microelectronic layer. There is then formed over the second microelectronic layer a first patterned photoresist layer which defines the location of a via to be formed through the second microelectronic layer, the etch stop layer and the first microelectronic layer. There is then etched, while employing a first etch method which employs the first patterned photoresist layer as a first etch mask layer, the second microelectronic layer, the etch stop layer and the first microelectronic layer to form a corresponding patterned second microelectronic layer, patterned etch stop layer and patterned first microelectronic layer which define the via.

Abstract: A method for forming within a deep ultraviolet (DUV) sensitive photosensitive layer formed upon a substrate employed within a microelectronics fabrication a pattern with attenuated defects and improved strippability. There is provided a substrate employed within a microelectronics fabrication. There is then formed over the substrate a photosensitive layer formed of an organic polymer resin plus additives which is sensitive to deep ultraviolet (DUV) irradiation. There is then formed within the photosensitive layer a patterned latent image by selective irradiation with a deep ultraviolet (DUV) source. There is then developed the latent image by successive treatment of the photosensitive layer to a first developer agent at a first concentration and a second developer agent at a second concentration, interspersed with aqueous solvent rinses, to form a patterned photoresist layer with attenuated residues.

Abstract: A new method is provided for the alignment of the patterning of AlCu pads in an environment of copper interconnect line patterns. A layer of passivation material is deposited over a surface that contains alignment marks. The layer of passivation is patterned creating in the surface of the layer of passivation the opening that is required for the AlCu pad in addition to openings for a new pattern of alignment marks. A layer of AlCu is sputter deposited over the surface of the layer of passivation thereby including the openings that have been created in the layer of passivation. This creates a new pattern of alignment marks in the surface of the deposited layer of AlCu whereby these new alignment marks align with the pattern of new alignment marks that has been etched in the layer of passivation. The new alignment marks are then used to pattern the layer of AlCu for the creation of the AlCu pad.

Abstract: A tool for placing an identifying mark on a semiconductor wafer has a bundle of optical fibers that can be illuminated in a pattern representing an identifying character. Light from the fibers is focused on a photoresist layer during wafer manufacture and a pattern of dots is etched into the wafer to represent the character. The dots are too small to be seen with the human eye but the character can be read by a human or by a machine. The character is etched as part of a conventional etch step in manufacturing the wafer and it is easily repeated as a series of manufacturing steps obscure the original mark.

Abstract: A new method is provided of trench etching of the dual damascene structure. The invention replaces the conventional ARC deposition with the deposition of I-line photoresist. The I-line photoresist serves as an anti reflective coating and eliminates, for small opening size, the problems that are encountered with conventional ARC. The deposition characteristics of the I-line photoresist can be adjusted by pre-baking the I-line photoresist prior to deposition thereby controlling its viscosity and density.

Abstract: A tool and method for placing an identifying mark on a semiconductor wafer has a bundle of optical fibers that can be illuminated in a pattern representing an identifying character. Light from the fibers is focused on a photoresist layer during wafer manufacture and a pattern of dots is etched into the wafer to represent the character. The dots are too small to be seen with the human eye but the character can be read by a human or by a machine. The character is etched as part of a conventional etch step in manufacturing the wafer and it is easily repeated as a series of manufacturing steps obscure the original mark.

Abstract: A method is adapted to form wire interconnect pads on integrated circuit devices and includes the steps of providing a semiconductor substrate having an aluminum-copper top metal layer, and a titanium nitride layer covering the aluminum-copper top metal layer, and a photoresist coating applied to the titanium nitride layer. The photoresist coating is partially exposed and partially developed to form openings for etching an array of submicron size holes. Etching through the titanium nitride layer to the aluminum-copper layer, by way of the partially developed photoresist, forms a rough textured surface profile in the array of cavities, with diameters of less than 0.3 um, etched in the aluminum copper layer. After stripping of the photoresist and depositing a passivation film, windows are formed delineating improved bond pads for wire bonding. The textured cavities increase the surface area of the bond pads and provide improved bondability for the 0.35 and 0.3 um IC devices.

Abstract: A process is described for forming very narrow polysilicon gate lines for use as gate electrodes in FETs. The process uses a consumable hard mask of silicon oxynitride covered by a thin layer of silicon oxide during the etching of the polysilicon. The thicknesses of the two layers that make up the hard mask are chosen so that the structure also serves as an ARC for the photoresist coating immediately above it. A relatively thin layer of the latter is used in order to improve resolution. After the photoresist has been patterned it may be trimmed or it may be removed and re-formed, since the silicon oxide layer provides protection for the underlying silicon oxynitride. After the hard mask has been formed, all photoresist is removed and the polysilicon is etched. During etching there is simultaneous removal of the silicon oxide layer and part of the silicon oxynitride as well.