Abstract: Provided is an exposure apparatus including a variable focusing device. The variable focusing device may include a transparent membrane that may be deformed in the presence of an electric field. The deformation of the transparent membrane may allow the focus length of a radiation beam to be modified. In an embodiment, the variable focusing device may be modulated such that a radiation beam having a first focus length is provided for a first position on an exposure target and a radiation beam having a second focus length is provided for a second position on the exposure target. A method and computer-readable medium are also provided.

Abstract: A method and system is disclosed for inspecting defects on a wafer. After acquiring at least one digitized image of at least one portion of a wafer, at least one design database file corresponding to the portion of the wafer is converted into at least one inspection file. After setting one or more error detection thresholds, the digitized image and the inspection file are compared by an inspection tool for detecting defects with regard to the portion of the wafer based on the set error detection thresholds.

Abstract: A circuit protecting structure of an electronic device includes a circuit carrier and a shielding member. The circuit carrier includes a first surface and a second surface. The second surface includes a specific region thereon. The shielding member includes a shielding frame and a shielding plate. The shielding frame is arranged on the second surface of the circuit carrier and encloses the specific region. The shielding plate is fixed onto the shielding frame. The shielding frame and the shielding plate cooperatively define a closed space for accommodating and shielding the specific region of the circuit carrier.

Abstract: Methods and systems for lithographically exposing a substrate based on a curvature profile of the substrate.

Abstract: A pellicle-mask assembly includes a mask substrate having an absorber pattern, and a hard pellicle held against movement with respect to the mask substrate by gas pressure.

Abstract: A method for photolithography processing includes forming a photoresist layer on a surface of a substrate, baking the substrate to remove solvents from the photoresist layer, cleaning an edge of the substrate with a tape, and exposing the photoresist layer with radiation energy. The tape includes a cleaning material. The tape is positioned proximate to or in contact with the edge of the substrate while the substrate is rotating.

Abstract: A power supply apparatus includes a main body, a power input device, a first power output device and a second power output device. The first power output device includes a first cable and a first connector. The first cable is connected to a first surface of the first connector and includes at least a stop block and at least a fastening element. The second power output device includes a second cable and a second connector. The second cable is connected to a first surface of the second connector and includes an extension part and a retaining wall. An edge of the retaining wall is confined by the stop block and the extension part is clamped by the fastening element so as to selectively combine the first connector with the second connector as a composite connector assembly and facilitate securely fixing the composite connector assembly in a common power socket.

Abstract: A method and system is disclosed for examining mask pattern fidelity. A mask picture is generated from a first mask with a first OPC model applied to a mask design. The mask picture is converted into a mask based simulation file. A first simulation is conducted under a first set of predetermined lithography processing conditions using the converted simulation file to generate one or more files of a first set representing wafer photo resist profile thereof. The first OPC model is applied to the mask design in the database mask file. A second simulation is conducted under the first set of predetermined lithography processing conditions using the OPCed mask design to generate one or more files of a second set representing wafer photo resist profile thereof. The first and second sets of files are evaluated for inspecting mask fidelity.

Abstract: A circuit protecting structure of an electronic device includes a circuit carrier and a shielding member. The circuit carrier includes a first surface and a second surface. The second surface includes a specific region thereon. The shielding member includes a shielding frame and a shielding plate. The shielding frame is arranged on the second surface of the circuit carrier and encloses the specific region. The shielding plate is fixed onto the shielding frame.

Abstract: A mask and method for forming the same including carrying out a photolithographic patterning process the method including providing a substantially light transparent portion; forming a substantially light shielding layer disposed over the substantially light transparent portion; forming at least one barrier layer disposed over the substantially light shielding layer; forming a resist layer disposed over the at least one barrier layer; patterning the resist layer for producing a circuitry pattern; and, carrying out an etching process according to the circuitry pattern to expose a portion of the substantially light transparent portion to form a mask.

Abstract: An assembled structure includes a power semiconductor device, a first insulating member, a heat sink and a fastening element. The power semiconductor device has a first perforation. The first insulating member includes a first opening and a second opening corresponding to the first perforation and a receiving portion between the first opening and a second opening. The fastening element includes a head portion and a body portion. The body portion is penetrated through the first opening, the receiving portion, the second opening and the first perforation such that the power semiconductor device is fastened onto the heat sink.

Abstract: An electrical connector includes a plurality of pins, an isolation body and a latching mechanism. The isolation body has a specified side including a first portion, a second portion and an indentation. The second portion is higher than the first portion. The indentation is formed in the first portion and the second portion. The latching mechanism has an end fixed onto the second portion and extended above a bottom surface of the indentation, wherein the latching mechanism includes at least a fastening part.

Abstract: An electrical connector includes a plurality of pins, an isolation body and a latching mechanism. The isolation body has a specified side including a first portion, a second portion and an indentation. The second portion is higher than the first portion. The indentation is formed in the first portion and the second portion. The latching mechanism has an end fixed onto the second portion and extended above a bottom surface of the indentation, wherein the latching mechanism includes at least a fastening part.

Abstract: Disclosed is a method and a system for optimizing intra-field critical dimension of an integrated circuit. A first mask for an integrated circuit is provided comprising at least one device region. A second mask is provided by copying the first mask and a lithography operation is provided to the integrated circuit using the first and second masks, wherein the critical dimension of the integrated circuit is optimized using the second mask. The second mask comprises a plurality of sacrificial patterns, which may be a plurality of flat patterns or a plurality of grating patterns.

Abstract: Disclosed is a method and a system for optimizing intra-field critical dimension of an integrated circuit. A first mask for an integrated circuit is provided comprising at least one device region. A second mask is provided by copying the first mask and a lithography operation is provided to the integrated circuit using the first and second masks, wherein the critical dimension of the integrated circuit is optimized using the second mask. The second mask comprises a plurality of sacrificial patterns, which may be a plurality of flat patterns or a plurality of grating patterns.

Abstract: Disclosed is a lithography system. The lithography system includes a source designed to provide energy; an imaging system configured to direct the energy onto a substrate to form a predefined image thereon, and defining an optical axis; and an aperture incorporated with the imaging system, the aperture having a plurality of transmitting regions defined along radial axis not parallel to the optical axis, and each transmitting region operable to transmit the energy with adjustable intensity.

Abstract: A power supply apparatus includes a main body, a power input device, a first power output device and a second power output device. The power input device is coupled to an input terminal of the main body. The first power output device includes a first cable and a first connector. The first cable is interconnected between a first output terminal of the main body and a first surface of the first connector. An extension part is extended from the first surface of the first connector. The second power output device includes a second cable and a second connector. A first surface of the second connector is suppressed by the extension part of the first connector to facilitate securely fixing the first connector and the second connector in a power socket, so that a regulated output voltage is outputted from the first and second output devices to the power socket.

Abstract: A method and system is disclosed for examining mask pattern fidelity. A mask picture is generated from a first mask with a first OPC model applied to a mask design. The mask picture is converted into a mask based simulation file. A first simulation is conducted under a first set of predetermined lithography processing conditions using the converted simulation file to generate one or more files of a first set representing wafer photo resist profile thereof. The first OPC model is applied to the mask design in the database mask file. A second simulation is conducted under the first set of predetermined lithography processing conditions using the OPCed mask design to generate one or more files of a second set representing wafer photo resist profile thereof. The first and second sets of files are evaluated for inspecting mask fidelity.

Abstract: A method to prevent photoresist residues formed in an aperture is provided. The method includes using a halogen-containing plasma treatment before the aperture is filled with a photoresist. Due to the halogen-containing plasma treatment, amine components on the sidewalls of a via or contact hole or trench opening can be efficiently removed. Accordingly, photoresist residues or via poison can be avoided.

Abstract: A method for patterning a substrate includes forming a material layer on the substrate; performing a first etching on the material layer to form a pattern; measuring the pattern of the material layer using an optical spectrum metrology tool; determining whether the measuring indicates that the etching step achieved a predefined result; and producing an etching recipe and performing a second etching of the material layer using the etching recipe if the predefined result was not achieved.