Abstract: A method for planarizing a semiconductor device includes providing a substrate having at least one opening therein, each opening defining a lower portion and an upper portion; coating a light sensitive material layer over the substrate, the light sensitive material layer covering the lower and upper portions of the at least one opening; etching back the light sensitive material layer to expose the upper portion of the at least one opening; repeating the steps of coating and etching to remove a predetermined amount below the upper portion of the at least one opening; depositing an insulating layer over the substrate; and planarizing the insulating layer until the upper portion of the at least one opening is exposed.

Abstract: A system for planarizing a semiconductor device includes a holder component for holding the substrate. The substrate has at least one opening therein, and each opening defines a lower portion and an upper portion. A resist applicator applies a layer of resist over the substrate, such that the resist layer covers the lower and upper portions. An etching component etches back the resist layer to expose the upper portion of the at least one opening. The resist applicator and the etching component repeat the steps of applying and etching, respectively, to remove a predetermined amount below the upper portion. A deposition component deposits an insulating layer over the substrate. A planarizing component planarizes the insulating layer until the upper portion of the at least one opening is exposed.

Abstract: A mask substrate, photomask and method for forming the same are provided. The photomask includes a substantially light transparent substrate and a circuitry pattern disposed over the light transparent substrate. The circuitry pattern includes a phase shifting layer disposed over the substantially light transparent substrate. A substantially light shielding layer is disposed over the phase shifting layer. At least one barrier layer is disposed over the substantially light shielding layer. An uppermost portion of the substantially light shielding layer does not comprise anti-reflective properties and the at least one barrier layer comprises an uppermost hardmask layer and an underlying anti-reflective layer.

Abstract: Methods and systems for lithographically exposing a substrate based on a curvature profile of the substrate.

Abstract: A mask and method for forming the same including carrying out a photolithographic patterning process the method including providing a substantially light transparent portion; forming a substantially light shielding layer disposed over the substantially light transparent portion; forming at least one barrier layer disposed over the substantially light shielding layer; forming a resist layer disposed over the at least one barrier layer; patterning the resist layer for producing a circuitry pattern; and, carrying out an etching process according to the circuitry pattern to expose a portion of the substantially light transparent portion to form a mask.

Abstract: Provided is a non-transitory computer readable medium including instructions to generate a level sensor map and create a compensation map from the level sensor map. The level sensor map includes a first determination of a first height above a reference plane of a feature disposed on a semiconductor substrate, and a second determination of a second height above the reference plane of a second feature disposed on a semiconductor substrate. The first and second feature are in a single exposure field. The compensation map includes a determination of at least one parameter to be used during exposure of a single field during an exposure process for the semiconductor substrate.

Abstract: Provided is an exposure apparatus including a variable focusing device. The variable focusing device may include a transparent membrane that may be deformed in the presence of an electric field. The deformation of the transparent membrane may allow the focus length of a radiation beam to be modified. In an embodiment, the variable focusing device may be modulated such that a radiation beam having a first focus length is provided for a first position on an exposure target and a radiation beam having a second focus length is provided for a second position on the exposure target. A method and computer-readable medium are also provided.

Abstract: The present disclosure provides a system and method for manufacturing a mask for semiconductor processing. In one example, the system includes at least one exposure unit configured to select a recipe for a later baking process in a post treatment unit, a buffer unit coupled to the exposure unit and configured to move the mask substrate from the exposure unit to the post treatment unit without exposing the mask substrate to the environment; and the post treatment unit coupled to the buffer unit and the exposure unit and configured to perform a baking process on the mask substrate using baking parameters associated with the recipe selected by the exposure unit.

Abstract: An electrical connector includes a plurality of pins, an isolation body and a latching mechanism. The isolation body includes a receiving part. The receiving part is arranged at a front edge of the isolation body and has a first engaging element. The latching mechanism has a second engaging element engaged with the first engaging element, so that the latching mechanism is fixed onto the isolation body.

Abstract: Disclosed is a method and a system for optimizing intra-field critical dimension of an integrated circuit. A first mask for an integrated circuit is provided comprising at least one device region. A second mask is provided by copying the first mask and a lithography operation is provided to the integrated circuit using the first and second masks, wherein the critical dimension of the integrated circuit is optimized using the second mask. The second mask comprises a plurality of sacrificial patterns, which may be a plurality of flat patterns or a plurality of grating patterns.

Abstract: A hard mask layer and a developable bottom anti-reflective coating (dBARC) layer are formed over a dielectric layer of a substrate. A first photosensitive layer is formed above the dBARC layer, exposed, and developed to form a first pattern. The dBARC layer is developed. The first pattern is etched into the hard mask layer to form a first pattern of openings in the hard mask layer. Following removal of the first photosensitive layer, a second photosensitive layer is formed within the first pattern of openings. The second photosensitive layer is exposed and developed to form a second pattern. The dBARC layer is developed. The second pattern is etched into the hard mask layer to form a second pattern of openings in the hard mask layer. Following the removal of the second photosensitive layer and the dBARC layer, the first and the second patterns are etched into the dielectric layer.

Abstract: A heat-dissipating and fixing mechanism of an electronic component includes a heat-dissipating element, a circuit board and a thermally-conductive adhesive interface. The circuit board has multiple insertion holes. The pins of the electronic component are inserted into corresponding insertion holes of the circuit board. The thermally-conductive adhesive interface has a first surface bonded with the heat-dissipating element and a second surface bonded with the electronic component. As a consequence, the electronic component is fixed on the heat-dissipating element through the thermally-conductive adhesive interface, and the heat generated by the electronic component is transmitted to the heat-dissipating element through the thermally-conductive adhesive interface.

Abstract: Provided is a lithography system operation to include a first aperture or a second aperture. Each of the first and second apertures has two pairs of radiation-transmitting regions where one pair of radiation-transmitting regions are larger than a second pair. For an aperture, each pair of radiation-transmitting regions are on different diametrical axis. In an embodiment, one aperture is used for x-dipole illumination and the second aperture is used for y-dipole illumination.

Abstract: A power supply apparatus includes a main body, a power input device, a first power output device and a second power output device. The first power output device includes a first cable and a first connector. The first cable is connected to a first surface of the first connector and includes at least a stop block and at least a fastening element. The second power output device includes a second cable and a second connector. The second cable is connected to a first surface of the second connector and includes an extension part and a retaining wall. An edge of the retaining wall is confined by the stop block and the extension part is clamped by the fastening element so as to selectively combine the first connector with the second connector as a composite connector assembly and facilitate securely fixing the composite connector assembly in a common power socket.

Abstract: A method for patterning a substrate includes forming a material layer on the substrate; performing a first etching on the material layer to form a pattern; measuring the pattern of the material layer using an optical spectrum metrology tool; determining whether the measuring indicates that the etching step achieved a predefined result; and producing an etching recipe and performing a second etching of the material layer using the etching recipe if the predefined result was not achieved.

Abstract: Disclosed is a lithography system. The lithography system includes a source designed to provide energy; an imaging system configured to direct the energy onto a substrate to form a predefined image thereon, and defining an optical axis; and an aperture incorporated with the imaging system, the aperture having a plurality of transmitting regions defined along radial axis not parallel to the optical axis, and each transmitting region operable to transmit the energy with adjustable intensity.

Abstract: An electrical connector includes a plurality of pins, an isolation body and a latching mechanism. The isolation body includes a receiving part. The receiving part is arranged at a front edge of the isolation body and has a first engaging element. The latching mechanism has a second engaging element engaged with the first engaging element, so that the latching mechanism is fixed onto the isolation body.

Abstract: Disclosed is an improved aperture design for improving critical dimension accuracy and electron beam lithography. A pattern may be created on a reticle by passing an electron beam through a first aperture having a first shape comprising an upper horizontal edge, a lower horizontal edge, a vertical edge, an upper bevel, and a lower bevel, wherein a portion of the electron beam is projected onto a second aperture. The portion of the electronic beam is passed through the second aperture having a second shape, wherein the second shape is the first shape rotated horizontally by 180 degrees, and an overlapped portion of the first and second aperture is exposed on a surface of the reticle to create a pattern.

Abstract: A method includes forming an absorption material layer on a mask; applying a plasma treatment to the mask to reduce chemical contaminants after the forming of the absorption material layer; performing a chemical cleaning process of the mask; and performing a gas injection to the mask.

Abstract: An assembled structure includes a power semiconductor device, a first insulating member, a heat sink and a fastening element. The power semiconductor device has a first perforation. The first insulating member includes a first opening and a second opening corresponding to the first perforation and a receiving portion between the first opening and a second opening. The fastening element includes a head portion and a body portion. The body portion is penetrated through the first opening, the receiving portion, the second opening and the first perforation such that the power semiconductor device is fastened onto the heat sink. The head portion is received in the receiving portion so as to isolate the head portion of the fastening element from adjacent electronic components.