Abstract: A method is adapted to form wire interconnect pads on integrated circuit devices and includes the steps of providing a semiconductor substrate having an aluminum-copper top metal layer, and a titanium nitride layer covering the aluminum-copper top metal layer, and a photoresist coating applied to the titanium nitride layer. The photoresist coating is partially exposed and partially developed to form openings for etching an array of submicron size holes. Etching through the titanium nitride layer to the aluminum-copper layer, by way of the partially developed photoresist, forms a rough textured surface profile in the array of cavities, with diameters of less than 0.3 um, etched in the aluminum copper layer. After stripping of the photoresist and depositing a passivation film, windows are formed delineating improved bond pads for wire bonding. The textured cavities increase the surface area of the bond pads and provide improved bondability for the 0.35 and 0.3 um IC devices.

Abstract: Improved etching of sub-micron diameter via or contact holes in integrated circuits is achieved by first coating the dielectric layer through which the hole is to be etched with successive layers of titanium and silicon oxynitride. This is followed by coating with a conventional photoresist mask which is thinner than usual, thereby allowing for improved resolution. Etching is carried out in two stages. First, only the oxynitride and titanium layers are etched with minimal penetration into the dielectric. In this way a hard mask of titanium is formed. It's optical fidelity is excellent since the combination of silicon oxynitride and titanium act as a very efficient anti-reflection coating. Etching of the hole is then completed using a different etch which also removes the remaining photoresist, the silicon oxynitride as well as some of the titanium.

Abstract: This invention describes a method of making intra-field corrections to the alignment of a step and repeat projection system used to expose image fields on an integrated circuit wafer. A first pattern having first image fields and first alignment marks is formed on a wafer. A mask having a second image field and second alignment marks is projected on the wafers, having a layer of photoresist formed thereon, using light which will not expose the photoresist. The relative location of the second alignment marks to the second image field is the same as the relative location of the first alignment marks to the first image field. A detectors, comprising an interferometer, determines the displacement vector between the first alignment marks and the corresponding second alignment marks. The displacement vectors are fed to a computer which computes a translation correction, a rotation correction, and a magnification correction for the alignment of the mask to the wafer.