Abstract: A device includes a substrate; semiconductor fins extending from the substrate; a liner layer on sidewalls of the semiconductor fins; an etch stop layer over the substrate and extending laterally from a first portion of the liner layer on a first one of the semiconductor fins to a second portion of the line layer on a second one of the semiconductor fins; an isolation structure over the etch stop layer, wherein the etch stop layer and the isolation structure include different materials; a gate dielectric layer over a top surface of the isolation structure; and a dielectric feature extending through the gate dielectric layer and into the isolation structure, wherein the isolation structure and the dielectric feature collectively extend laterally from the first portion of the liner layer to the second portion of the line layer.

Abstract: A semiconductor package structure includes a substrate having a wiring structure. A first semiconductor die is disposed over the substrate and is electrically coupled to the wiring structure. A second semiconductor die is disposed over the substrate and is electrically coupled to the wiring structure, wherein the first semiconductor die and the second semiconductor die are arranged side-by-side. Holes are formed on a surface of the substrate, wherein the holes are located within a projection of the first semiconductor die or the second semiconductor die on the substrate. Further, a molding material surrounds the first semiconductor die and the second semiconductor die, and surfaces of the first semiconductor die and the second semiconductor die facing away from the substrate are exposed by the molding material.

Abstract: An actuating and sensing module is disclosed and includes a bottom plate, a gas pressure sensor, a thin gas transportation device and a cover plate. The bottom plate includes a pressure relief orifice, a discharging orifice and a communication orifice. The gas pressure sensor is disposed on the bottom plate and seals the communication orifice. The thin gas transportation device is disposed on the bottom plate and seals the pressure relief orifice and the discharging orifice. The cover plate is disposed on the bottom plate and covers the gas pressure sensor and the thin gas-transportation device. The cover plate includes an intake orifice. The thin gas transportation device is driven to inhale gas through the intake orifice, the gas is then discharged through the discharging orifice by the thin gas transportation device, and a pressure change of the gas is sensed by the gas pressure sensor.

Abstract: A planar winding transformer includes a magnetic core set and a multilayer circuit board. The magnetic core set includes two magnetic cores and two magnetic columns. The two magnetic cores are parallel to each other. The multilayer circuit board is disposed between two magnetic cores, and two magnetic columns penetrate through the multilayer circuit board. The multilayer circuit board includes two low voltage winding layers and one high voltage winding layer. Two low voltage winding layers are connected to each other in parallel, and the high voltage winding layer is disposed between two low voltage winding layers. When the high voltage winding layer receives a polarity current, at least one of the low voltage winding layers generates a corresponding induced current. Two magnetic cores and two magnetic columns form a closed path for magnetic flux.

Abstract: A method for manufacturing an integrated circuit includes patterning a plurality of photomask layers over a substrate, partially backfilling the patterned plurality of photomask layers with a first material using atomic layer deposition, completely backfilling the patterned plurality of photomask layers with a second material using atomic layer deposition, removing the plurality of photomask layers to form a masking structure comprising at least one of the first and second materials, and transferring a pattern formed by the masking structure to the substrate and removing the masking structure. The first material includes a silicon dioxide, silicon carbide, or carbon material, and the second material includes a metal oxide or metal nitride material.

Abstract: In an embodiment, a method includes forming a first fin and a second fin within an insulation material over a substrate, the first fin and the second fin includes different materials, the insulation material being interposed between the first fin and the second fin, the first fin having a first width and the second fin having a second width; forming a first capping layer over the first fin; and forming a second capping layer over the second fin, the first capping layer having a first thickness, the second capping layer having a second thickness different from the first thickness.

Abstract: The subject application relates to a server, terminal and non-transitory computer-readable medium. The server for handling streaming data for a live streaming, comprising one or a plurality of processors, wherein the one or plurality of processors execute a machine-readable instruction to perform: recording the streaming data for the live streaming; storing the streaming data as archive contents with first identifier; receiving interaction information during the live streaming; storing the interaction information as contexts with second identifier, transmitting the archive contents with first identifier to a first user terminal; and transmitting the contexts to the first user terminal according to the first identifier and the second identifier. According to the subject application, the archive contents may be more immersive and the user experience may be enhanced.

Abstract: Provided is a resistive random access memory (RRAM). The resistive random access memory includes a plurality of unit structures disposed on a substrate. Each of the unit structures includes a first electrode, and a first metal oxide layer. The first electrode is disposed on the substrate. The first metal oxide layer is disposed on the first electrode. In addition, the resistive random access memory includes a second electrode. The second electrode is disposed on the plurality of unit structures and connected to the plurality of unit structures.

Abstract: A display device includes first and second display modules and first and second turning pieces that include a first coupling piece, a first turning piece, a second turning piece, and a third turning piece, a second coupling piece and a guiding device. When the first and second display modules are switched between folding and unfolding, the first turning piece pivots relative to the first coupling piece and the second turning piece, and the third turning piece pivots relative to the second coupling piece and the second turning piece. When the display module is switched from folded to unfolded, the other side of the first display module relative to the side is pulled, the side of the first display module is guided by one end of the guiding device and slides to the other end, the first and second display modules are symmetrically unfolded with the side edge as the center.

Abstract: A lateral diffusion metal-oxide semiconductor (LDMOS) device includes a first gate structure and a second gate structure extending along a first direction on a substrate, a first source region extending along the first direction on one side of the first gate structure, a second source region extending along the first direction on one side of the second gate structure, a drain region extending along the first direction between the first gate structure and the second gate structure, a guard ring surrounding the first gate structure and the second gate structure, and a shallow trench isolation (STI) surrounding the guard ring.

Abstract: A semiconductor device includes a semiconductor channel. The semiconductor device includes a metal gate structure disposed over the semiconductor channel. The semiconductor device includes a gate electrode having a bottom surface contacting an upper surface of the metal gate structure. The gate electrode has its side portions extending from its top surface toward the semiconductor fin with a first depth and a central portion extending from its top surface toward the semiconductor fin with a second depth, the first depth being substantially greater than the second depth.

Abstract: The invention refers to a diffusion plate and a backlight module having the diffusion plate. The diffusion plate comprises a plate-body and a plurality of pyramid-like structures arranged on a surface of the plate-body. Each pyramid-like structure has a bottom surface, a first convex portion and a second convex portion. The first convex portion and the second convex portion have different vertex angles, and therefore the pyramid-like structure can also be called as “pyramid-like structure with multiple vertex angles”. The pyramid-like structures with multiple vertex angles can increase the light splitting points, which can improve the light splitting effect of the diffusion plate. The light source of a single light-emitting diode can be divided into eight point-light sources (light splitting points) or more, which is double the number of light splitting points compared with the traditional pyramid structure with single vertex, and thus can greatly improve the light diffusion effect.

Abstract: A method includes forming an interfacial layer over a substrate; forming a quasi-antiferroelectric (QAFE) layer over the interfacial layer, in which forming the QAFE layer comprises performing an atomic layer deposition (ALD) cycle, and the ALD cycle includes performing a first sub-cycle for X time(s), in which the first sub-cycle comprises providing a Zr-containing precursor; performing a second sub-cycle for Y time(s), in which the second sub-cycle comprises providing a Hf-containing precursor; and performing a third sub-cycle for Z time(s), in which the third sub-cycle comprises providing a Zr-containing precursor, and in which X+Z is at least three times Y; and forming a gate electrode over the QAFE layer.

Abstract: A coated metal alloy substrate with at least one chamfered edge, a process for producing a coating a metal alloy substrate, and an electronic device having a housing comprising a coated metal alloy substrate are described. The coated metal alloy substrate with at least one chamfered edge comprises a hydrophobic anti-fingerprint layer deposited on the metal alloy substrate, a passivation layer deposited on the at least one chamfered edge, and a water based paint layer deposited on the passivation layer.

Abstract: A method includes receiving a device design layout and a scribe line design layout surrounding the device design layout. The device design layout and the scribe line design layout are rotated in different directions. An optical proximity correction (OPC) process is performed on the rotated device design layout and the rotated scribe line design layout. A reticle includes the device design layout and the scribe line design layout is formed after performing the OPC process.

Abstract: A piezoelectric valve driver device is provided. A first driver is connected to a first side of a valve. A second driver is connected to a second side of the valve. A power charging circuit is coupled between an external power source and a second voltage. A charging and discharging current controller is connected to the first driver, the second driver and the power charging circuit, and is configured to control currents of the first driver, the second driver and the power charging circuit. When a driver circuit switches the valve from a closed state to an open state, the first driver provides a first voltage to the first side of the valve, and the second voltage that is outputted to the second side of the valve by the second driver is discharged to output a discharging current to the external power source through the power charging circuit.

Abstract: Electrostatic discharge (ESD) structures are provided. An ESD structure includes a semiconductor substrate, a first epitaxy region with a first type of conductivity over the semiconductor substrate, a second epitaxy region with a second type of conductivity over the semiconductor substrate, and a plurality of semiconductor layers. The semiconductor layers are stacked over the semiconductor substrate and between the first and second epitaxy regions. A first conductive feature is formed over the first epitaxy region and outside an oxide diffusion region. A second conductive feature is formed over the second epitaxy region and outside the oxide diffusion region. A third conductive feature is formed over the first epitaxy region and within the oxide diffusion region. A fourth conductive feature is formed over the second epitaxy region and within the oxide diffusion region. The oxide diffusion region is disposed between the first and second conductive features.

Abstract: An image processing method for a video processor, for generating an extrapolated frame according to a previous frame and a current frame, includes steps of: projecting a plurality of motion vectors (MVs) to the extrapolated frame subsequent to the current frame; determining whether a block of the extrapolated frame is projected by at least two of the MVs; selecting at least two candidate MVs from the MVs projected to the block when the block is projected by at least two of the MVs; calculating a blended MV which is a mixture of the at least two candidate MVs, and projecting the blended MV to the previous frame; obtaining a reference MV corresponding to position of the previous frame projected by the blended MV; and comparing the reference MV with the at least two candidate MVs, to select a final MV for the block from the at least two candidate MVs.

Abstract: The present disclosure describes a method for forming metallization layers that include a ruthenium metal liner and a cobalt metal fill. The method includes depositing a first dielectric on a substrate having a gate structure and source/drain (S/D) structures, forming an opening in the first dielectric to expose the S/D structures, and depositing a ruthenium metal on bottom and sidewall surfaces of the opening. The method further includes depositing a cobalt metal on the ruthenium metal to fill the opening, reflowing the cobalt metal, and planarizing the cobalt and ruthenium metals to form S/D conductive structures with a top surface coplanar with a top surface of the first dielectric.