Abstract: A semiconductor package structure including a circuit substrate, at least one chip, an encapsulant, a plurality of conductive connectors, a redistribution layer, and a plurality of conductive terminals is provided. The circuit substrate has a first surface and a second surface opposite to the first surface. The at least one chip has an active surface and a rear surface opposite to the active surface. The at least one chip is disposed on the circuit substrate with the rear surface. The encapsulant encapsulates the at least one chip. The plurality of conductive connectors surrounds the at least one chip. The redistribution layer is located on the encapsulant. The plurality of conductive terminals is located on the second surface. The at least one chip is electrically connected to the plurality of conductive terminals via the redistribution layer, the plurality of conductive connectors, and the circuit substrate. A manufacturing method of a semiconductor package structure is also provided.

Abstract: A lid opening component, a lid opening device, and a suction system are disclosed. The suction system includes the lid opening device and a suction assembly, wherein the lid opening device includes a positioning assembly and a lid opening assembly having the lid opening components, and the lid opening component includes a needle holder, a plurality of unpowered needles, and a drive part. The suction system identifies the locations of a container and its lids through the positioning assembly of the lid opening device, opens the container's lids by fitting the unpowered needles of the lid opening components in with the surfaces of the container's lids and rotating the lid opening components of the lid opening assembly, and by moving the suction assembly to the openings of the container, draws out the content in the container through the suction assembly.

Abstract: A chip package structure including a first chip, an encapsulant, a first redistribution layer, a second redistribution layer, a second chip, and a third chip is provided. The first chip has an active surface, a back side surface opposite to the active surface, a plurality of conductive vias, and a plurality of conductive connectors disposed on the back side surface. The encapsulant covers the active surface, the back side surface, and the conductive connectors. The encapsulant has a first encapsulating surface and a second encapsulating surface opposite to the first encapsulating surface. The first redistribution layer is disposed on the first encapsulating surface. The second redistribution layer is disposed on the second encapsulating surface. The second chip is disposed on the second redistribution layer. The third chip is disposed on the second redistribution layer. A manufacturing method of a chip package structure is also provided.

Abstract: A liquid withdrawal system includes a base, at least one motion-enhancing element, a plurality of grip elements and a clamp. The base has a load-carrying surface and a rotational axis. The rotational axis is perpendicular to the load-carrying surface. The base is rotatable relative to the rotational axis. The motion-enhancing element is disposed on the load-carrying surface. The clamp is disposed opposite the load-carrying surface. The base and clamp jointly define a receiving space. The receiving space is adapted to receive a liquid barrel. The grip elements are movably connected to the base and symmetrically positioned relative to the base.

Abstract: A package structure and a method of manufacturing the same are provided. The package structure includes a substrate, a redistribution layer (RDL) structure, a first die, an encapsulant and a plurality of conductive terminals. The RDL structure is disposed on and electrically connected to the substrate. A width of the RDL structure is less than a width of the substrate. The first die is disposed on the substrate and the RDL structure. The first connectors of the first die are electrically connected to the RDL structure. The second connectors of the first die are electrically connected to the substrate. A first pitch of two adjacent first connectors is less than a second pitch of two adjacent second connectors. The encapsulant is on the substrate to encapsulate the RDL structure and the first die. The conductive terminals are electrically connected to the first die through the substrate and the RDL structure.

Abstract: A chip package structure using silicon interposer as interconnection bridge lifts multi-dies above the fan-out molding package embedded with premade Si interposer interconnection bridge under the multi-die space. The interconnection bridge connects the multi-dies through fine pitch high I/O interconnection. A first RDL and a second RDL are further disposed on top side and bottom side of the fan-out molding package, further providing connection for the multi-dies to a substrate via the connection routing inside the fan-out molding package.

Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a first and a second active dies separately arranged, an insulating encapsulation at least laterally encapsulating the first and the second active dies, a redistribution layer disposed on the insulating encapsulation, the first and the second active dies, and a fine-pitched die disposed on the redistribution layer and extending over a gap between the first and the second active dies. The fine-pitched die has a function different from the first and the second active dies. A die connector of the fine-pitched die is connected to a conductive feature of the first active die through a first conductive pathway of the redistribution layer. A first connecting length of the first conductive pathway is substantially equal to a shortest distance between the die connector of the fine-pitched die and the conductive feature of the first active die.

Abstract: A package structure including a first chip, a second chip, a dielectric body, a third chip, an encapsulant, a first conductive terminal, and a circuit layer is provided. The dielectric body covers the first chip and the second chip. The third chip is disposed on the dielectric body such that a third active surface thereof faces a first active surface of the first chip or a second active surface of the second chip. The encapsulant covers the third chip. The first conductive terminal is disposed on the dielectric body and is opposite to the third chip. The circuit layer includes a first circuit portion and a second circuit portion. The first circuit portion penetrates the dielectric body. The first chip, the second chip, or the third chip is electrically connected to the first conductive terminal through the first circuit portion. The second circuit portion is embedded in the dielectric body.

Abstract: A package structure including a first circuit board, a second circuit board, an encapsulant, a plurality of conductive terminals, and a package device is provided. The first circuit board has a first top surface and a first bottom surface opposite to each other. The second circuit board has a second top surface and a second bottom surface opposite to each other. The encapsulant encapsulates the first and second circuit boards. The conductive terminals are disposed on the first or second bottom surface and electrically connected to the first or second circuit board. The package device is disposed on the first or second top surface and electrically connected to the first and second circuit boards. The package device includes a first chip, a second chip, a chip encapsulant, a circuit layer, and a plurality of conductive package terminals. A manufacturing method of a package structure is also provided.

Abstract: A package structure including a redistribution circuit structure, a first chip, a second chip, a first circuit board, a second circuit board, and a plurality of conductive terminals is provided. The redistribution circuit structure has a first connection surface and a second connection surface opposite to the first connection surface. The first chip and the second chip are disposed on the first connection surface and are electrically connected to the redistribution circuit structure. The first circuit board and the second circuit board are disposed on the second connection surface and are electrically connected to the redistribution circuit structure. The conductive terminals are disposed on the first circuit board or the second circuit board. The conductive terminals are electrically connected to the first circuit board or the second circuit board. A manufacturing method of a package structure is also provided.

Abstract: A semiconductor package structure, including a circuit substrate, at least two chips, an encapsulant, and a redistribution layer, is provided. The circuit substrate has a first surface and a second surface opposite to the first surface. The at least two chips are disposed on the first surface. Each of the at least two chips has an active surface facing the circuit substrate and includes multiple first conductive connectors and multiple second conductive connectors disposed on the active surface. A pitch of the first conductive connectors is less than a pitch of the second conductive connectors. The encapsulant encapsulates the at least two chips. The redistribution layer is located on the second surface. The first conductive connectors are electrically connected to the redistribution layer by the circuit substrate. The second conductive connectors are electrically connected to the circuit substrate. A manufacturing method of a semiconductor package structure is also provided.

Abstract: A package structure including a redistribution circuit structure, an insulator, a plurality of conductive connection pieces, a first chip, a second chip, an encapsulant, a third chip, and a plurality of conductive terminals is provided. The redistribution circuit structure has first and second connection surfaces opposite to each other. The insulator is embedded in and penetrates the redistribution circuit structure. The conductive connection pieces penetrate the insulator. The first and second chips are disposed on the first connection surface. The encapsulant is disposed on the redistribution circuit structure and at least laterally covers the first and second chips. The third chip is disposed on the second connection surface and electrically connected to the first and second chips through the conductive connection pieces. The conductive terminals are disposed on the second connection surface and electrically connected to the first chip or the second chip through the redistribution circuit structure.

Abstract: A packaging structure includes a bridge die, a through silicon via die, a first encapsulant, a first active die, a second active die, a second encapsulant, and a redistribution circuit structure. The first encapsulant covers the through silicon via die and the bridge die. The first active die is electrically connected to the bridge die and the through silicon via die. The second active die is electrically connected to the bridge die. The second encapsulant covers the first active die and the second active die. The redistribution circuit structure is electrically connected to the through silicon via die. The through silicon via die is disposed between the first active die and the redistribution circuit structure. A manufacturing method of a packaging structure is also provided.

Abstract: A package device and a manufacturing method thereof are provided. The manufacturing method of the package device includes providing a substrate and forming a redistribution layer on the substrate. The substrate has at least one device region and a non-device region. The redistribution layer includes at least one inspection structure and at least one wire structure. The wire structure is disposed in the device region, a part of the inspection structure and a part of the wire structure are formed of a same layer, and the inspection structure has a trench exposing the part of the inspection structure.

Abstract: The disclosure provides a package structure including a redistribution circuit structure, a first circuit board, a second circuit board, a first insulator, multiple conductive terminals, and a package. The redistribution circuit structure has a first connection surface and a second connection surface opposite to each other. The first circuit board and the second circuit board are disposed on the first connection surface and are connected electrically to the redistribution circuit structure. The first insulator is disposed on the first connection surface and covers the first circuit board and the second circuit board. The conductive terminals are connected electrically to and disposed on the first circuit board or the second circuit board. The package is disposed on the second connection surface and is connected electrically to the redistribution circuit structure. A manufacturing method of a package structure is also provided.

Abstract: A manufacturing method is applied to set a stackable chip package. The manufacturing method includes encapsulating a plurality of chips stacked with each other, disposing a lateral surface of the stacked chips having conductive elements onto a substrate, disassembling the substrate from the conductive elements when the stacked chips are encapsulated, and disposing a dielectric layer with openings on the stacked chips to align the openings with the conductive elements for ball mounting process.

Abstract: A package structure including at least one semiconductor chip, an insulating encapsulant, a conductive frame, a supporting frame, a conductive layer and a redistribution layer is provided. The at least one semiconductor chip has an active surface and a backside surface opposite to the active surface. The insulating encapsulant is encapsulating the at least one semiconductor chip. The conductive frame is surrounding the insulating encapsulant. The supporting frame is surrounding the conductive frame. The conductive layer is disposed on the backside surface of the semiconductor chip. The redistribution layer is disposed on and electrically connected to the active surface of the semiconductor chip.

Abstract: A semiconductor package structure including a sensor die, a substrate, a light blocking layer, a circuit layer, a dam structure and an underfill is provided. The sensor die has a sensing surface. The sensing surface includes an image sensing area and a plurality of conductive bumps. The substrate is disposed on the sensing surface. The light blocking layer is located between the substrate and the sensor die. The circuit layer is disposed on the light blocking layer. The sensor die is electrically connected to the circuit layer by the conductive bumps. The dam structure is disposed on the substrate and surrounds the image sensing area. Opposite ends of the dam structure directly contact the sensor die and the light blocking layer. The underfill is disposed between the dam structure and the conductive bumps.

Abstract: By using a photosensitive material coating or laminating on the substrate, an opening well structure with plurality of openings and pillars is formed by photolithography or mechanical processing to have patterns corresponding to the active sensor areas of the chip die so as to provide improved support on the substrate for the cover glass. The overall package structure is then reinforced without the risk of cracking the substrate.

Abstract: A package structure including a redistribution structure, a die, at least one connecting module, a first insulating encapsulant, a chip stack, and a second insulating encapsulant. The die is disposed on and electrically connected to the redistribution structure. The connecting module is disposed on the redistribution structure. The connecting module has a protection layer and a plurality of conductive bars. The conductive bars are embedded in the protection layer. The protection layer includes a plurality of openings corresponding to the conductive bars. The first insulating encapsulant encapsulates the die and the connecting module. The chip stack is disposed on the first insulating encapsulant and the die. The chip stack is electrically connected to the connecting module. The second insulating encapsulant encapsulates the chip stack.