Abstract: A semiconductor package structure including a circuit substrate, at least one chip, an encapsulant, a plurality of conductive connectors, a redistribution layer, and a plurality of conductive terminals is provided. The circuit substrate has a first surface and a second surface opposite to the first surface. The at least one chip has an active surface and a rear surface opposite to the active surface. The at least one chip is disposed on the circuit substrate with the rear surface. The encapsulant encapsulates the at least one chip. The plurality of conductive connectors surrounds the at least one chip. The redistribution layer is located on the encapsulant. The plurality of conductive terminals is located on the second surface. The at least one chip is electrically connected to the plurality of conductive terminals via the redistribution layer, the plurality of conductive connectors, and the circuit substrate. A manufacturing method of a semiconductor package structure is also provided.

Abstract: A chip package structure using silicon interposer as interconnection bridge lifts multi-dies above the fan-out molding package embedded with premade Si interposer interconnection bridge under the multi-die space. The interconnection bridge connects the multi-dies through fine pitch high I/O interconnection. A first RDL and a second RDL are further disposed on top side and bottom side of the fan-out molding package, further providing connection for the multi-dies to a substrate via the connection routing inside the fan-out molding package.

Abstract: An integrated antenna package structure including a circuit board, a chip, an encapsulant and an antenna is provided. The chip is disposed on and electrically connected to the circuit board. The encapsulant encapsulates the chip. The encapsulant has a first surface and a second surface, wherein the normal vector of the first surface is different from the normal vector of the second surface. The antenna is disposed on the first surface and the second surface of the encapsulant. A manufacturing method of an integrated antenna package structure is also provided.

Abstract: A quick connector assembly and a quick connector device are disclosed. The quick connector assembly includes a first base, a first fluid interface assembly and a valve assembly. The valve assembly regulates whether a fluid flows through the quick connector assembly or not, and thereby sealing the flow of the fluid at both sides of the quick connector assembly. The quick connector assembly and the quick connector device in an embodiment of the present disclosure can regulate the flow of the fluid effectively and provide better barriers to keep concurrent flows separated and isolated. Especially, the quick connector device can be used in slurry delivery system which has fluid being abrasive fluid or solid contained liquid.

Abstract: A fan-out semiconductor package and packaging method thereof are disclosed. In the packaging method, a photosensitive material is used to encapsulate multiple bare chips and multiple passive devices, so multiple metal pads of each bare chip and multiple metal terminals of each passive device are exposed out of the photosensitive material by a photolithography process. The exposed metal pads and the exposed metal terminals are directly and electrically connected to a redistribution layer. In the packaging method, the bare chips and the passive devices are located on the same side of the redistribution layer and encapsulated by the photosensitive material. In addition, in the packaging method, the bare chips are not processed by a wafer bump process and does not use the thinner passive devices with high cost. Therefore, a height of the fan-out semiconductor package of the present invention is decreased and a manufacturing cost is relatively reduced.

Abstract: A fan-out chip package assembly with fine pitch silicon through via uses one or more silicon interposers in the bottom package as interconnections between the top package and the substrate. The one or more partially distributed silicon interposers may be disposed in the same layer of the bottom semiconductor die according to the design requirement of the fan-out contact pads of the top package, allowing more design freedom of the top high level chips.

Abstract: A semiconductor package structure including a circuit substrate, a redistribution layer, and at least two dies is provided. The circuit substrate has a first surface and a second surface opposite the first surface. The redistribution layer is located on the first surface. The redistribution layer is electrically connected to the circuit substrate. The spacing of the opposing sidewalls of the redistribution layer is less than the spacing of the opposing sidewalls of the circuit substrate. The redistribution layer is directly in contact with the circuit substrate. At least two dies are disposed on the redistribution layer. Each of the at least two dies has an active surface facing the circuit substrate. One of the at least two dies is electrically connected to the other of the at least two dies by the redistribution layer. A manufacturing method of a semiconductor package structure is also provided.

Abstract: A package structure and a method of manufacturing the same are provided. The package structure includes a substrate, a redistribution layer (RDL) structure, a first die, an encapsulant and a plurality of conductive terminals. The RDL structure is disposed on and electrically connected to the substrate. A width of the RDL structure is less than a width of the substrate. The first die is disposed on the substrate and the RDL structure. The first connectors of the first die are electrically connected to the RDL structure. The second connectors of the first die are electrically connected to the substrate. A first pitch of two adjacent first connectors is less than a second pitch of two adjacent second connectors. The encapsulant is on the substrate to encapsulate the RDL structure and the first die. The conductive terminals are electrically connected to the first die through the substrate and the RDL structure.

Abstract: A stacked package structure has a metal casing, a stacked chipset, an encapsulation and a redistribution layer. The stacked chipset is adhered in the metal casing. The encapsulation is formed in the metal casing to encapsulate the stacked chip set, but a plurality of surfaces of the metal pads are exposed through the encapsulation. The redistribution layer is further formed on the encapsulation and electrically connects to the metal pads of the stacked chipset. Therefore, the stacked package structure includes the metal casing, so an efficiency of heat dissipation and structural strength are increased.

Abstract: A rotary bucket mixing device is disclosed. The rotary bucket mixing device includes a main body, a rotating disk assembly, a power gear assembly and a first idler assembly. The power gear assembly receives a power to drive the rotating disk assembly to rotate and thereby rotating a mixing bucket disposed on a supporting assembly of the rotating disk assembly and mixing the contents in the mixing bucket. The first idler assembly controls a rotational speed. The rotary bucket mixing device of the present disclosure provides a better support to the mixing bucket and therefore the safety during the mixing process is enhanced.

Abstract: An integrated antenna package structure including a circuit board, a chip, an encapsulant and an antenna is provided. The chip is disposed on the circuit board and electrically connected to the circuit board. The encapsulant encapsulates the chip. The antenna is embedded in the encapsulant. The antenna has a first outer surface, the encapsulant has a second outer surface, and the first outer surface is substantially coplanar with the second outer surface. A manufacturing method of an integrated antenna package structure is also provided.

Abstract: An integrated antenna package structure including a circuit board, a chip, an encapsulant and an antenna is provided. The chip is disposed on the circuit board and electrically connected to the circuit board. The encapsulant encapsulates the chip. The antenna is embedded in the encapsulant. The antenna has a first outer surface, the encapsulant has a second outer surface, and the first outer surface is substantially coplanar with the second outer surface. A manufacturing method of an integrated antenna package structure is also provided.

Abstract: An integrated antenna package structure including a circuit board, a chip, an encapsulant and an antenna is provided. The chip is disposed on and electrically connected to the circuit board. The encapsulant encapsulates the chip. The encapsulant has a first surface and a second surface, wherein the normal vector of the first surface is different from the normal vector of the second surface. The antenna is disposed on the first surface and the second surface of the encapsulant. A manufacturing method of an integrated antenna package structure is also provided.

Abstract: A manufacturing method of a chip package structure includes: dicing a wafer to separate chips formed thereon; mounting the chips on a carrier, wherein an active surface and pads of each chip are buried in an adhesive layer disposed on the carrier, and a top surface of the adhesive layer between the chips is bulged away from the carrier; forming an encapsulant to encapsulate the chips and cover the adhesive layer, wherein the encapsulant has a concave surface covering the top surface of the adhesive layer and a back surface opposite to the concave surface; removing the carrier and the adhesive layer; forming a first dielectric layer to cover the concave surface and the active surface; forming a patterned circuit layer on the first dielectric layer, to electrically connect to the pads through openings in the first dielectric layer; and forming a second dielectric layer on the patterned circuit layer.

Abstract: A semiconductor package including a die stack, an insulating encapsulation encapsulating the die stack, a first redistribution layer (RDL) and a second RDL disposed on two opposite sides of the insulating encapsulation, and a through insulating via disposed aside the die stack and extending through the insulating encapsulation to be electrically connected to the first RDL and the second RDL. The die stack includes a first die and a second die stacked upon one another and electrically connected to the first die. The second die includes a through semiconductor via disposed therein. One of the first die and the second die includes conductive features having different thicknesses. The second RDL is connected to the through semiconductor via of the second die. A manufacturing method of a semiconductor package is also provided.

Abstract: A package structure including a frame structure, a die, an encapsulant, a redistribution structure, and a passive component is provided. The frame structure has a cavity. The die is disposed in the cavity. The encapsulant fills the cavity to encapsulate the die. The redistribution structure is disposed on the encapsulant, the die, and the frame structure. The redistribution structure is electrically coupled to the die. The passive component is disposed on the frame structure and electrically coupled to the redistribution structure through the frame structure. A manufacturing method of a package structure is also provided. The frame structure may provide support, reduce warpage, dissipate heat from the die, act as a shield against electromagnetic interference, and/or provide electrical connection for grounding.

Abstract: A chip package structure including a first chip, an encapsulant, a first redistribution layer, a second redistribution layer, a second chip, and a third chip is provided. The first chip has an active surface, a back side surface opposite to the active surface, a plurality of conductive vias, and a plurality of conductive connectors disposed on the back side surface. The encapsulant covers the active surface, the back side surface, and the conductive connectors. The encapsulant has a first encapsulating surface and a second encapsulating surface opposite to the first encapsulating surface. The first redistribution layer is disposed on the first encapsulating surface. The second redistribution layer is disposed on the second encapsulating surface. The second chip is disposed on the second redistribution layer. The third chip is disposed on the second redistribution layer. A manufacturing method of a chip package structure is also provided.

Abstract: A semiconductor package including a semiconductor chip, a conductive element disposed aside the semiconductor chip, a conductive via disposed on and electrically connected to the conductive element, an insulating encapsulation, and a first circuit structure disposed on the semiconductor chip and the conductive via is provided. A height of the conductive element is less than a height of the semiconductor chip. The insulating encapsulation encapsulates the semiconductor chip, the conductive element, and the conductive via. The conductive via is located between the first circuit structure and the conductive element, and the semiconductor chip is electrically coupled to the conductive via through the first circuit structure.

Abstract: An integrated antenna package structure including a chip, a circuit layer, an encapsulant, a coupling end, an insulating layer, a conductive connector, a dielectric substrate, and an antenna is provided. The circuit layer is electrically connected to the chip. The encapsulant is disposed on the circuit layer and covers the chip. The coupling end is disposed on the encapsulant. The insulating layer covers the coupling end. The insulating layer is not externally exposed. The conductive connector penetrates the encapsulant. The coupling end is electrically connected to the circuit layer by the conductive connection. The dielectric substrate is disposed on the encapsulant and covers the coupling end. The antenna is disposed on the dielectric substrate. A manufacturing method of an integrated antenna package structure is also provided.

Abstract: An integrated antenna package structure including a chip package and an antenna device is provided. The antenna device is disposed on the chip package. The chip package includes a chip, an encapsulant, a circuit layer, and a conductive connector. The encapsulant at least directly covers the back side of the chip. The circuit layer is disposed on the encapsulant and electrically connected to the chip. The conductive connector penetrates the encapsulant and is electrically connected to the circuit layer. The antenna device includes a dielectric body, a coupling layer, and an antenna layer. The dielectric body has a first dielectric surface and a second dielectric surface opposite to the first dielectric surface. The coupling layer is disposed on the second dielectric surface of the dielectric body. The antenna layer is disposed on the first dielectric surface of the dielectric body. The antenna layer is electrically connected to the conductive connector.