Patents by Inventor Hung-Hsin Hsu

Hung-Hsin Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10796931
    Abstract: A manufacturing method of a package structure is described. The method includes at least the following steps. A carrier is provided. A semiconductor die and a sacrificial structure are disposed on the carrier. The semiconductor die is electrically connected to the bonding pads on the sacrificial structure through a plurality of conductive wires. As encapsulant is formed on the carrier to encapsulate the semiconductor die, the sacrificial structure and the conductive wires. The carrier is debonded, and at least a portion of the sacrificial structure is removed through a thinning process. A redistribution layer is formed on the semiconductor die and the encapsulant. The redistribution layer is electrically connected to the semiconductor die through the conductive wires.
    Type: Grant
    Filed: December 23, 2019
    Date of Patent: October 6, 2020
    Assignee: Powertech Technology Inc.
    Inventors: Han-Wen Lin, Hung-Hsin Hsu, Shang-Yu Chang Chien, Nan-Chun Lin
  • Patent number: 10788205
    Abstract: An atomizing system is provided to connect a liquid supply zone and a gas supply zone. In the atomizing system, a first pipeline is connected between the liquid supply zone and a first treatment tank, a second pipeline is connected between the first treatment tank and a second treatment tank, a third pipeline is connected between the gas supply zone and the second treatment tank. The end of each of the nozzles is connected to the other end of the third pipeline. The liquid supplied from the liquid supply zone is flowed into the second treatment tank through the second pipeline, the gas supplied from the gas supply zone is flowed into the second treatment tank through the nozzles, so that the liquid contacts the gas in the second treatment tank to produce the atomized liquid.
    Type: Grant
    Filed: July 3, 2018
    Date of Patent: September 29, 2020
    Assignee: ASIA IC MIC-PROCESS, INC.
    Inventor: Hung-Hsin Hsu
  • Publication number: 20200273803
    Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a first and a second active dies separately arranged, an insulating encapsulation at least laterally encapsulating the first and the second active dies, a redistribution layer disposed on the insulating encapsulation, the first and the second active dies, and a fine-pitched die disposed on the redistribution layer and extending over a gap between the first and the second active dies. The fine-pitched die has a function different from the first and the second active dies. A die connector of the fine-pitched die is connected to a conductive feature of the first active die through a first conductive pathway of the redistribution layer. A first connecting length of the first conductive pathway is substantially equal to a shortest distance between the die connector of the fine-pitched die and the conductive feature of the first active die.
    Type: Application
    Filed: July 17, 2019
    Publication date: August 27, 2020
    Applicant: Powertech Technology Inc.
    Inventors: Hung-Hsin Hsu, Nan-Chun Lin, Shang-Yu Chang Chien
  • Publication number: 20200273829
    Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes first dies, an insulating encapsulation laterally encapsulating the first dies, a second die disposed over the portion of the insulating encapsulation and at least partially overlapping the first dies, and a redistribution structure disposed on the insulating encapsulation and electrically connected to the first dies and the second die. A second active surface of the second die faces toward first active surfaces of the first dies. The redistribution structure includes a first conductive via disposed proximal to the first dies, and a second conductive via disposed proximal to the second die. The first and second conductive vias are electrically coupled and disposed in a region of the redistribution structure between the second die and one of the first dies. The first conductive via is staggered from the second conductive via by a lateral offset.
    Type: Application
    Filed: July 25, 2019
    Publication date: August 27, 2020
    Applicant: Powertech Technology Inc.
    Inventors: Hung-Hsin Hsu, Shang-Yu Chang Chien, Nan-Chun Lin
  • Publication number: 20200269200
    Abstract: A material mixing and supplying system is provided. The material mixing and supplying system includes a feeding module, at least three mixing and supplying barrels, a supply module, and a control unit, wherein the three mixing and supplying barrels are capable of mixing and supplying the mixed material. The supplying time of the mixed material is greater than a sum of the feeding time and the mixing time. A total operation number of the at least three mixing and supplying barrels is determined by a set amount of mixed material to be supplied by the material mixing and supplying system, and a total time to finish supplying the set amount of mixed material is determined by the total operation number.
    Type: Application
    Filed: February 18, 2020
    Publication date: August 27, 2020
    Inventors: HUNG-HSIN HSU, YAN-LAN CHIOU
  • Patent number: 10756065
    Abstract: A method of fabricating a package structure including at least the following steps is provided. A carrier is provided. A first package is formed on the carrier. The first package is formed by at least the following steps. A first redistribution layer is formed on the carrier, wherein the first redistribution layer has a first surface and a second surface opposite to the first surface. A semiconductor die is bonded on the first surface of the first redistribution layer. The semiconductor die is electrically connected to the first redistribution layer through a plurality of conductive wires. An insulating material is formed to encapsulate the semiconductor die and the plurality of conductive wires.
    Type: Grant
    Filed: January 14, 2020
    Date of Patent: August 25, 2020
    Assignee: Powertech Technology Inc.
    Inventors: Shang-Yu Chang Chien, Hung-Hsin Hsu, Nan-Chun Lin
  • Publication number: 20200203313
    Abstract: A stacked package structure has a metal casing, a stacked chipset, an encapsulation and a redistribution layer. The stacked chipset is adhered in the metal casing. The encapsulation is formed in the metal casing to encapsulate the stacked chip set, but a plurality of surfaces of the metal pads are exposed through the encapsulation. The redistribution layer is further formed on the encapsulation and electrically connects to the metal pads of the stacked chipset. Therefore, the stacked package structure includes the metal casing, so an efficiency of heat dissipation and structural strength are increased.
    Type: Application
    Filed: December 21, 2018
    Publication date: June 25, 2020
    Applicant: Powertech Technology Inc.
    Inventors: Ming-Chih Chen, Hung-Hsin Hsu, Yuan-Fu Lan, Hsien-Wen Hsu
  • Publication number: 20200152609
    Abstract: A method of fabricating a package structure including at least the following steps is provided. A carrier is provided. A first package is formed on the carrier. The first package is formed by at least the following steps. A first redistribution layer is formed on the carrier, wherein the first redistribution layer has a first surface and a second surface opposite to the first surface. A semiconductor die is bonded on the first surface of the first redistribution layer. The semiconductor die is electrically connected to the first redistribution layer through a plurality of conductive wires. An insulating material is formed to encapsulate the semiconductor die and the plurality of conductive wires.
    Type: Application
    Filed: January 14, 2020
    Publication date: May 14, 2020
    Applicant: Powertech Technology Inc.
    Inventors: Shang-Yu Chang Chien, Hung-Hsin Hsu, Nan-Chun Lin
  • Publication number: 20200126815
    Abstract: A manufacturing method of a package structure is described. The method includes at least the following steps. A carrier is provided. A semiconductor die and a sacrificial structure are disposed on the carrier. The semiconductor die is electrically connected to the bonding pads on the sacrificial structure through a plurality of conductive wires. As encapsulant is formed on the carrier to encapsulate the semiconductor die, the sacrificial structure and the conductive wires. The carrier is debonded, and at least a portion of the sacrificial structure is removed through a thinning process. A redistribution layer is formed on the semiconductor die and the encapsulant. The redistribution layer is electrically connected to the semiconductor die through the conductive wires.
    Type: Application
    Filed: December 23, 2019
    Publication date: April 23, 2020
    Applicant: Powertech Technology Inc.
    Inventors: Han-Wen Lin, Hung-Hsin Hsu, Shang-Yu Chang Chien, Nan-Chun Lin
  • Patent number: 10629554
    Abstract: A package structure includes a die, an encapsulant, a dam structure, and a redistribution structure. The die has an active surface and a rear surface opposite to the active surface. The encapsulant encapsulates sidewalls of the die. The encapsulant has a first surface and a second surface opposite to the first surface. The first surface is coplanar with the rear surface of the die. The second surface is located at a level height different from the active surface of the die. The dam structure is disposed on the active surface of the die. A top surface of the dam structure is substantially coplanar with the second surface of the encapsulant. The redistribution structure is over the encapsulant, the dam structure, and the die. The redistribution structure is electrically connected to the die.
    Type: Grant
    Filed: April 13, 2018
    Date of Patent: April 21, 2020
    Assignee: Powertech Technology Inc.
    Inventors: Nan-Chun Lin, Hung-Hsin Hsu
  • Patent number: 10629559
    Abstract: A package structure including a semiconductor die, an insulating encapsulant, a dielectric layer, and a redistribution layer is provided. The semiconductor die has an active surface, a back surface opposite to the active surface, and a plurality of conductive bumps disposed on the active surface. The insulating encapsulant is encapsulating the semiconductor die. The redistribution layer is disposed on the he insulating encapsulant and electrically connected to the plurality of conductive bumps. The dielectric layer is disposed between the insulating encapsulant and the redistribution layer, wherein the dielectric layer encapsulates at least a portion of each of the plurality of conductive bumps.
    Type: Grant
    Filed: September 19, 2018
    Date of Patent: April 21, 2020
    Assignee: Powertech Technology Inc.
    Inventors: Shang-Yu Chang Chien, Hung-Hsin Hsu, Nan-Chun Lin
  • Publication number: 20200091126
    Abstract: A semiconductor package including a plurality of first chips, a plurality of through silicon vias, a least one insulator, a first circuit structure and a first encapsulant is provided. The first chip electrically connected to the through silicon vias includes a sensing area on a first active surface, a first back surface and a plurality of through holes extending from the first back surface towards the first active surface. The insulator is disposed on the first active surfaces of the first chips. The first circuit structure disposed on the first back surfaces of the first chips and electrically connected to the through silicon vias. The first encapsulant, laterally encapsulating the first chips.
    Type: Application
    Filed: November 19, 2019
    Publication date: March 19, 2020
    Applicant: Powertech Technology Inc.
    Inventors: Nan-Chun Lin, Hung-Hsin Hsu, Shang-Yu Chang Chien, Wen-Hsiung Chang
  • Publication number: 20200091103
    Abstract: A package structure including a semiconductor die, an insulating encapsulant, a dielectric layer, and a redistribution layer is provided. The semiconductor die has an active surface, a back surface opposite to the active surface, and a plurality of conductive bumps disposed on the active surface. The insulating encapsulant is encapsulating the semiconductor die. The redistribution layer is disposed on the he insulating encapsulant and electrically connected to the plurality of conductive bumps. The dielectric layer is disposed between the insulating encapsulant and the redistribution layer, wherein the dielectric layer encapsulates at least a portion of each of the plurality of conductive bumps.
    Type: Application
    Filed: September 19, 2018
    Publication date: March 19, 2020
    Applicant: Powertech Technology Inc.
    Inventors: Shang-Yu Chang Chien, Hung-Hsin Hsu, Nan-Chun Lin
  • Patent number: 10593647
    Abstract: A package structure including first and second packages is provided. The first package includes a semiconductor die, an insulating encapsulant, a first redistribution layer, a second redistribution layer, and a plurality of conductive wire segments. The semiconductor die has an active surface and a back surface. The insulating encapsulant encapsulates the semiconductor die. The first redistribution layer is disposed on the back surface of the semiconductor die and a bottom surface of the insulating encapsulant. The first redistribution layer has a first surface and a second surface opposite to the first surface. The second redistribution layer is disposed on the active surface of the semiconductor die. The plurality of conductive wire segments electrically connects the semiconductor die to the second redistribution layer and the first redistribution layer to the second redistribution layer. The second package is stacked on the second surface of the first redistribution layer over the first package.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: March 17, 2020
    Assignee: Powertech Technology Inc.
    Inventors: Shang-Yu Chang Chien, Hung-Hsin Hsu, Nan-Chun Lin
  • Publication number: 20200075510
    Abstract: A semiconductor package including a semiconductor die, an insulating encapsulant, a passive component, such as a thin film capacitor, and a redistribution structure is provided. The semiconductor die includes an active surface and a plurality of conductive pads disposed on the active surface. The insulating encapsulant encapsulates the semiconductor die and exposes the active surface of the semiconductor die. The passive component is disposed on the active surface of the semiconductor die. The redistribution structure is disposed on the active surface of the semiconductor die electrically connected to the conductive pads of the semiconductor die and the passive component. A manufacturing method of a semiconductor package is also provided.
    Type: Application
    Filed: August 30, 2018
    Publication date: March 5, 2020
    Applicant: Powertech Technology Inc.
    Inventors: Shang-Yu Chang Chien, Hung-Hsin Hsu, Nan-Chun Lin
  • Publication number: 20200035614
    Abstract: A package structure including a frame structure, a die, an encapsulant, and a redistribution structure is provided. The frame structure has a cavity. The die is disposed in the cavity. The die has an active surface, a rear surface opposite to the active surface, a plurality of lateral sides connecting the active surface and the rear surface, and a plurality of connection pads disposed on the active surface. The encapsulant encapsulates at least a portion of the frame structure and lateral sides of the die. The redistribution structure is disposed on the encapsulant and the active surface of the die. The connection pads are directly in contact with the redistribution structure.
    Type: Application
    Filed: July 30, 2018
    Publication date: January 30, 2020
    Applicant: Powertech Technology Inc.
    Inventors: Nan-Chun Lin, Hung-Hsin Hsu
  • Publication number: 20200006290
    Abstract: A package structure including first and second packages is provided. The first package includes a semiconductor die, an insulating encapsulant, a first redistribution layer, a second redistribution layer, and a plurality of conductive wire segments. The semiconductor die has an active surface and a back surface. The insulating encapsulant encapsulates the semiconductor die. The first redistribution layer is disposed on the back surface of the semiconductor die and a bottom surface of the insulating encapsulant. The first redistribution layer has a first surface and a second surface opposite to the first surface. The second redistribution layer is disposed on the active surface of the semiconductor die. The plurality of conductive wire segments electrically connects the semiconductor die to the second redistribution layer and the first redistribution layer to the second redistribution layer. The second package is stacked on the second surface of the first redistribution layer over the first package.
    Type: Application
    Filed: June 27, 2018
    Publication date: January 2, 2020
    Applicant: Powertech Technology Inc.
    Inventors: Shang-Yu Chang Chien, Hung-Hsin Hsu, Nan-Chun Lin
  • Patent number: 10522512
    Abstract: A semiconductor package including an ultra-thin redistribution structure, a semiconductor die, a first insulating encapsulant, a semiconductor chip stack, and a second insulating encapsulant is provided. The semiconductor die is disposed on and electrically coupled to the ultra-thin redistribution structure. The first insulating encapsulant is disposed on the ultra-thin redistribution structure and encapsulates the semiconductor die. The semiconductor chip stack is disposed on the first insulating encapsulant and electrically coupled to the ultra-thin redistribution structure. The second insulating encapsulant is disposed on the ultra-thin redistribution structure and encapsulates the semiconductor chip stack and the first insulating encapsulant. A manufacturing method of a semiconductor package is also provided.
    Type: Grant
    Filed: May 2, 2018
    Date of Patent: December 31, 2019
    Assignee: Powertech Technology Inc.
    Inventors: Shang-Yu Chang Chien, Hung-Hsin Hsu, Nan-Chun Lin
  • Publication number: 20190393200
    Abstract: A package structure includes a first redistribution structure, a die, a plurality of conductive sheets, a plurality of conductive balls, and a first encapsulant. The first redistribution structure has a first surface and a second surface opposite to the first surface. The die has a plurality of connection pads electrically connected to the first surface of the first redistribution structure. The conductive sheets are electrically connected to the first surface of the first redistribution structure. The conductive balls are correspondingly disposed on the conductive sheets and are electrically coupled to the first surface of the first redistribution structure through the conductive sheets. The first encapsulant encapsulates the die, the conductive sheets, and the conductive balls. The first encapsulant exposes at least a portion of each conductive ball.
    Type: Application
    Filed: June 25, 2018
    Publication date: December 26, 2019
    Applicant: Powertech Technology Inc.
    Inventors: Shang-Yu Chang Chien, Hung-Hsin Hsu, Nan-Chun Lin
  • Patent number: 10512890
    Abstract: A mixing apparatus includes a first and a second feeding tube, a first and a second atomizing/refining dose control device, and a reaction chamber. The first and second feeding tubes are arranged in a multi-sleeves manner. The first and second atomizing/refining dose control devices are respectively disposed on terminal ends of the first and second feeding tubes. The reaction chamber accommodates the first and second feeding tubes and the first and second atomizing/refining dose control devices and has a liquid dose mixing wall. The first and second feeding tubes respectively receive a first and a second liquid dose. The first and second atomizing/refining dose control devices respectively atomize or refine the first and second liquid doses and spray the atomized or refined first and second liquid doses on a surface of the liquid dose mixing wall, so as to mix the first and second liquid doses.
    Type: Grant
    Filed: April 23, 2019
    Date of Patent: December 24, 2019
    Assignee: Asia IC Mic-Process, Inc.
    Inventors: Hung-Hsin Hsu, Yan-Lan Chiou