Abstract: An integrated circuit device includes a substrate having a first portion in a first device region and a second portion in a second device region. A first semiconductor strip is in the first device region. A dielectric liner has an edge contacting a sidewall of the first semiconductor strip, wherein the dielectric liner is configured to apply a compressive stress or a tensile stress to the first semiconductor strip. A Shallow Trench Isolation (STI) region is over the dielectric liner, wherein a sidewall and a bottom surface of the STI region is in contact with a sidewall and a top surface of the dielectric liner.

Abstract: An air adjusting device includes a casing, a hood, a first airflow generating unit, a tunnel and an air conditioning module. The hood has a wind inlet. The first airflow generating unit is connected to the hood. The tunnel is connected to the first airflow generating unit, wherein the tunnel has a wind outlet. The hood, the first airflow generating unit and the tunnel form an airflow passage. The airflow passage is isolated from an internal space of the casing. At least one part of the air conditioning module is disposed at the wind inlet. The first airflow generating unit draws a first ambient air into the airflow passage from the wind inlet. A temperature of the first ambient air is adjusted by the air conditioning module and discharged from the wind outlet through the airflow passage.

Abstract: Battery packs according to some embodiments of the present technology may include a first end beam and a second end beam. The battery packs may include a first side beam and a second side beam each extending between the first end beam and the second end beam. The battery packs may include a base. The first end beam, the second end beam, the first side beam, the second side beam, and the base may be welded along each interface between each component. The battery packs may include a plurality of battery cells disposed between the first side beam and the second side beam. Each battery cell of the plurality of battery cells may be separated from an adjacent battery cell by an interface material. The battery packs may include a lid coupled with a surface of each battery cell of the plurality of battery cells facing the lid.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate and a fin structure over the substrate. The fin structure has a channel height. The semiconductor device structure also includes a stack of nanostructures over the substrate. The channel height is greater than a lateral distance between the fin structure and the stack of the nanostructures. The semiconductor device structure further includes a metal gate stack over the nanostructures, and the nanostructures are separated from each other by portions of the metal gate stack. In addition, the semiconductor device structure includes a dielectric layer surrounding the metal gate stack, the nanostructures, and the fin structure.

Abstract: An image processing apparatus for evaluating cardiac images and a ventricular status identification method are provided. In the method, a region of interest (ROI) is determined from multiple target images, a variation in grayscale values of multiple pixels in the ROIs of each target image is determined, and one or more representative images are obtained according to the variation in the grayscale values. The target image is related to the pixels within an endocardial contour of a left ventricle. A boundary of the ROI is approximately located at two sides of a bottom of the endocardial contour. The ROI corresponds to a mitral valve. The variation in the grayscale values is related to a motion of the mitral valve. The representative image is for evaluating a status of the left ventricle.

Abstract: Provided are a memory cell and a method of forming the same. The memory cell includes a first dielectric pattern, a second dielectric pattern, a first bottom electrode, a first storage pattern, and a first top electrode. The first bottom electrode is disposed between the first dielectric pattern and the second dielectric pattern, and the first bottom electrode interfaces a first sidewall of the first dielectric pattern and a sidewall of the second dielectric pattern. The first storage pattern is disposed on the first dielectric pattern, the second dielectric pattern and the first bottom electrode, wherein the first storage pattern is electrically connected to the first bottom electrode. The first storage pattern is between the first bottom electrode and the first top electrode. A semiconductor die including a memory array is also provided.

Abstract: A method of manufacturing a semiconductor device includes forming a photoresist layer over a substrate. A first precursor and a second precursor are combined. The first precursor is an organometallic having a formula: MaRbXc, where M is one or more of Sn, Bi, Sb, In, and Te, R is one or more of a C7-C11 aralkyl group, a C3-C10 cycloalkyl group, a C2-C10 alkoxy group, and a C2-C10 alkylamino group, X is one or more of a halogen, a sulfonate group, and an alkylamino group, and 1?a?2, b?1, c?1, and b+c?4, and the second precursor is one or more of water, an amine, a borane, and a phosphine. The photoresist layer is selectively exposed to actinic radiation to form a latent pattern. The latent pattern is developed by applying a developer to the selectively exposed photoresist layer.

Abstract: An etch stop layer is formed over a semiconductor fin and gate stack. The etch stop layer is formed utilizing a series of pulses of precursor materials. A first pulse introduces a first precursor material to the semiconductor fin and gate stack. A second pulse introduces a second precursor material, which is turned into a plasma and then directed towards the semiconductor fin and gate stack in an anisotropic deposition process. As such, a thickness of the etch stop layer along a bottom surface is larger than a thickness of the etch stop layer along sidewalls.

Abstract: The present invention provides a chemical sensor comprising a substrate, a first colorimetric sensor array exposed and arranged in a first accommodating space of the substrate and a second colorimetric sensor array arranged in a second accommodating space of the substrate. The second accommodating space is covered with an isolating layer to isolates liquid molecules but allows gas molecules to pass through. The first colorimetric sensor array changes from a first initial color to a first indicating color according to a volatile part and a non-volatile part of an analyte, and the second colorimetric sensor array changes from a second initial color to a second indicating color according to the volatile part of the analyte, so that information of the volatile part and the non-volatile part of the analyte can be obtained simultaneously.

Abstract: A process is provided to fabricate a finFET device having a semiconductor layer of a two-dimensional “2D” semiconductor material. The semiconductor layer of the 2D semiconductor material is a thin film layer formed over a dielectric fin-shaped structure. The 2D semiconductor layer extends over at least three surfaces of the dielectric fin structure, e.g., the upper surface and two sidewall surfaces. A vertical protrusion metal structure, referred to as “metal fin structure”, is formed about an edge of the dielectric fin structure and is used as a seed to grow the 2D semiconductor material.

Abstract: The disclosure provides an eye state assessment method and an electronic device. The method includes: obtaining an optic disc image area from a first fundus photography and generating multiple optic cup-to-disc ratio assessment results by multiple first models based on the optic disc image area; obtaining a first assessment result of an eye based on the optic cup-to-disc ratio assessment results; performing multiple data augmentation operations on the first fundus photography to generate multiple second fundus photographies; generating multiple retinal nerve fiber layer (RNFL) defect assessment results by multiple second models based on the second fundus photographies; obtaining a second assessment result of the eye based on the RNFL defect assessment results; and obtaining an optic nerve assessment result of the eye based on the first assessment result and the second assessment result.

Abstract: In a method of manufacturing a semiconductor device, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed over a bottom fin structure. A sacrificial gate structure having sidewall spacers is formed over the fin structure. A source/drain region of the fin structure, which is not covered by the sacrificial gate structure, is removed. The second semiconductor layers are laterally recessed. Dielectric inner spacers are formed on lateral ends of the recessed second semiconductor layers. The first semiconductor layers are laterally recessed. A source/drain epitaxial layer is formed to contact lateral ends of the recessed first semiconductor layer. The second semiconductor layers are removed thereby releasing the first semiconductor layers in a channel region. A gate structure is formed around the first semiconductor layers.

Abstract: A method and a system for establishing a light source information prediction model are provided. A plurality of training images are captured for a target object. A white object is attached on the target object. True light source information of the training images is obtained according to a color of the white object in each of the training images. A neural network model is trained according to the training images and the true light source information, and a plurality of pieces of predicted light source information is generated according to the neural network model during the training. A learning rate for training the neural network model is adaptively adjusted based on the predicted light source information.

Abstract: A method includes forming a first source/drain region and a second source/drain region in a semiconductor fin; depositing a first dielectric layer over the first source/drain region and the second source/drain region; etching an opening through the first dielectric layer, wherein etching the opening comprises etching the first dielectric layer; forming first sidewall spacers on sidewalls of the opening; and forming a gate stack in the opening, wherein the gate stack is disposed between the first sidewall spacers.

Abstract: A method of forming a semiconductor device includes etching a substrate to form two first trenches separated by a fin; filling the two first trenches with an isolation layer; and depositing a dielectric layer over the fin and the isolation layer. The method further includes forming a second trench in the dielectric layer over a channel region of the semiconductor device, the second trench exposing the isolation layer. The method further includes etching the isolation layer through the second trench to expose an upper portion of the fin in the channel region of the semiconductor device, and forming a dummy gate in the second trench over the isolation layer and engaging the upper portion of the fin.

Abstract: A metal structure includes a patterned molybdenum tantalum oxide layer and a patterned metal layer. The patterned molybdenum tantalum oxide layer is disposed on a first substrate, in which the patterned molybdenum tantalum oxide layer includes about 2 to 12 atomic percent of tantalum. Both of an atomic percent of molybdenum and an atomic percent of oxygen of the patterned molybdenum tantalum oxide layer are greater than the atomic percent of tantalum of the patterned molybdenum tantalum oxide layer. The patterned metal layer is disposed on the patterned molybdenum tantalum oxide layer.

Abstract: A free-standing faucet which includes a valve assembly, a spout, an inlet tube set, and a free-standing casing tube, a spray holder, and a spray is revealed. The valve assembly consists of a housing, a mixing valve, and a diverter, and a handle. The housing is composed of a mixing valve chamber in which the mixing valve is mounted, a pipe joint connected to the inlet tube set, a connection portion formed on one side of the pipe joint close to the mixing valve chamber, a first cold water channel, and a first hot water channel. The first hot and cold water channels are formed inside the pipe joint and communicating with the connection portion and the inlet tube set. An adapter is connected to the connection portion and having second cold and hot water channels. Thereby the mixing valve can be assembled and positioned easily, securely and accurately.

Abstract: A method may include forming a first silicon nitride layer in an opening of the semiconductor device and on a top surface of the semiconductor device, wherein the semiconductor device includes an epitaxial source/drain and a metal gate. The method may include forming a second silicon nitride layer on the first silicon nitride layer, as a sacrificial layer, and removing the second silicon nitride layer from sidewalls of the first silicon nitride layer formed in the opening. The method may include removing the second silicon nitride layer and the first silicon nitride layer formed at a bottom of the opening, and depositing a metal layer in the opening to form a metal drain in the opening of the semiconductor device.

Abstract: In an embodiment, a method includes: forming a differential contact etch stop layer (CESL) having a first portion over a source/drain region and a second portion along a gate stack, the source/drain region being in a substrate, the gate stack being over the substrate proximate the source/drain region, a first thickness of the first portion being greater than a second thickness of the second portion; depositing a first interlayer dielectric (ILD) over the differential CESL; forming a source/drain contact opening in the first ILD; forming a contact spacer along sidewalls of the source/drain contact opening; after forming the contact spacer, extending the source/drain contact opening through the differential CESL; and forming a first source/drain contact in the extended source/drain contact opening, the first source/drain contact physically and electrically coupling the source/drain region, the contact spacer physically separating the first source/drain contact from the first ILD.

Abstract: A structure and a formation method of hybrid semiconductor devices are provided. The structure includes a substrate and a fin structure over the substrate. The fin structure has a channel height. The structure also includes a stack of nanostructures over the substrate. The channel height is greater than a lateral distance between the fin structure and the stack of the nanostructures. The structure further includes a gate stack over the nanostructures. The nanostructures are separated from each other by portions of the gate stack.