Abstract: A backlight module includes a light guide plate, a light source, multiple first optical microstructures, and multiple second optical microstructures. The first optical microstructures and the second optical microstructures are disposed on the bottom surface of the light guide plate. Each of the first optical microstructures has a first light receiving surface facing the light source. Each of the second optical microstructures has a second light receiving surface facing the light source. A first angle is included between the first light receiving surface and the bottom surface. A second angle is included between the second light receiving surface and the bottom surface. The second angle is different from the first angle. A display apparatus adopting the backlight module is also provided.

Abstract: A semiconductor high-voltage device includes a semiconductor substrate; a high-voltage well in the semiconductor substrate; a drift region in the high-voltage well; a recessed channel region adjacent to the drift region; a heavily doped drain region in the drift region and spaced apart from the recessed channel; an isolation structure between the recessed channel region and the heavily doped drain region in the drift region; a buried gate dielectric layer on the recessed channel region, wherein the top surface of the buried gate dielectric layer is lower than the top surface of the heavily doped drain region; and a gate on the buried gate dielectric layer.

Abstract: An image processing apparatus for evaluating cardiac images and a ventricular status identification method are provided. In the method, a region of interest (ROI) is determined from multiple target images, a variation in grayscale values of multiple pixels in the ROIs of each target image is determined, and one or more representative images are obtained according to the variation in the grayscale values. The target image is related to the pixels within an endocardial contour of a left ventricle. A boundary of the ROI is approximately located at two sides of a bottom of the endocardial contour. The ROI corresponds to a mitral valve. The variation in the grayscale values is related to a motion of the mitral valve. The representative image is for evaluating a status of the left ventricle.

Abstract: A semiconductor device includes a semiconductor substrate, a gate structure, a first drift region, a first source/drain region, and a gate oxide layer. The gate structure and the gate oxide layer are disposed on the semiconductor substrate. The first drift region is disposed in the semiconductor substrate. The first source/drain region is disposed in the first drift region. At least a part of a first portion of the gate oxide layer is disposed between the gate structure and the semiconductor substrate in a vertical direction. A second portion of the gate oxide layer is disposed between the first portion and the first source/drain region in a horizontal direction. The second portion includes a bottom extending downwards and a first concave top surface located above the bottom. A part of the first drift region is located under the first portion and the second portion of the gate oxide layer.

Abstract: An integrated circuit device includes a first bit line structure that has a horizontal portion and a vertical portion in which an upper surface of the vertical portion is exposed for making electrical contact with a contact that, in turn, is in electrical contact with a metal pattern through which operating voltages may be applied to the bit line structure.

Abstract: A method according to the present disclosure includes forming a fin-shaped structure protruding from a substrate, forming a gate structure intersecting the fin-shaped structure, forming a gate spacer on a sidewall of the gate structure, and forming a conductive feature above the fin-shaped structure. The gate spacer is laterally between the gate structure and the conductive feature. The method also includes depositing a dielectric layer over the gate structure and the conductive feature, performing an etching process, thereby forming an opening through the dielectric layer and exposing top surfaces of the conductive feature and the gate structure, recessing the gate spacers through the opening, thereby exposing the sidewall of the gate structure, and forming a contact feature in the opening, wherein the contact feature is in contact with the conductive feature and has a bottom portion protruding downward to be in contact with the sidewall of the gate structure.

Abstract: An etch stop layer is formed over a semiconductor fin and gate stack. The etch stop layer is formed utilizing a series of pulses of precursor materials. A first pulse introduces a first precursor material to the semiconductor fin and gate stack. A second pulse introduces a second precursor material, which is turned into a plasma and then directed towards the semiconductor fin and gate stack in an anisotropic deposition process. As such, a thickness of the etch stop layer along a bottom surface is larger than a thickness of the etch stop layer along sidewalls.

Abstract: A high voltage semiconductor device includes a semiconductor substrate, an isolation structure, a gate oxide layer, and a gate structure. The semiconductor substrate includes a channel region, and at least a part of the isolation structure is disposed in the semiconductor substrate and surrounds the channel region. The gate oxide layer is disposed on the semiconductor substrate, and the gate oxide layer includes a first portion and a second portion. The second portion is disposed at two opposite sides of the first portion in a horizontal direction, and a thickness of the first portion is greater than a thickness of the second portion. The gate structure is disposed on the gate oxide layer and the isolation structure.

Abstract: A method of forming a semiconductor device includes forming a dummy gate structure across a fin protruding from a substrate, forming gate spacers on opposite sidewalls of the dummy gate structure, forming source/drain epitaxial structures on opposite sides of the dummy gate structure, forming a first interlayer dielectric (ILD) layer on the source/drain epitaxial structures and outer sidewalls of the gate spacers, replacing the dummy gate structure with a replacement gate structure, etching back the replacement gate structure to form a recess between the gate spacers, performing a first non-conformal deposition process to fill the recess with a first gate cap material, and planarizing the first gate cap material to remove a portion of the first gate cap material outside the recess.

Abstract: A semiconductor device includes a semiconductor substrate, a trench, and a gate structure. The trench is disposed in the semiconductor substrate. The gate structure is disposed on the semiconductor substrate. The gate structure includes a gate electrode, a first gate oxide layer, and a second gate oxide layer. A first portion of the gate electrode is disposed in the trench, and a second portion of the gate electrode is disposed outside the trench. The first gate oxide layer is disposed between the gate electrode and the semiconductor substrate. At least a portion of the first gate oxide layer is disposed in the trench. The second gate oxide layer is disposed between the second portion of the gate electrode and the semiconductor substrate in a vertical direction. A thickness of the second gate oxide layer is greater than a thickness of the first gate oxide layer.

Abstract: A method includes bonding a first wafer to a second wafer, performing a trimming process on the first wafer, and depositing a sidewall protection layer contacting a sidewall of the first wafer. The depositing the sidewall protection layer includes depositing a high-density material in contact with the sidewall of the first wafer. The sidewall protection layer has a density higher than a density of silicon oxide. The method further includes removing a horizontal portion of the sidewall protection layer that overlaps the first wafer, and forming an interconnect structure over the first wafer. The interconnect structure is electrically connected to integrated circuit devices in the first wafer.

Abstract: Methods and system for embedding digital watermark information into textual data arranged in a table of cells are provided. A first subset of cells are selected and for each primary cell key and cell partition number are determined. A portion of a digital watermark ID code is embedded at an embedding position determined based on the partition number. Methods and systems for extracting digital watermark information from the textual data are also provided. A cell is fetched from the table and the presence of portion of the digital watermark ID code is determined. A primary cell key and cell partition number are determined. A portion of the digital watermark ID code is extracted at the embedding position within the cell, the embedding position determined based on the cell partition number. The digital watermarking systems and methods provide tracking for unauthorized copying of the data while modifying only a subset of the data.

Abstract: A process is provided to fabricate a finFET device having a semiconductor layer of a two-dimensional “2D” semiconductor material. The semiconductor layer of the 2D semiconductor material is a thin film layer formed over a dielectric fin-shaped structure. The 2D semiconductor layer extends over at least three surfaces of the dielectric fin structure, e.g., the upper surface and two sidewall surfaces. A vertical protrusion metal structure, referred to as “metal fin structure”, is formed about an edge of the dielectric fin structure and is used as a seed to grow the 2D semiconductor material.

Abstract: A resistive memory device includes a bottom electrode, a switching layer including a first horizontal portion, a second horizontal portion over an upper surface of the bottom electrode, and a first vertical portion over a side surface of the bottom electrode, a top electrode including a first horizontal portion over the first horizontal portion of the switching layer, a second horizontal portion over the second horizontal portion of the switching layer, and a first vertical portion over the first vertical portion of the switching layer, and a conductive via contacting the first horizontal portion, the second horizontal portion and the first vertical portion of the top electrode. By providing a switching layer and a top electrode which conform to a non-planar profile of the bottom electrode, charge crowding and a localized increase in electric field may facilitate resistance-state switching and provide a reduced operating voltage.

Abstract: Photoresists and methods of forming and using the same are disclosed. In an embodiment, a method includes spin-on coating a first hard mask layer over a target layer; depositing a photoresist layer over the first hard mask layer using chemical vapor deposition or atomic layer deposition, the photoresist layer being deposited using one or more organometallic precursors; heating the photoresist layer to cause cross-linking between the one or more organometallic precursors; exposing the photoresist layer to patterned energy; heating the photoresist layer to cause de-crosslinking in the photoresist layer forming a de-crosslinked portion of the photoresist layer; and removing the de-crosslinked portion of the photoresist layer.

Abstract: Transistor structures and methods of forming transistor structures are provided. The transistor structures include alternating layers of a first epitaxial material and a second epitaxial material. In some embodiments, one of the first epitaxial material and the second epitaxial material may be removed for one of an n-type or p-type transistor. A bottommost layer of the first epitaxial material and the second epitaxial material may be be removed, and sidewalls of one of the first epitaxial material and the second epitaxial material may be indented or recessed.

Abstract: The invention provides a semiconductor structure, the semiconductor structure includes a substrate, two shallow trench isolation structures are located in the substrate, a first region, a second region and a third region are defined between the two shallow trench isolation structures, the second region is located between the first region and the third region. Two thick oxide layers are respectively located in the first region and the third region and directly contact the two shallow trench isolation structures respectively, and a thin oxide layer is located in the second region, the thickness of the thick oxide layer in the first region is greater than that of the thin oxide layer in the second region.

Abstract: A device for obtaining a newly generated oxygen from an atmospheric environment is disclosed. The device includes a container having an inlet and an outlet, a cathode accommodated in the container and being in contact with an environmental oxygen in the atmospheric environment, an anode accommodated in the container and disposed at a position opposite to the cathode, an electrolyte accommodated in the container and immersing therein the cathode and the anode, a moisture removal unit disposed at the outlet having an outlet position, and a gas permeable element disposed at the outlet, wherein the cathode is disposed at the inlet, and the gas permeable element is disposed at a position closer to the outlet position than the moisture removal unit.

Abstract: A perovskite optical element includes a light guiding unit and a luminescent layer. The light guiding unit is configured to conduct light and serves as a resonant cavity. The luminescent layer is a thin film made of perovskite material and clads the light guiding unit. The luminescent layer is configured to be excited by an excitation module to emit light. The light is conducted and output by the light guiding unit. A manufacturing method of a perovskite optical element includes preparing a dip coating solution; dipping a single crystal optical fiber in the dip coating solution for one hour, removing the single crystal optical fiber out of the dip coating solution, and drying the single crystal optical fiber; and placing the single crystal optical fiber into a tube furnace, heating the crystal optical fiber, and introducing synthetic molecules into the tube furnace.

Abstract: The present invention relates to the treatment of IgE mediated diseases using an anti-IgE antibody. In particular, the anti-IgE antibody is a multifunctional antibody against IgE, which neutralizes IgE and inhibits IgE synthesis. Specifically, the treatment of the present invention is effective in providing a rapid and/or sustained suppression of disease symptoms.