Abstract: A method is provided. The method includes steps as follows. EUV light is generated. A collector is used to gather the EUV light onto a first optical reflector. The first optical reflector is used to reflect the EUV light to a reticle, so as to impart the EUV light with a pattern. A second optical reflector is used to reflect the EUV light with the pattern onto a wafer. The first optical reflector is rotated.

Abstract: A method of lithography includes obtaining a profile of a single field of a substrate that having a photoresist layer thereon, in which the profile includes a first feature and a second feature having different heights. A depth of focus distribution map is generated according to the profile. A project lens is tuned based on the generated depth of focus distribution map, such that the project lens provides a first focus length in a first project pixel of the project lens and a second focus length in a second project pixel of the project lens, wherein the first focus length and the second focus lengths. The single field of the substrate is exposed by using the tuned project lens.

Abstract: The present invention provides a protection circuit and related operation control method to enable the PFM circuit when the operating duration of the PFM circuit is not greater than a first threshold, and disables the PFM circuit when a rest duration of the PFM circuit is not greater than a second threshold. The present invention further provides a protection circuit and related operation control method to avoid starting excessive vertical scanning operations within one frame scanning period by masking one of the gate scanning start signal STV, the gate clock signal CKV and the gate discharge signal OEV. The present invention further provides a protection circuit and related operation control method to disable the gate scanning start signal STV when the number of clock cycles is not equal to a target number of clock cycles, which protects the gate driver from overload.

Abstract: A scanner includes a light source configured to apply a light to a backside of a wafer. The light is reflected from the backside of the wafer. A first mirror is configured to receive the light from the backside of the wafer and reflect the light. A sensor is configured to receive the light from the first mirror and generate an output signal indicative of a backside topography of the wafer.

Abstract: A method for adhering a reticle onto a top surface of a chuck is provided in accordance with some embodiments of the present disclosure. The method includes contacting a plurality of fibers on the top surface of the chuck with the reticle. The reticle is slid relative to the top surface of the chuck along a first direction to increase a contact area between the fibers and the reticle, such that the reticle is adhered to the fibers.

Abstract: A semiconductor device includes a carrier having a first central axis extending along a first direction and a second central axis extending along a second direction, a plurality of dies disposed on a surface of the carrier, and a plurality of scribing lines separating the plurality of dies from each other. The plurality of scribing lines include a plurality of continuous lines along the first direction and a plurality of discontinuous lines along the second direction, at least one of the plurality of continuous lines overlaps the first central axis, at least one of the plurality of discontinuous lines overlaps the second central axis. The plurality of dies are symmetrically arranged on the carrier about the first central axis and the second central axis.

Abstract: A method for semiconductor fabrication includes mounting a wafer onto a first wafer table. The first wafer table includes a first set of pins that support the wafer, the first set of pins having a first pitch between adjacent pins. The method further includes forming a first set of overlay marks on the wafer; and transferring the wafer onto a second wafer table. The second wafer table includes a second set of pins having a second pitch between adjacent pins. The second set of pins are individually and vertically movable, and the second pitch is smaller than the first pitch. The method further includes moving a portion of the second set of pins such that a remaining portion of the second set of pins supports the wafer and the remaining portion has the first pitch between adjacent pins.

Abstract: A temperature controlling apparatus includes a platen, a fluid source that supplies a fluid, a first conduit, a second conduit, and a plurality of outlet thermal sensors. The first conduit includes a first inlet, a first outlet, and a first heater configured to heat the fluid to a first heating temperature. The fluid having the first heating temperature is dispensed on the platen through the first outlet. The second conduit includes a second inlet, a second outlet and a second heater configured to heat the fluid to a second heating temperature different from the first heating temperature. The fluid having the second heating temperature is dispensed on the platen through the second outlet. The outlet thermal sensors are disposed at the first outlet and the second outlet to sense temperature of the fluid dispensed from the first outlet and the second outlet respectively.

Abstract: An interconnect structure and a method of forming the interconnect structure are provided. A dielectric layer and openings therein are formed over a substrate. A conductive seed layer is formed over the top surface and along a bottom and sidewalls of the openings. A conductive fill layer is formed over the seed layer. Metal oxide on the surface of the seed layer may be reduced/removed by a surface pre-treatment. The cleaned surface is covered by depositing fill material over the seed layer without exposing the surface to oxygen. The surface treatment may include a reactive remote plasma clean using hydrogen radicals. If electroplating is used to deposit the fill layer, then the surface treatment may include soaking the substrate in the electrolyte before turning on the electroplating current. Other surface treatments may include active pre-clean (APC) using hydrogen radicals; or Ar sputtering using a metal clean version xT (MCxT) tool.

Abstract: A system and method for monitoring qualities of teaching and learning are provided. The system includes at least one receiving interface, a processor, and an output apparatus, wherein the processor is electrically connected to the at least one receiving interface and the output apparatus. The at least one receiving interface receives at least one digital image. The processor identifies at least one facial message from the at least one digital image, identifies at least one body message from the at least one digital image, and determines at least one teaching and learning quality index according to the at least one facial message and the at least one body message. The output apparatus outputs the at least one facial message, the at least one body message, and the at least one teaching and learning quality index.

Abstract: A method for thinning a wafer is provided. The method includes placing a wafer on a support assembly and securing an etching mask to a backside of the wafer. The etching mask covers a peripheral portion of the wafer. The method further includes performing a wet etching process on the backside of the wafer to form a thinned wafer, and the thinned wafer includes peripheral portions having a first thickness and a central portion having a second thickness smaller than the first thickness. A system for forming the thinned wafer is also provided.

Abstract: The present disclosure provides a method for planarizing a metal-dielectric surface. The method includes: providing a slurry to a first metal-dielectric surface, wherein the first metal-dielectric surface comprises a silicon oxide portion and a metal portion, and wherein the slurry comprises a ceria compound; and performing a chemical mechanical polish (CMP) operation using the slurry to simultaneously remove the silicon oxide portion and the metal portion. The present disclosure also provides a method for planarizing a metal-dielectric surface and a method for manufacturing a semiconductor.

Abstract: An injection molding method includes the steps of positioning a core piece in a mold cavity through a plurality of positioning pins; injecting a molten plastic material into the mold cavity to surround and cover the core piece; maintaining the pressure inside the mold cavity at a predetermined maintaining time so that the core piece is positioned by the molten plastic material; retracting the positioning pins from the mold cavity when a predetermined retraction time is reached, so that spaces occupied by the positioning pins in the mold cavity can be filled with the molten plastic material; and completely curing the molten plastic material to form a finished product.

Abstract: Embodiments described herein relate to a dynamically controlled lens used in lithography tools. Multiple regions of the dynamic lens can be used to transmit a radiation beam for lithography process. By allowing multiple regions to transmit the radiation beam, the dynamically controlled lens can have an extended life cycle compared to conventional fixed lens. The dynamically controlled lens can be replaced or exchanged at a lower frequency, thus, improving efficiency of the lithography tools and reducing production cost.

Abstract: Embodiments of the present disclosure relate to apparatus and methods for cleaning an exhaust path of a semiconductor process tool. One embodiment provides an exhaust pipe section and a pipe cleaning assembly connected between a semiconductor process tool and a factory exhaust. The pipe cleaning assembly includes a residue remover disposed in the exhaust pipe section. The residue remover is operable to move in the exhaust pipe section to dislodge accumulated materials from an inner surface of the exhaust pipe section.

Abstract: A semiconductor package includes a semiconductor device, an encapsulating material, and a redistribution structure. The semiconductor device includes a chamfer disposed on one of a plurality of side surfaces of the semiconductor device. The encapsulating material encapsulates the semiconductor device. The redistribution structure is disposed over the encapsulating material and electrically connected to the semiconductor device.

Abstract: A semiconductor device includes a source and a drain and a channel disposed between the source and the drain, a first gate dielectric layer disposed on the channel, a first gate electrode disposed on the first gate dielectric layer, a second gate dielectric layer disposed on the first gate electrode, and a second gate electrode disposed on the second gate dielectric layer. The second gate dielectric layer is made of a ferroelectric material. A first area of a bottom surface of the first gate electrode which is in contact with the first gate dielectric layer where the is greater than a second area of a bottom surface of the second gate dielectric layer which is in contact with the first gate electrode.

Abstract: A method for forming a photoresist layer includes the following steps. A first photoresist layer is formed on a first wafer provided on a platen. The platen includes a plurality of temperature zones being at a first set of process temperatures. A first etching process is performed on the first wafer to form a first patterned metal layer. A profile variation of the first patterned metal layer with respect to a reference profile is determined. The first set of process temperatures is adjusted to a second set of process temperatures according to the profile variation. A second photoresist layer is formed on a second wafer provided on the platen with the temperature zones being at the second set of process temperatures respectively.

Abstract: A semiconductor package includes a carrier, at least and adhesive portion, a plurality of micro pins and a die. The carrier has a first surface and second surface opposite to the first surface. The adhesive portion is disposed on the first surface, and the plurality of the micro pins is disposed in the adhesive portions. The die is disposed on the remaining adhesive portion free of the micro pins.

Abstract: A method includes moving a sticky structure to a wafer table such that a first particle on the wafer table is adhered to the sticky structure, moving the sticky structure away from the wafer table after the first particle is adhered to the sticky structure, and performing a lithography process to a wafer held by the wafer table after moving the sticky structure away from the wafer table.