Patents by Inventor Hung Liao

Hung Liao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method of operating semiconductor apparatus and semiconductor apparatus
    Patent number: 10849214
    Abstract: A method of operating a semiconductor apparatus includes generating a target material droplet; exciting the target material droplet to generate radiation for exposing a wafer; receiving, by a catcher, the target material droplet after exciting the target material droplet, in which the catcher has a front section, a rear section, and a drain port at the rear section; heating the rear section of the catcher such that the target material droplet in the rear section is in a liquid phase; and maintaining a temperature of the front section of the catcher lower than a temperature of the rear section of the catcher.
    Type: Grant
    Filed: December 26, 2018
    Date of Patent: November 24, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Po-Ming Shih, Chi-Hung Liao
  • SLURRY
    Publication number: 20200357653
    Abstract: The present disclosure provides a slurry. The slurry includes an abrasive including a ceria compound; a removal rate regulator to adjust removal rates of the slurry to metal and to dielectric material; and a buffering agent to adjust a pH value of the slurry, wherein the slurry comprises a dielectric material removal rate higher than a metal oxide removal rate.
    Type: Application
    Filed: July 27, 2020
    Publication date: November 12, 2020
    Inventors: CHUN-HUNG LIAO, CHUNG-WEI HSU, TSUNG-LING TSAI, CHEN-HAO WU, AN-HSUAN LEE, SHEN-NAN LEE, TENG-CHUN TSAI, HUANG-LIN CHAO
  • METHOD AND SYSTEM FOR THINNING WAFER THEREOF
    Publication number: 20200357651
    Abstract: A method for thinning a wafer is provided. The method includes placing a wafer on a support assembly, and the support assembly includes a plurality of pin. The method includes securing an etching mask to a backside of the wafer, and the etching mask has an extending portion which covers a peripheral portion of the wafer. The etching mask has a plurality of circular bores extended along a vertical direction, and the etching mask is secured to the support assembly by connecting the circular bores and the pins. The method also includes performing a wet etching process on the backside of the wafer to foil a thinned wafer, wherein the thinned wafer has a peripheral portion with a first thickness and a central portion having a second thickness smaller than the first thickness.
    Type: Application
    Filed: July 27, 2020
    Publication date: November 12, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chien-Ling HWANG, Bor-Ping JANG, Hsin-Hung LIAO, Chung-Shi LIU
  • WAFER CHARACTERISTIC PREDICTION METHOD AND ELECTRONIC DEVICE
    Publication number: 20200334338
    Abstract: A wafer characteristic prediction method and an electronic device are provided. The method includes: receiving a process parameter of a wafer during a mass production; inputting the process parameter to a prediction model to obtain a wafer characteristic of the wafer being mass produced; and outputting the wafer characteristic.
    Type: Application
    Filed: July 22, 2019
    Publication date: October 22, 2020
    Applicant: DigWise Technology Corporation, LTD
    Inventors: JingJie Wu, Yuan-Hung Liao, Chih-Chen Liu
  • Wafer table with dynamic support pins
    Patent number: 10811300
    Abstract: A method for semiconductor fabrication includes mounting a wafer onto a first wafer table. The first wafer table includes a first set of pins that support the wafer, the first set of pins having a first pitch between adjacent pins. The method further includes forming a first set of overlay marks on the wafer; and transferring the wafer onto a second wafer table. The second wafer table includes a second set of pins having a second pitch between adjacent pins. The second set of pins are individually and vertically movable, and the second pitch is smaller than the first pitch. The method further includes moving a portion of the second set of pins such that a remaining portion of the second set of pins supports the wafer and the remaining portion has the first pitch between adjacent pins.
    Type: Grant
    Filed: December 18, 2019
    Date of Patent: October 20, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chi-Hung Liao, Min-Cheng Wu
  • Drippage prevention system and method of operating same
    Patent number: 10792697
    Abstract: A drippage prevention system including: a first automatic control valve (ACV), an input of the first ACV fluidically connected to a source of fluid to be dispensed, the first ACV having a position ranging from fully closed to fully open; a second ACV, an input of the second ACV being fluidically connected to the output of the first ACV, and an output of the second ACV being fluidically connected to a nozzle, the second ACV having positions ranging from fully closed to fully open; a proxy sensor configured to generate a proxy signal representing an indirect measure of a position of the first ACV; and a controller electrically connected to the first and second ACVs and the proxy sensor, the controller being configured to cause the second ACV to close based on the proxy signal and thereby stop flow of the liquid to the nozzle.
    Type: Grant
    Filed: May 17, 2017
    Date of Patent: October 6, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chien-Hung Wang, Chun-Chih Lin, Chi-Hung Liao, Yung-Yao Lee, Wei Chang Cheng
  • SEMICONDUCTOR PACKAGE STRUCTURE
    Publication number: 20200303214
    Abstract: A semiconductor package structure includes a molding compound, a micro pin extending through the molding compound, and a die surrounded by the molding compound. The micro pin has a top surface, a bottom surface, and a sidewall extending from the bottom surface to the top surface of the micro pin. The sidewall of the micro pin has a first portion and a second portion. The first portion of the sidewall is adjacent to the bottom surface of the micro pin and free of the molding compound. The second portion of the sidewall is adjacent to the top surface of the micro pin and in contact with the molding compound.
    Type: Application
    Filed: June 8, 2020
    Publication date: September 24, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chien-Ling HWANG, Bor-Ping JANG, Chung-Shi LIU, Hsin-Hung LIAO, Ying-Jui HUANG
  • PARTICLE REMOVAL FROM WAFER TABLE AND PHOTOMASK
    Publication number: 20200301292
    Abstract: A system includes a frame, a projection lens, a wafer table, and a cleaner. The frame has an opening vertically extending through the frame. The projection lens is disposed on the frame. The wafer table is below the frame, in which the wafer table is movable along a horizontal direction. The cleaner is over the frame, in which the cleaner comprises a sticky structure movable along a vertical direction and through the opening of the frame.
    Type: Application
    Filed: June 5, 2020
    Publication date: September 24, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Min-Cheng WU, Chi-Hung LIAO
  • METHOD OF FABRICATING SEMICONDUCTOR PACKAGE STRUCTURE
    Publication number: 20200303213
    Abstract: A method of fabricating a semiconductor package structure is provided. The method includes applying a plurality of first adhesive portions onto a carrier; applying a second adhesive portion onto the carrier; disposing a plurality of micro pins respectively in the first adhesive portions, such that each of the micro pins has a first portion embedded in a corresponding one of the first adhesive portions and a second portion protruding from said corresponding one of the first adhesive portions; bonding a die to the second adhesive portion; forming a molding compound surrounding the micro pins and the die; and removing the carrier from the molding compound after forming the molding compound.
    Type: Application
    Filed: June 8, 2020
    Publication date: September 24, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chien-Ling HWANG, Bor-Ping JANG, Chung-Shi LIU, Hsin-Hung LIAO, Ying-Jui HUANG
  • POST CMP CLEANING APPARATUS AND POST CMP CLEANING METHODS
    Publication number: 20200294821
    Abstract: A post CMP cleaning apparatus is provided. The post CMP cleaning apparatus includes a cleaning stage. The post CMP cleaning apparatus also includes a rotating platen disposed in the cleaning stage, and the rotating platen is configured to hold and rotate a semiconductor wafer. The post CMP cleaning apparatus further includes a vibrating device disposed over the rotating platen. The post CMP cleaning apparatus further includes a solution delivery module disposed near the vibrating device and configured to deliver a cleaning fluid to the semiconductor wafer. The vibrating device is configured to provide the cleaning fluid with a specific frequency which is at least greater than 100 MHz while the rotating platen is rotating the semiconductor wafer, so that particles on the semiconductor wafer are removed by the cleaning fluid.
    Type: Application
    Filed: March 14, 2019
    Publication date: September 17, 2020
    Inventors: Chen-Hao WU, Chu-An LEE, Chun-Hung LIAO, Shen-Nan LEE, Teng-Chun TSAI, Huang-Lin CHAO, Chih-Hung CHEN
  • SIGNAL PROCESSING DEVICE
    Publication number: 20200295791
    Abstract: A signal processing device includes a signal input, a signal output, a first amplifier, a second amplifier, a first distortion adjustment circuit, and a second distortion adjustment circuit. The signal input receives a RF signal to be amplified. The signal output outputs an amplified RF signal. Each of the first and second amplifiers includes an input coupled to the signal input and an output coupled to the signal output. The first distortion adjustment circuit includes a connection coupled to the input of the first amplifier. The second distortion adjustment circuit includes a connection coupled to the input of the second amplifier. The number of transistors in the first amplifier is different from the number of transistors in the second amplifier.
    Type: Application
    Filed: August 15, 2019
    Publication date: September 17, 2020
    Applicant: RichWave Technology Corp.
    Inventor: Lu-Hung Liao
  • Photolithography Method and Photolithography System
    Publication number: 20200292470
    Abstract: A photolithography method includes dispensing a first liquid onto a first target layer formed over a first wafer through a nozzle at a first distance from the first target layer; capturing an image of the first liquid on the first target layer; patterning the first target layer after capturing the image of the first liquid; comparing the captured image of the first liquid to a first reference image to generate a first comparison result; responsive to the first comparison result, positioning the nozzle and a second wafer such that the nozzle is at a second distance from a second target layer on the second wafer; dispensing a second liquid onto the second target layer formed over the second wafer through the nozzle at the second distance from the second target layer; and patterning the second target layer after dispensing the second liquid.
    Type: Application
    Filed: June 1, 2020
    Publication date: September 17, 2020
    Inventors: Chi-Hung Liao, Wei Chang Cheng
  • Lithography system and method for exposing wafer
    Patent number: 10775700
    Abstract: A method is provided. The method includes steps as follows. EUV light is generated. A collector is used to gather the EUV light onto a first optical reflector. The first optical reflector is used to reflect the EUV light to a reticle, so as to impart the EUV light with a pattern. A second optical reflector is used to reflect the EUV light with the pattern onto a wafer. The first optical reflector is rotated.
    Type: Grant
    Filed: June 21, 2019
    Date of Patent: September 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chi-Hung Liao, Min-Cheng Wu
  • Lithography apparatus and method using the same
    Patent number: 10775706
    Abstract: A method of lithography includes obtaining a profile of a single field of a substrate that having a photoresist layer thereon, in which the profile includes a first feature and a second feature having different heights. A depth of focus distribution map is generated according to the profile. A project lens is tuned based on the generated depth of focus distribution map, such that the project lens provides a first focus length in a first project pixel of the project lens and a second focus length in a second project pixel of the project lens, wherein the first focus length and the second focus lengths. The single field of the substrate is exposed by using the tuned project lens.
    Type: Grant
    Filed: September 27, 2018
    Date of Patent: September 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chi-Hung Liao, Min-Cheng Wu
  • Power circuit, gate driver and related operation control method for multi-source display system
    Patent number: 10777121
    Abstract: The present invention provides a protection circuit and related operation control method to enable the PFM circuit when the operating duration of the PFM circuit is not greater than a first threshold, and disables the PFM circuit when a rest duration of the PFM circuit is not greater than a second threshold. The present invention further provides a protection circuit and related operation control method to avoid starting excessive vertical scanning operations within one frame scanning period by masking one of the gate scanning start signal STV, the gate clock signal CKV and the gate discharge signal OEV. The present invention further provides a protection circuit and related operation control method to disable the gate scanning start signal STV when the number of clock cycles is not equal to a target number of clock cycles, which protects the gate driver from overload.
    Type: Grant
    Filed: November 21, 2019
    Date of Patent: September 15, 2020
    Assignee: HIMAX TECHNOLOGIES LIMITED
    Inventors: Chi-Hung Liao, Chang-Lung Wu, Jen-Chun Peng, Huan-Sen Liao, Kuo-Tung Hsu, Wei-Jen Chang
  • System and method for correcting non-ideal wafer topography
    Patent number: 10770327
    Abstract: A scanner includes a light source configured to apply a light to a backside of a wafer. The light is reflected from the backside of the wafer. A first mirror is configured to receive the light from the backside of the wafer and reflect the light. A sensor is configured to receive the light from the first mirror and generate an output signal indicative of a backside topography of the wafer.
    Type: Grant
    Filed: March 30, 2018
    Date of Patent: September 8, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Cheng-Mu Lin, Chi-Hung Liao, Yi-Ming Dai, Yueh Lin Yang
  • Photolithography apparatus and method and method for handling wafer
    Patent number: 10768534
    Abstract: A method for adhering a reticle onto a top surface of a chuck is provided in accordance with some embodiments of the present disclosure. The method includes contacting a plurality of fibers on the top surface of the chuck with the reticle. The reticle is slid relative to the top surface of the chuck along a first direction to increase a contact area between the fibers and the reticle, such that the reticle is adhered to the fibers.
    Type: Grant
    Filed: December 26, 2018
    Date of Patent: September 8, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Po-Ming Shih, Chi-Hung Liao
  • Semiconductor wafer device and manufacturing method thereof
    Patent number: 10770331
    Abstract: A semiconductor device includes a carrier having a first central axis extending along a first direction and a second central axis extending along a second direction, a plurality of dies disposed on a surface of the carrier, and a plurality of scribing lines separating the plurality of dies from each other. The plurality of scribing lines include a plurality of continuous lines along the first direction and a plurality of discontinuous lines along the second direction, at least one of the plurality of continuous lines overlaps the first central axis, at least one of the plurality of discontinuous lines overlaps the second central axis. The plurality of dies are symmetrically arranged on the carrier about the first central axis and the second central axis.
    Type: Grant
    Filed: August 20, 2018
    Date of Patent: September 8, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Bor-Ping Jang, Chien Ling Hwang, Hsin-Hung Liao, Yeong-Jyh Lin
  • Wafer Table With Dynamic Support Pins
    Publication number: 20200273741
    Abstract: A method for semiconductor fabrication includes mounting a wafer onto a first wafer table. The first wafer table includes a first set of pins that support the wafer, the first set of pins having a first pitch between adjacent pins. The method further includes forming a first set of overlay marks on the wafer; and transferring the wafer onto a second wafer table. The second wafer table includes a second set of pins having a second pitch between adjacent pins. The second set of pins are individually and vertically movable, and the second pitch is smaller than the first pitch. The method further includes moving a portion of the second set of pins such that a remaining portion of the second set of pins supports the wafer and the remaining portion has the first pitch between adjacent pins.
    Type: Application
    Filed: May 11, 2020
    Publication date: August 27, 2020
    Inventors: Chi-Hung Liao, Min-Cheng Wu
  • TEMPERATURE CONTROLLING APPARATUS
    Publication number: 20200264510
    Abstract: A temperature controlling apparatus includes a platen, a fluid source that supplies a fluid, a first conduit, a second conduit, and a plurality of outlet thermal sensors. The first conduit includes a first inlet, a first outlet, and a first heater configured to heat the fluid to a first heating temperature. The fluid having the first heating temperature is dispensed on the platen through the first outlet. The second conduit includes a second inlet, a second outlet and a second heater configured to heat the fluid to a second heating temperature different from the first heating temperature. The fluid having the second heating temperature is dispensed on the platen through the second outlet. The outlet thermal sensors are disposed at the first outlet and the second outlet to sense temperature of the fluid dispensed from the first outlet and the second outlet respectively.
    Type: Application
    Filed: May 7, 2020
    Publication date: August 20, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chi-Hung Liao, Wei-Chang Cheng