Abstract: Provided is a sensing and adaptation method for exercise. The method is applied to a sensing and adaptation device for exercise and includes the following steps: generating an exercise game and a first resistance setting to an exercise equipment according to a first exercise target data; receiving an exercise interactive data of a user operating the exercise game from the exercise equipment; generating a reaction-time data according to a stage data of the exercise game and the exercise interactive data and generating an operation trajectory data according to the first resistance setting, the stage data and the exercise interactive data; calculating a deviation degree of the operation trajectory data; calculating a second exercise target data according to the deviation degree; generating a second resistance setting and updating the exercise game according to the second exercise target, and transmitting the second resistance setting to the exercise equipment.

Abstract: In an embodiment, a device includes: an integrated circuit die; an encapsulant at least partially surrounding the integrated circuit die, the encapsulant including fillers having an average diameter; a through via extending through the encapsulant, the through via having a lower portion of a constant width and an upper portion of a continuously decreasing width, a thickness of the upper portion being greater than the average diameter of the fillers; and a redistribution structure including: a dielectric layer on the through via, the encapsulant, and the integrated circuit die; and a metallization pattern having a via portion extending through the dielectric layer and a line portion extending along the dielectric layer, the metallization pattern being electrically coupled to the through via and the integrated circuit die.

Abstract: A package substrate and a fabricating method thereof are provided, in which a core board body is provided, a first organic conductive layer and a second metal layer are sequentially formed on a first metal layer of the core board body, and portions of the first organic conductive layer and the first metal layer are removed respectively according to a pattern of the second metal layer, such that the second metal layer, or the second metal layer, the first organic conductive layer and the first metal layer are served as a first circuit layer. Therefore, the design of the organic conductive layer can facilitate the control of the side etching amount of the metal circuit during etching, enabling the production of circuit layer with fine line width/fine line pitch.

Abstract: A semiconductor package including a first semiconductor die, a second semiconductor die, a first insulating encapsulation, a dielectric layer structure, a conductor structure and a second insulating encapsulation is provided. The first semiconductor die includes a first semiconductor substrate and a through substrate via (TSV) extending from a first side to a second side of the semiconductor substrate. The second semiconductor die is disposed on the first side of the semiconductor substrate. The first insulating encapsulation on the second semiconductor die encapsulates the first semiconductor die. A terminal of the TSV is coplanar with a surface of the first insulating encapsulation. The dielectric layer structure covers the first semiconductor die and the first insulating encapsulation. The conductor structure extends through the dielectric layer structure and contacts with the through substrate via.

Abstract: A semiconductor package includes a semiconductor device, an encapsulating material, a redistribution structure, and an adhesive residue. The encapsulating material encapsulates a first part of a side surface of the semiconductor device. The redistribution structure is disposed over the semiconductor device and a first side of the encapsulating material. The adhesive residue is disposed over a second side of the encapsulating material opposite to the first side and surrounding the semiconductor device, wherein the adhesive residue encapsulates a second part of the side surface of the semiconductor device.

Abstract: A TIG welding flux for chromium-molybdenum steel is used to form a weld bead with high mechanical strength and high fracture toughness between two chromium-molybdenum steel workpieces. The TIG welding flux for chromium-molybdenum steel includes 30-44 wt % of silicon dioxide (SiO2), 20-35 wt % of manganese(IV) oxide (MnO2), 14-24 wt % of chromium(III) oxide (Cr2O3), 9-19 wt % of nickel(III) oxide (Ni2O3), 7-14 wt % of molybdenum trioxide (MoO3) and 5-10 wt % of calcium fluoride (CaF2).

Abstract: A device includes a first redistribution structure comprising a first conductive line and a second conductive line. An integrated circuit die is attached to the first redistribution structure. A first via is coupled to the first conductive line on a first side, and a first conductive connector is coupled to the first conductive line on a second side opposite the first side. A second via is coupled to the second conductive line on the first side, and a second conductive connector is coupled to the second conductive line on the second side. The first via directly contacts the first conductive line without directly contacting the first conductive connector. The second via directly contacts the second conductive line and directly contacts the second conductive connector.

Abstract: A method of manufacturing a carrying substrate is provided. At least one circuit component is disposed on a first circuit structure. An encapsulation layer is formed on the first circuit structure and encapsulates the circuit component. A second circuit structure is formed on the encapsulation layer and electrically connected to the circuit component. The circuit component is embedded in the encapsulation layer via an existing packaging process. Therefore, the routing area is increased, and a package substrate requiring a large size has a high yield and low manufacturing cost.

Abstract: An apparatus is disclosed for making circuitry with passive fundamental components more robust. In example implementations, an apparatus includes at least one passive fundamental component and at least one redundant passive fundamental component. The apparatus also includes fault tolerant circuitry coupled to the at least one passive fundamental component and the at least one redundant passive fundamental component. The fault tolerant circuitry includes fault detection circuitry configured to detect a fault of the at least one passive fundamental component. The fault tolerant circuitry also includes component repair circuitry configured to disconnect the at least one passive fundamental component based on the fault.

Abstract: A semiconductor device includes first IC dies disposed side-by-side, a second IC die overlapping and electrically coupled to the first IC dies, and first conductive features. Each first IC die includes first and second die connectors. A first pitch of the first die connectors is less than a second pitch of the second die connectors and is substantially equal to a third pitch of the third die connectors of the second IC die. The first conductive features are interposed between and electrically coupled to the first and third die connectors. Each first conductive feature includes at least a first conductive bump and at least a first conductive joint.

Abstract: In an embodiment, a device includes: a back-side redistribution structure including: a metallization pattern on a first dielectric layer; and a second dielectric layer on the metallization pattern; a through via extending through the first dielectric layer to contact the metallization pattern; an integrated circuit die adjacent the through via on the first dielectric layer; a molding compound on the first dielectric layer, the molding compound encapsulating the through via and the integrated circuit die; a conductive connector extending through the second dielectric layer to contact the metallization pattern, the conductive connector being electrically connected to the through via; and an intermetallic compound at the interface of the conductive connector and the metallization pattern, the intermetallic compound extending only partially into the metallization pattern.

Abstract: In an embodiment, a device includes: a back-side redistribution structure including: a metallization pattern on a first dielectric layer; and a second dielectric layer on the metallization pattern; a through via extending through the first dielectric layer to contact the metallization pattern; an integrated circuit die adjacent the through via on the first dielectric layer; a molding compound on the first dielectric layer, the molding compound encapsulating the through via and the integrated circuit die; a conductive connector extending through the second dielectric layer to contact the metallization pattern, the conductive connector being electrically connected to the through via; and an intermetallic compound at the interface of the conductive connector and the metallization pattern, the intermetallic compound extending only partially into the metallization pattern.

Abstract: A semiconductor structure includes a first die; a plurality of first conductive vias adjacent to the first die. The semiconductor structure further includes a plurality of second conductive vias disposed over the first conductive vias, each of the second conductive vias corresponding to one of the first conductive vias; a plurality of third conductive vias disposed over the first die; and a molding material encapsulating the first die, the first conductive vias, the second conductive vias and the third conductive vias. A first width of each of the plurality of first conductive vias, a second width of each of the plurality of second conductive vias and a third width of the plurality of third conductive vias are different from each other.

Abstract: A method of manufacturing a carrying substrate is provided. At least one circuit component is disposed on a first circuit structure. An encapsulation layer is formed on the first circuit structure and encapsulates the circuit component. A second circuit structure is formed on the encapsulation layer and electrically connected to the circuit component. The circuit component is embedded in the encapsulation layer via an existing packaging process. Therefore, the routing area is increased, and a package substrate requiring a large size has a high yield and low manufacturing cost.

Abstract: An apparatus is disclosed for robust transistor circuitry. In example implementations, an apparatus includes a current mirror and fault handler circuitry that is coupled to the current mirror. The current mirror includes a core transistor having a control terminal, a first transistor, and a second transistor. The first transistor has a control terminal that is coupled to the control terminal of the core transistor. The second transistor has a control terminal that is coupled to the control terminal of the core transistor. The fault handler circuitry is configured to select the first transistor or the second transistor to provide a mirrored current of the current mirror.

Abstract: A package structure including a first semiconductor die, a second semiconductor die, first conductive pillars and a first insulating encapsulation is provided. The first semiconductor die includes a semiconductor substrate, an interconnect structure and a first redistribution circuit structure. The semiconductor substrate includes a first portion and a second portion disposed on the first portion. The interconnect structure is disposed on the second portion, the first redistribution circuit structure is disposed on the interconnect structure, and the lateral dimension of the first portion is greater than the lateral dimension of the second portion. The second semiconductor die is disposed on the first semiconductor die. The first conductive pillars are disposed on the first redistribution circuit structure of the first semiconductor die. The first insulating encapsulation is disposed on the first portion.

Abstract: Coil structures and methods of forming are provided. The coil structure includes a substrate. A plurality of coils is disposed over the substrate, each coil comprising a conductive element that forms a continuous spiral having a hexagonal shape in a plan view of the coil structure. The plurality of coils is arranged in a honeycomb pattern, and each conductive element is electrically connected to an external electrical circuit.

Abstract: An electronic package and a circuit structure thereof are provided, in which a circuit layer and an electrical function part are formed on a dielectric layer of the circuit structure, and the dielectric layer has at least one corner at a right angle, where a shape of the electrical function part at the corner and corresponding to the right angle is of a non-right angle shape and/or a routing path of the circuit layer at the corner and corresponding to the right angle is of a non-right angle shape, so that stress concentration can be reduced, thereby preventing the electronic package from warping.

Abstract: A semiconductor structure includes a first die; a second die disposed over the first die; a plurality of first conductive vias adjacent to the first die. The semiconductor structure further includes a plurality of second conductive vias disposed over the first conductive vias, each of the second conductive vias corresponding to one of the first conductive vias; a plurality of third conductive vias disposed over the first die and adjacent to the second die; and a molding material encapsulating the first die, the second die, the first conductive vias, the second conductive vias and the third conductive vias. A stepped shape is formed around an interface between each of the first conductive vias and the corresponding one of the second conductive vias.

Abstract: A method includes bonding a first device die to a second device die, encapsulating the first device die in a first encapsulant, performing a backside grinding process on the second device die to reveal through-vias in the second device die, and forming first electrical connectors on the second device die to form a package. The package includes the first device die and the second device die. The method further includes encapsulating the first package in a second encapsulant, and forming an interconnect structure overlapping the first package and the second encapsulant. The interconnect structure comprises second electrical connectors.