Abstract: In an embodiment, a device includes: an integrated circuit die; an encapsulant at least partially surrounding the integrated circuit die, the encapsulant including fillers having an average diameter; a through via extending through the encapsulant, the through via having a lower portion of a constant width and an upper portion of a continuously decreasing width, a thickness of the upper portion being greater than the average diameter of the fillers; and a redistribution structure including: a dielectric layer on the through via, the encapsulant, and the integrated circuit die; and a metallization pattern having a via portion extending through the dielectric layer and a line portion extending along the dielectric layer, the metallization pattern being electrically coupled to the through via and the integrated circuit die.

Abstract: A method includes forming a plurality of first conductive vias over a redistribution layer (RDL); disposing a first die over the RDL and adjacent to the first vias; and forming a plurality of second conductive vias over and electrically connected to the first conductive vias, each of the second conductive vias corresponding to one of the first conductive vias. The method further includes forming a plurality of third conductive vias over the first die; disposing a second die over the first die and adjacent to the third conductive vias; and encapsulating the first die, the second die, the first conductive vias, the second conductive vias and the third conductive vias with a molding material.

Abstract: A method of manufacturing a semiconductor package includes depositing a first dielectric layer over a carrier substrate. A first metallization pattern is formed over the first dielectric layer. The first metallization pattern has a first opening exposing the first dielectric layer. A second dielectric layer is deposited over the first metallization pattern, forming a dielectric slot through the first metallization pattern by filling the first opening. A second metallization pattern and a third dielectric layer are formed over the second dielectric layer. A through via is formed over the third dielectric layer, so that the dielectric slot is laterally under the through via.

Abstract: The present invention relates to a fiber composite material and a method for producing the fiber composite material. The method for producing the fiber composite material includes a hydrolysis step of a silicon precursor having an alkoxy group, an in-situ condensation step and a drying step. A specific silicon precursor having a secondary amino group and alkyl groups is used therein, as well as a specific weight ratio of the silicon precursor to a fiber material, the in-situ condensation step can be performed in the absence of organic solvents in the method for producing the fiber composite material, and a hydrophobic modification on silicon-based gels can be performed, thereby simplifying the process, decreasing a thermal conductivity of the resulted fiber composite material and preventing drop dust of the resulted fiber composite material.

Abstract: The present invention relates to silicon-based powders and a method for producing the silicon-based powders. The method for producing the silicon-based powders includes a hydrolysis step of a silicon precursor having an alkoxy group, a condensation step and a drying step. By a specific weight ratio of water to the silicon precursor having the alkoxy group and a silicon precursor having a secondary amino group and an alkyl group, in the method for producing the silicon-based powders, the condensation step can be performed without organic solvents, and a modification on silicon-based gels can be performed to enhance a safety of processes and a hydrophobicity of the resulted silicon-based powders, and decrease a thermal conductivity and a bulk density of the resulted silicon-based powders.

Abstract: A smart power stage (SPS) circuit of a power converter and a current monitoring circuit thereof are disclosed. The SPS circuit includes an output stage circuit and a driver. The output stage circuit receives an input voltage and the power converter provides an output voltage and an inductor current. The driver includes a driving circuit, a monitoring signal generation circuit and a compensation circuit. The driving circuit receives a PWM signal and provides a driving signal to the output stage circuit. The monitoring signal generation circuit receives the PWM signal, input voltage and output voltage for generating a monitoring signal related to the inductor current. The monitoring signal includes a simulated current signal. The compensation circuit is coupled to the monitoring signal generation circuit. When the simulated current signal is greater than a default value, the compensation circuit generates a compensation signal superposing to the simulated current signal.

Abstract: A method includes forming a first redistribution structure by depositing a first dielectric layer and forming first and second conductive features on the first dielectric layer, the second conductive feature being provided with a gap exposing the first dielectric layer. The method further includes depositing a second dielectric layer on the first and second conductive features; forming first and second openings in the second dielectric layer, the first opening exposing the first conductive feature and the second opening exposing the second conductive feature and the gap; forming a first via on the first conductive feature and partially in the first opening; forming a second via on the second conductive feature and partially in the second opening and the gap; attaching a die to the first redistribution structure adjacent the first via and the second via; and encapsulating the die, the first via, and the second via with an encapsulant.

Abstract: A method of using a tungsten inert gas (TIG) welding flux for super duplex stainless steel (SDSS) is used to solve the problems of low weld depth/width ratio, low corrosion resistance, and arc blow existing in the conventional TIG welding flux for duplex stainless steel. The TIG welding flux for SDSS includes 20-30 wt % of silicon dioxide (SiO2), 20-25 wt % of titanium dioxide (TiO2), 15-20 wt % of vanadium dioxide (VO2), 10-15 wt % of molybdenum trioxide (MoO3), 10-15 wt % of zirconium diboride (ZrB2), 5-10 wt % of aluminum nitride (AlN), 5-10 wt % of manganese carbonate (MnCO3) and 5-10 wt % of nickel carbonate (NiCO3).

Abstract: A package structure including a first semiconductor die, a second semiconductor die, first conductive pillars and a first insulating encapsulation is provided. The first semiconductor die includes a semiconductor substrate, an interconnect structure and a first redistribution circuit structure. The semiconductor substrate includes a first portion and a second portion disposed on the first portion. The interconnect structure is disposed on the second portion, the first redistribution circuit structure is disposed on the interconnect structure, and the lateral dimension of the first portion is greater than the lateral dimension of the second portion. The second semiconductor die is disposed on the first semiconductor die. The first conductive pillars are disposed on the first redistribution circuit structure of the first semiconductor die. The first insulating encapsulation is disposed on the first portion.

Abstract: A TIG welding flux for dissimilar steels is used to solve the problem that the conventional friction stir welding procedure for butt-joint welding a stainless steel workpiece and a carbon steel workpiece cannot be used on site, as well as the problem that the increased operating time and manufacturing cost due to forming bevel faces on both the stainless steel workpiece and the carbon steel workpiece. The TIG welding flux for dissimilar steels includes 25-35 wt % of silicon dioxide (SiO2), 20-30 wt % of cobalt (II, III) oxide (Co3O4), 15-20 wt % of manganese (II, III) oxide (Mn3O4), 10-15 wt % of nickel (III) oxide (Ni2O3), 7-12 wt % of molybdenum trioxide (MoO3), 6-11 wt % of manganese (II) carbonate (MnCO3), 5-10 wt % of nickel (II) carbonate (NiCO3), and 2-4 wt % of aluminum fluoride (AlF3).

Abstract: A method includes forming a first metal mesh over a carrier, forming a first dielectric layer over the first metal mesh, and forming a second metal mesh over the first dielectric layer. The first metal mesh and the second metal mesh are staggered. The method further includes forming a second dielectric layer over the second metal mesh, attaching a device die over the second dielectric layer, with the device die overlapping the first metal mesh and the second metal mesh, encapsulating the device die in an encapsulant, and forming redistribution lines over and electrically connecting to the device die.

Abstract: Wireless charging devices, methods of manufacture thereof, and methods of charging electronic devices are disclosed. In some embodiments, a wireless charging device includes a controller, a molding material disposed around the controller, and an interconnect structure disposed over the molding material and coupled to the controller. The wireless charging device includes a wireless charging coil coupled to the controller. The wireless charging coil comprises a first portion disposed in the interconnect structure and a second portion disposed in the molding material. The wireless charging coil is adapted to provide an inductance to charge an electronic device.

Abstract: Coil structures and methods of forming are provided. The coil structure includes a substrate. A plurality of coils is disposed over the substrate, each coil comprising a conductive element that forms a continuous spiral having a hexagonal shape in a plan view of the coil structure. The plurality of coils is arranged in a honeycomb pattern, and each conductive element is electrically connected to an external electrical circuit.

Abstract: In an embodiment, a device includes: an integrated circuit die; an encapsulant at least partially surrounding the integrated circuit die, the encapsulant including fillers having an average diameter; a through via extending through the encapsulant, the through via having a lower portion of a constant width and an upper portion of a continuously decreasing width, a thickness of the upper portion being greater than the average diameter of the fillers; and a redistribution structure including: a dielectric layer on the through via, the encapsulant, and the integrated circuit die; and a metallization pattern having a via portion extending through the dielectric layer and a line portion extending along the dielectric layer, the metallization pattern being electrically coupled to the through via and the integrated circuit die.

Abstract: An apparatus is disclosed for robust transistor circuitry. In example implementations, an apparatus includes a current mirror and fault handler circuitry that is coupled to the current mirror. The current mirror includes a core transistor having a control terminal, a first transistor, and a second transistor. The first transistor has a control terminal that is coupled to the control terminal of the core transistor. The second transistor has a control terminal that is coupled to the control terminal of the core transistor. The fault handler circuitry is configured to select the first transistor or the second transistor to provide a mirrored current of the current mirror.

Abstract: An apparatus is disclosed for making circuitry with passive fundamental components more robust. In example implementations, an apparatus includes at least one passive fundamental component and at least one redundant passive fundamental component. The apparatus also includes fault tolerant circuitry coupled to the at least one passive fundamental component and the at least one redundant passive fundamental component. The fault tolerant circuitry includes fault detection circuitry configured to detect a fault of the at least one passive fundamental component. The fault tolerant circuitry also includes component repair circuitry configured to disconnect the at least one passive fundamental component based on the fault.

Abstract: An object orientation identification method and an object orientation identification device are provided. The method is adapted for the object orientation identification device including a wireless signal transceiver. The object orientation identification device and a target object are both in a moving state. The method includes the following. A first signal is continuously transmitted by the wireless signal transceiver. A second signal reflected back from the target object is received by the wireless signal transceiver. Signal pre-processing is performed on the first signal and the second signal to obtain moving information of the target object with respect to the object orientation identification device. The moving information is input into a deep learning model to obtain orientation information of the target object with respect to the object orientation identification device.

Abstract: In an embodiment, a device includes: a back-side redistribution structure including: a metallization pattern on a first dielectric layer; and a second dielectric layer on the metallization pattern; a through via extending through the first dielectric layer to contact the metallization pattern; an integrated circuit die adjacent the through via on the first dielectric layer; a molding compound on the first dielectric layer, the molding compound encapsulating the through via and the integrated circuit die; a conductive connector extending through the second dielectric layer to contact the metallization pattern, the conductive connector being electrically connected to the through via; and an intermetallic compound at the interface of the conductive connector and the metallization pattern, the intermetallic compound extending only partially into the metallization pattern.

Abstract: A TIG welding flux for chromium-molybdenum steel is used to form a weld bead with high mechanical strength and high fracture toughness between two chromium-molybdenum steel workpieces. The TIG welding flux for chromium-molybdenum steel includes 30-44 wt % of silicon dioxide (SiO2), 20-35 wt % of manganese(IV) oxide (MnO2), 14-24 wt % of chromium(III) oxide (Cr2O3), 9-19 wt % of nickel(III) oxide (Ni2O3), 7-14 wt % of molybdenum trioxide (MoO3) and 5-10 wt % of calcium fluoride (CaF2).

Abstract: A structure includes an encapsulating material, and a coil including a through-conductor. The through-conductor is in the encapsulating material, with a top surface of the through-conductor coplanar with a top surface of the encapsulating material, and a bottom surface of the through-conductor coplanar with a bottom surface of the encapsulating material. A metal plate is underlying the encapsulating material. A slot is in the metal plate and filled with a dielectric material. The slot has a portion overlapped by the coil.