Abstract: A locking method for an electronic device includes steps of: (a) adjusting working stages of an electronic device locking apparatus according to a size of an anti-theft hole of an electronic device; (b) inserting a fixing member into the anti-theft hole; and (c) switching a lock to a locking state, such that the electronic device locking apparatus and the electronic device are inseparable. Movements of the working stages and the fixing member are separate. The working stages can be adjusted in advance, and then the fixing member is inserted into and is unfolded to engage in the anti-theft hole. When unlocking, just folding the fixing member and then the fixing member can leave the anti-theft hole. The fixing member can be used to engage in the anti-theft hole of the same size, directly without changing the working stage, which is convenient to use.

Abstract: Provided is an integrated microfluidic device for SARS-CoV-2 detection. Also provided is a method for detecting SARS-CoV-2 by using the same, comprising viral lysis, RNA extraction, and reverse-transcription loop-mediated isothermal amplification (RT-LAMP). The integrated microfluidic device of the present disclosure is small in size, automatically operatable, and easy to use by ordinary people, and the present disclosure can achieve rapid detection with high sensitivity and specificity.

Abstract: A stepless adjustable electronic device locking apparatus has a fixing member, a stage adjusting mechanism, a driving mechanism, an unlocking member, and a lock. The driving mechanism selectively unfolds the fixing member to engage in an anti-theft hole based on a current one of working stages to which the stage adjusting mechanism adjusts. The unlocking member is able to fold the fixing member. By separating adjustment of the working stages and movement of the fixing member, the movements of the fixing member do not interfere in the working stages. Therefore, the unlocking member can be applied to the driving mechanism to unlock. The fixing member can be folded to disengage from the anti-theft hole through the unlocking member without being reversely rotated and adjusting the working stages, so as to unlocking quickly.

Abstract: A driving circuit includes at least one light-emitting element, a drive line, a data line, a touch sensor, and a read line. The drive line is electrically coupled to a first terminal of the at least one light-emitting element. The data line is electrically coupled to a second terminal of the at least one light-emitting element. The drive line is electrically coupled to a first terminal of the touch sensor. The read line is electrically coupled to a second terminal of the touch sensor. The read line is electrically isolated from the data line.

Abstract: Various embodiments of the present disclosure are directed towards a method for forming a semiconductor structure. The method includes loading a first wafer and a second wafer onto a bonding platform such that the second wafer overlies the first wafer. An alignment process is performed to align the second wafer over the first wafer by virtue of a plurality of wafer pins, where a plurality of first parameters are associated with the wafer pins during the alignment process. The second wafer is bonded to the first wafer. An overlay (OVL) measurement process is performed on the first wafer and the second wafer by virtue of the plurality of wafer pins, where a plurality of second parameters are associated with the wafer pins during the alignment process.

Abstract: Structures and methods for reducing process charging damages are disclosed. In one example, a silicon-on-insulator (SOI) structure is disclosed. The SOI structure includes: a substrate, a polysilicon region and an etch stop layer. The substrate includes: a handle layer, an insulation layer arranged over the handle layer, and a buried layer arranged over the insulation layer. The polysilicon region extends downward from an upper surface of the buried layer and terminates in the handle layer. The etch stop layer is located on the substrate. The etch stop layer is in contact with both the substrate and the polysilicon region.

Abstract: An electronic module is provided. The electronic module includes a first transducer and a second transducer. The first transducer is configured to radiate a first ultrasonic wave. The second transducer is configured to radiate a second ultrasonic wave. The first transducer and the second transducer are disposed on noncoplanar surfaces.

Abstract: A semiconductor device includes an ultra-thick metal (UTM) structure. The semiconductor device includes a passivation layer including a first passivation oxide. The first passivation oxide includes an unbias film and a first bias film, where the unbias film is on portions of the UTM structure and on portions of a layer on which the UTM structure is formed, and the first bias film is on the unbias film. The passivation layer includes a second passivation oxide consisting of a second bias film, the second bias film being on the first bias film. The passivation layer includes a third passivation oxide consisting of a third bias film, the third bias film being on the second bias film.

Abstract: An image identification method is used to eliminate accumulated error of operation of a joystick. The joystick has an optical sensor adapted to analyze a movement of a plurality of identification dots disposed on a stick body. The image identification method includes receiving a series of detection images, setting a first identification dot of the plurality of identification dots as being a reference identification dot, and setting a second identification dot of the plurality of identification dos as being the reference identification dot and cancelling the first identification dot as being the reference identification dot when the first identification dot is near a border of the detection image. A position change of the reference identification dot in the series of detection images is used for identifying a control status of the joystick.

Abstract: Provided is a memory device including a substrate, a stack structure, a plurality of pads and an additional dielectric layer. The substrate has an array region and a staircase region. The stack structure is disposed on the substrate. The stack structure includes a plurality of dielectric layers and a plurality of conductive layers stacked alternately. The pads are disposed on the substrate in the staircase region. The pads are respectively connected to the conductive layers, so as to form a staircase structure. The additional dielectric layer is disposed on the stack structure to contact a topmost conductive layer of the conductive layers. A topmost pad of the pads includes a landing portion to contact a plug and an extension portion. The landing portion is laterally adjacent to the additional dielectric layer, and the extension portion extends over a top surface of the additional dielectric layer.

Abstract: A monitoring device for physiological signal monitoring includes a first light receiving and transmitting device and a control device. The first light receiving and transmitting device generates a first light signal to an object and receives a second light signal to generate a first electrical signal. The control device controls the first light receiving and transmitting device to generate the first light signal in a first period, and controls the first light receiving and transmitting device to receive the second light signal to generate the first electrical signal in a second period. The invention further includes an operating method for physiological signal monitoring.

Abstract: There is provided a detection system including a detection device and a post processor. The detection device and the post processor exchange data therebetween using a predetermined communication protocol. The detection device outputs at least one of calculated data and raw data to the post processor in response to each polling according to a request from the post processor. The raw data is provided to the post processor for the machine learning.

Abstract: A semiconductor structure including a substrate, a first dielectric layer, a first conductive feature, an etch stop layer, a second dielectric layer and a second conductive feature is provided. The first dielectric layer is disposed over the substrate. The first conductive feature is disposed in the first dielectric layer. The etch stop layer is disposed over the first dielectric layer and the first conductive feature, wherein the etch stop layer comprises a metal-containing layer and a silicon-containing layer, the metal-containing layer is located between the first dielectric layer and the silicon-containing layer, the metal-containing layer comprises a nitride-containing region and an oxide-containing region, and the nitride-containing region contacts the first conductive feature. The second dielectric layer is disposed over the etch stop layer. The second conductive feature penetrates the second dielectric layer and electrically connects with the first conductive feature.

Abstract: A pressure sensing element has an elastic porous substrate, an electrode, an upper protective layer, and a lower protective layer. The elastic porous substrate is provided with a piezoelectric layer on a surface of the elastic porous substrate. The electrode is formed on at least one of a top and a bottom of the elastic porous substrate. The upper protective layer and a lower protective layer are provided respectively above and below the elastic porous substrate. The elastic porous substrate has multiple holes arranged in regular and repetitive patterns including gyroidal structures, lattice structures or schwarz structures.

Abstract: A method of forming a semiconductor device includes: forming a first conductive feature in a first dielectric layer disposed over a substrate; forming a metal cap layer over an upper surface of the first conductive feature distal from the substrate; selectively forming a dielectric cap layer over an upper surface of the first dielectric layer and laterally adjacent to the metal cap layer, wherein the metal cap layer is exposed by the dielectric cap layer; and forming an etch stop layer stack over the metal cap layer and the dielectric cap layer, wherein the etch stop layer stack comprises a plurality of etch stop layers.

Abstract: A semiconductor device includes a substrate, a first conductive feature over a portion of the substrate, and an etch stop layer over the substrate and the first conductive feature. The etch stop layer includes a silicon-containing dielectric (SCD) layer and a metal-containing dielectric (MCD) layer over the SCD layer. The semiconductor device further includes a dielectric layer over the etch stop layer, and a second conductive feature in the dielectric layer. The second conductive feature penetrates the etch stop layer and electrically connects to the first conductive feature.

Abstract: An isolated cancer-targeting peptide that includes at least two copies of the amino acid sequence PFLP (SEQ ID NO: 1) or PFLF (SEQ ID NO: 2). Also disclosed is a pharmaceutical composition for treating cancer. The composition contains the isolated cancer-targeting peptide and an anti-cancer agent. Further disclosed is a bispecific anti-cancer antibody that includes the isolated cancer-targeting peptide and an antigen-binding peptide that stimulates T cell activity. Methods are provided for treating cancer by administering the pharmaceutical composition or the bispecific anti-cancer antibody. Further provided is a method for diagnosing cancer by administering a radionuclide-labeled cancer-targeting peptide to an individual and imaging a location of the radionuclide.

Abstract: An improved method of forming conductive features and a semiconductor device formed by the same are disclosed. In an embodiment, a method includes providing a first conductive feature in a first dielectric layer; selectively depositing an etch-resistant layer over the first dielectric layer, a sidewall of the etch-resistant layer being coterminous with a sidewall of the first dielectric layer; after selectively depositing the etch-resistant layer, selectively depositing a capping layer over the first conductive feature adjacent the etch-resistant layer, a sidewall of the capping layer being coterminous with a sidewall of the first conductive feature; and forming a second conductive feature over the capping layer, the etch-resistant layer separating the second conductive feature from the first dielectric layer.

Abstract: An electronic system test method, comprising: (a)inputting a victim test pattern to a victim signal path of a target electronic system and simultaneously inputting at least one aggressor test pattern to at least one aggressor signal path of the target electronic system, according to a major set of test patterns comprising a plurality of minor set of test patterns; (b)acquiring a output response corresponding to the step (a); and (c)after changing the victim test pattern or the aggressor test pattern, and after repeating the step (a) and the step (b) until all of the major test patterns set are used thereby acquiring a plurality of the output responses, determining a combination level according to the output responses. The victim test pattern is an X bit pattern and the aggressor test pattern is a Y bit pattern, X and Y are positive integers larger than or equal to 3.

Abstract: The present disclosure provides a method of manufacturing a semiconductor device. The method includes providing a structure having a frontside and a backside, the structure including a substrate and a stack of a first type and a second type epitaxial layers having different material compositions alternatively stacked above the substrate, wherein the stack is at the frontside of the structure and the substrate is at the backside of the structure; patterning the stack, thereby forming a fin above the substrate; implanting a first dopant into a first region of the fin, the first dopant having a first conductivity type; implanting a second dopant into a second region of the fin, the second dopant having a second conductivity type opposite the first conductivity type; and forming a first contact on the first region and a second contact on the second region.