Patents by Inventor Hung Wang

Hung Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230121210
    Abstract: An improved method of forming conductive features and a semiconductor device formed by the same are disclosed. In an embodiment, a method includes forming a metal line extending through a first dielectric layer, the metal line being electrically coupled to a transistor; selectively depositing a sacrificial material over the metal line; selectively depositing a first dielectric material over the first dielectric layer and adjacent to the sacrificial material; selectively depositing a second dielectric material over the first dielectric material; removing the sacrificial material to form a first recess exposing the metal line; and forming a metal via in the first recess and electrically coupled to the metal line.
    Type: Application
    Filed: March 31, 2022
    Publication date: April 20, 2023
    Inventors: Wei-Ren Wang, Jen Hung Wang, Tze-Liang Lee
  • Publication number: 20230121958
    Abstract: Interconnect structures exhibiting reduced accumulation of copper vacancies along interfaces between contact etch stop layers (CESLs) and interconnects, along with methods for fabrication, are disclosed herein. A method includes forming a copper interconnect in a dielectric layer and depositing a metal nitride CESL over the copper interconnect and the dielectric layer. An interface between the metal nitride CESL and the copper interconnect has a first surface nitrogen concentration, a first nitrogen concentration and/or a first number of nitrogen-nitrogen bonds. A nitrogen plasma treatment is performed to modify the interface between the metal nitride CESL and the copper interconnect.
    Type: Application
    Filed: December 20, 2022
    Publication date: April 20, 2023
    Inventors: Hui Lee, Po-Hsiang Huang, Wen-Sheh Huang, Jen Hung Wang, Su-Jen Sung, Chih-Chien Chi, Pei-Hsuan Lee
  • Patent number: 11630514
    Abstract: A brainwave feedback system, adapted to generate feedback based on a user's brainwave, the brainwave feedback system comprises: a brainwave sensing device, configured to obtain a first brainwave signal of the user; a server, storing a keyword string pool including a plurality of sorted keywords, and performing a feedback procedure when a first physiological parameter falls outside of a predetermined parameter range, wherein the first physiological parameter is associated with the first brainwave signal, the feedback procedure includes choosing a keyword from the keyword string pool by the server as a feedback keyword, and outputting the feedback keyword; and an output component, in communicable connection with the server, wherein the output component presents an analysis result corresponding to the first physiological parameter. The present disclosure further discloses an operation method of brainwave feedback system.
    Type: Grant
    Filed: May 28, 2020
    Date of Patent: April 18, 2023
    Assignee: NATIONAL CHENG KUNG UNIVERSITY
    Inventors: Sheng-Fu Liang, Fu-Zen Shaw, Chih-En Kuo, Yung-Hung Wang, Tsung-Hua Lu, Tsung-Hao Hsieh, Tai-Jie Yun, Jen Jui Hsueh, I Yu Chen
  • Publication number: 20230103920
    Abstract: The present invention provides a method of angiography for cerebrovascular obliteration includes: using a classifier to obtain a 2D medical image using from a plurality of Multiphase CTA images; using a gray-scale conversion to obtain a N*M pixels grayscale image; filtering the grayscale image not being meet a condition of grayscale threshold and performing an image binarization to obtain a binarized image; confirming at least one vascular region and performing an image skeletonization; filtering according to a vascular image features of a vascular region to obtain a vascular-enhanced image; using a fracture analysis to obtain an analysis report related to a plurality of quantifying parameters of vascular characteristics; wherein the quantifying parameters of vascular characteristics comprises a quantitative value of fractal dimension (FD), vessel density (VD), skeleton density (SD) and vascular diameter index (VDI).
    Type: Application
    Filed: October 6, 2022
    Publication date: April 6, 2023
    Inventors: Tzong-Rong Ger, Chi-Ming Ku, Chun-Hung Wang
  • Patent number: 11610842
    Abstract: Provided is a memory device including a substrate, a stack structure, a plurality of pads, and a protective layer. The substrate has an array region and a staircase region. The stack structure is disposed on the substrate. The stack structure includes a plurality of dielectric layers and a plurality of conductive layers stacked alternately. The pads are disposed on the substrate in the staircase region. The pads are respectively connected to the conductive layers, so as to form a staircase structure. The protective layer is disposed on the stack structure to contact a topmost conductive layer. A top surface of the protective layer adjacent to a topmost pad has a curved profile.
    Type: Grant
    Filed: December 2, 2020
    Date of Patent: March 21, 2023
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Ching Hung Wang, Shih Chin Lee, Chen-Yu Cheng, Tzung-Ting Han
  • Patent number: 11598828
    Abstract: The present disclosure generally relates to a Wheatstone bridge array that has four resistors. Each resistor includes a plurality of TMR structures. Two resistors have identical TMR structures. The remaining two resistors also have identical TMR structures, though the TMR structures are different from the other two resistors. Additionally, the two resistors that have identical TMR structures have a different resistance area as compared to the remaining two resistors that have identical TMR structures. Therefore, the working bias field for the Wheatstone bridge array is non-zero.
    Type: Grant
    Filed: December 30, 2019
    Date of Patent: March 7, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventors: Yuankai Zheng, Christian Kaiser, Zhitao Diao, Chih-Ching Hu, Chen-jung Chien, Yung-Hung Wang, Dujiang Wan, Ronghui Zhou, Ming Mao, Ming Jiang, Daniele Mauri
  • Publication number: 20230068625
    Abstract: A semiconductor structure includes a first dielectric layer, a first conductive feature, a second conductive feature, a first etch stop layer, and a conductive via. The first conductive feature and the second conductive feature are embedded in the first dielectric layer. The first etch stop layer is disposed over the dielectric layer. The conductive via is surrounded by the first etch stop layer and electrically connected to the first conductive feature, in which the conductive via is in contact with a top surface of the first etch stop layer.
    Type: Application
    Filed: August 30, 2021
    Publication date: March 2, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wei-Ren WANG, Tze-Liang LEE, Jen-Hung WANG
  • Publication number: 20230069501
    Abstract: A method includes providing a first semiconductor layer at a frontside of a structure; implanting first dopants of a first conductivity-type into the first semiconductor layer, resulting in a doped layer in the first semiconductor layer; forming a stack of semiconductor layers over the first semiconductor layer; patterning the stack of semiconductor layers and the first semiconductor layer into fins; forming an isolation structure adjacent to a lower portion of the fins; etching the stack of semiconductor layers to form a source/drain trench over the first semiconductor layer; forming a source/drain feature in the source/drain trench, wherein the source/drain feature is doped with second dopants of a second conductivity-type opposite to the first conductivity-type; forming a contact hole at a backside of the structure, wherein the contact hole exposes the doped layer in the first semiconductor layer; and forming a first contact structure in the contact hole.
    Type: Application
    Filed: August 31, 2021
    Publication date: March 2, 2023
    Inventors: Chih Chieh Yeh, Ming-Shuan Li, Chih-Hung Wang, Zi-Ang Su
  • Publication number: 20230066893
    Abstract: Various embodiments of the present disclosure are directed towards a method for forming a semiconductor structure. The method includes loading a first wafer and a second wafer onto a bonding platform such that the second wafer overlies the first wafer. An alignment process is performed to align the second wafer over the first wafer by virtue of a plurality of wafer pins, where a plurality of first parameters are associated with the wafer pins during the alignment process. The second wafer is bonded to the first wafer. An overlay (OVL) measurement process is performed on the first wafer and the second wafer by virtue of the plurality of wafer pins, where a plurality of second parameters are associated with the wafer pins during the alignment process.
    Type: Application
    Filed: August 26, 2021
    Publication date: March 2, 2023
    Inventors: Ching-Hung Wang, Yeong-Jyh Lin, Ching I Li, Tzu-Wei Yu, Chung-Yi Yu
  • Patent number: 11594459
    Abstract: A semiconductor device includes an ultra-thick metal (UTM) structure. The semiconductor device includes a passivation layer including a first passivation oxide. The first passivation oxide includes an unbias film and a first bias film, where the unbias film is on portions of the UTM structure and on portions of a layer on which the UTM structure is formed, and the first bias film is on the unbias film. The passivation layer includes a second passivation oxide consisting of a second bias film, the second bias film being on the first bias film. The passivation layer includes a third passivation oxide consisting of a third bias film, the third bias film being on the second bias film.
    Type: Grant
    Filed: February 11, 2021
    Date of Patent: February 28, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Li Chun Liu, Chun Tang Wang, Chih Hung Wang, Ching Feng Lee, Yu-Lung Yeh
  • Patent number: 11594266
    Abstract: A semiconductor circuit and an operating method for the same are provided. The method includes the following steps. A memory circuit is operated during a first timing to obtain a first memory state signal S1. The memory circuit is operated during a second timing after the first timing to obtain a second memory state signal S2. A difference between the first memory state signal S1 and the second memory state signal S2 is calculated to obtain a state difference signal SD. A calculating is performed to obtain an un-compensated output data signal OD relative with an input data signal ID and the second memory state signal S2. The state difference signal SD and the un-compensated output data signal OD are calculated to obtain a compensated output data signal OD?.
    Type: Grant
    Filed: March 9, 2021
    Date of Patent: February 28, 2023
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Yu-Hsuan Lin, Chao-Hung Wang
  • Patent number: 11591822
    Abstract: A multi-key lock core includes a housing, a driving cylinder, a plurality of circular lock plates, and a lock rod. The driving cylinder is disposed in the housing, a sidewall of the driving cylinder is provided with a penetration portion, and the driving cylinder is rotatable to the penetration portion to correspond to an engagement recessed portion. The circular lock plates are disposed in the driving cylinder and each include an outer edge provided with a first recessed portion, and the outer edge of at least one of the circular lock plates is further provided with a second recessed portion. The lock rod is disposed in the penetration portion, and may partially enter the engagement recessed portion to restrict rotation of the driving cylinder. A first key may push the circular lock plates to rotate to the first recessed portion to correspond to the penetration portion, so that the lock rod can move to partially enter the first recessed portion and detach from the engagement recessed portion.
    Type: Grant
    Filed: November 9, 2020
    Date of Patent: February 28, 2023
    Assignee: SINOX CO., LTD.
    Inventor: Chia-Hung Wang
  • Publication number: 20230057060
    Abstract: The present invention provides a test component extraction module having a first arm, a second arm, and a base. The second arm is connected to the first arm. The base is connected to the second arm and has a suction hole for holding a test component. Wherein a first angle is predetermined between the first arm and the second arm. When the suction hole sucks the test component attached to a surface, and the first arm gradually moves away from the surface, a second angle is between the second arm and the first arm, and the second angle is greater than the first angle.
    Type: Application
    Filed: August 12, 2022
    Publication date: February 23, 2023
    Inventors: Sheng-Hung WANG, Po-Hsiang CHANG, Mei-Cheng LAI
  • Publication number: 20230056613
    Abstract: A simulation test system and a simulation test method are provided. The simulation test system includes a control device, a power setting device, and a data capture device. The control device generates a context control signal corresponding to one of a plurality of operating contexts. The power setting device generates at least one of a simulated charging power and a simulated load in response to the context control signal and provides at least one of the simulated charging power and the simulated load to a device under test to configure the device under test to generate test data in response to at least one of the simulated charging power and the simulated load. The data capture device captures the test data and provides the test data to the control device.
    Type: Application
    Filed: August 15, 2022
    Publication date: February 23, 2023
    Applicant: COMPAL ELECTRONICS, INC.
    Inventors: Chien-Lee Liu, Wen-Hua Kao, Tzu-Chiang Mi, Wei-Chih Shih, Hsun-Hung Wang, Hao-Jung Chiou, Yi-Hsun Lin
  • Patent number: 11586328
    Abstract: A circuit board includes multiple of first touch sensing electrodes, multiple of second touch sensing electrodes, and multiple of dummy patterns. The first touch sensing electrodes extend along a first direction. The second touch sensing electrodes extend along a second direction. The first touch sensing electrodes are electrically insulated from the second touch sensing electrodes. The first direction is not parallel to the second direction. The dummy patterns are positioned on the areas between the first touch sensing electrodes and the second touch sensing electrodes. The first touch sensing electrodes, the second touch sensing electrodes, and the dummy electrodes are non-transparent.
    Type: Grant
    Filed: February 11, 2022
    Date of Patent: February 21, 2023
    Assignee: TPK Touch Solutions (Xiamen) Inc.
    Inventors: Ming-Chuan Lin, Wen-Hung Wang, Chuan-Chih Fu
  • Patent number: 11582553
    Abstract: An electronic module is provided. The electronic module includes a first transducer and a second transducer. The first transducer is configured to radiate a first ultrasonic wave. The second transducer is configured to radiate a second ultrasonic wave. The first transducer and the second transducer are disposed on noncoplanar surfaces.
    Type: Grant
    Filed: April 27, 2021
    Date of Patent: February 14, 2023
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chih Lung Lin, Kuei-Hao Tseng, Kai Hung Wang
  • Patent number: 11577489
    Abstract: A label sticker includes a release layer strip, an attachment layer strip and a label layer strip. The attachment layer strip is made of an artificial dressing material and its lower surface is coated with or adhered to a first glue layer. The lower surface of the attachment layer strip is attached to the upper surface of the release layer strip through the first glue layer. The label layer strip is made of a waterproof material and its lower surface is coated with or adhered to a second glue layer. The lower surface of the label layer strip is attached to the upper surface of the attachment layer strip through the second glue layer. The label sticker, to be adhered to the human skin to serve identification purposes, can be manufactured by mass production but is unlikely to be wetted and smeared.
    Type: Grant
    Filed: October 29, 2020
    Date of Patent: February 14, 2023
    Assignees: MEGA PRECISION PRINTING CO., LTD
    Inventor: Chih-Hung Wang
  • Publication number: 20230039900
    Abstract: The invention provides a method for realizing a multi-channel convolutional recurrent neural network EEG emotion recognition model using transfer learning, the method uses a dual-channel one-dimensional convolutional neural network model constructed based on three heartbeats recognition method as the source domain model for transferring, to obtain a multi-channel convolutional recurrent neural network EEG emotion recognition model with EEG signal as the target domain, it solves the problem of scarcity of EEG labeling data, and can improve the accuracy of EEG emotion prediction.
    Type: Application
    Filed: March 29, 2022
    Publication date: February 9, 2023
    Applicant: FUZHOU UNIVERSITY
    Inventors: Liang-Hung Wang, I-chun Kuo
  • Publication number: 20230029951
    Abstract: An electronic device performance adjustment system and an electronic device performance adjustment method are provided. The electronic device performance adjustment system includes an electronic device, a power supply, and a battery. The electronic device is configured to have multiple operation powers. The power supply is coupled to the electronic device. The power supply is configured to provide a supply current to the electronic device. The battery is coupled to the electronic device and the power supply. The battery is configured to provide a battery current to the electronic device. The power supply is configured to charge the battery. The battery has a battery level. The electronic device further includes a controller coupled to the battery. The controller is configured to determine whether to adjust the operation power of the electronic device according to a change in the battery level.
    Type: Application
    Filed: June 2, 2022
    Publication date: February 2, 2023
    Applicant: PEGATRON CORPORATION
    Inventors: Kai-Hsuan Wang, Ming-Che Lee, Kai-Hung Wang
  • Publication number: 20230030770
    Abstract: A driving circuit includes at least one light-emitting element, a drive line, a data line, a touch sensor, and a read line. The drive line is electrically coupled to a first terminal of the at least one light-emitting element. The data line is electrically coupled to a second terminal of the at least one light-emitting element. The drive line is electrically coupled to a first terminal of the touch sensor. The read line is electrically coupled to a second terminal of the touch sensor. The read line is electrically isolated from the data line.
    Type: Application
    Filed: July 29, 2021
    Publication date: February 2, 2023
    Inventors: Ming-Chuan Lin, Wen-Hung Wang, Chuan-Chih Fu