Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a fin disposed in a first region of the semiconductor device, channel members disposed in a second region of the semiconductor device and stacked in a vertical direction, first and second metal gates disposed on a top surface of the fin, a third metal gate wrapping around each of the channel members, a first implant region in the fin with a first conductivity type, and a second implant region in the fin with a second conductivity opposite the first conductivity type. The fin includes first and second type epitaxial layers alternatingly disposed in the vertical direction. The first and second type epitaxial layers have different material compositions. The first type epitaxial layers and the channel members have the same material composition.

Abstract: In one example, a keyboard housing may include a chassis, a plurality of keys exposed through a top surface of the chassis, and an input device assembly connected to the chassis. The input device assembly may include a flexible touch sensing component to receive a touch input and a support structure. The support structure may include a first portion and a second portion foldable onto the first portion. The first portion and the second portion may support the flexible touch sensing component.

Abstract: Electrostatic discharge (ESD) structures are provided. An ESD structure includes a semiconductor substrate, a first epitaxy region with a first type of conductivity over the semiconductor substrate, a second epitaxy region with a second type of conductivity over the semiconductor substrate, and a plurality of semiconductor layers. The semiconductor layers are stacked over the semiconductor substrate and between the first and second epitaxy regions. A first conductive feature is formed over the first epitaxy region and outside an oxide diffusion region. A second conductive feature is formed over the second epitaxy region and outside the oxide diffusion region. A third conductive feature is formed over the first epitaxy region and within the oxide diffusion region. A fourth conductive feature is formed over the second epitaxy region and within the oxide diffusion region. The oxide diffusion region is disposed between the first and second conductive features.

Abstract: A radar signal processing system with a self-interference cancelling function includes an analog front end (AFE) processor, an analog to digital converter (ADC), an adaptive interference canceller (AIC), and a digital to analog converter (DAC). The AFE processor receives an original input signal and generates an analog input signal. The ADC converts the analog input signal to a digital input signal. The AIC generates a digital interference signal digital interference signal by performing an adaptive interference cancellation process according to the digital input signal. The DAC converts the digital interference signal to an analog interference signal. Finally, the analog interference signal is fed back to the AFE and cancelled from the original input signal in the AFE processor while performing the front end process, reducing the interference of the static interference from the leaking of a close-by transmitter during the front end process.

Abstract: Disclosed is a method for forming a crystalline protective polysilicon layer which does not create defective voids during subsequent processes so as to provide effective protection to devices underneath. In one embodiment, a method for forming a semiconductor device, includes: depositing a protective coating on a first polysilicon layer; forming an epitaxial layer on the protective coating; and depositing a second polysilicon layer over the epitaxial layer, wherein the protective coating comprises a third polysilicon layer, wherein the third polysilicon layer is deposited at a first temperature in a range of 600-700 degree Celsius, and wherein the third polysilicon layer in the protect coating is configured to protect the first polysilicon layer when the second polysilicon layer is etched.

Abstract: A keyboard and a key structure capable of displaying instant image thereof are provided. The key structure includes a display unit, a circuit membrane, an elastic member, a key seat, a first supporting frame, a second supporting frame, and a translucent keycap. The first supporting frame has two first arms and two axle portions. The ends of the first arms are slidably disposed on an accommodation portion of the key seat. The second supporting frame has two second arms and two linking holes. The ends of the second arms are pivotally connected to the accommodation portion. The linking hole is elongated-shaped. When the translucent keycap is not pressed, the axle portion abuts against one hole-end of the linking hole. When the translucent keycap is pressed, the axle portion abuts against another one hole-end of the linking hole.

Abstract: A security lock has a fixing element and at least one hook. The fixing element is mounted in a security slot of an electronic device. The hook is capable of moving axially with respect to the fixing element, and the hook moves radially outward along a guiding structure of the fixing element to engage with the security slot, the fixing element stays static, i.e., without moving and rotating as the hook is moving. Therefore, the security lock won't press the security slot, and further prevents damage to the security slot caused by frequently or constantly loaded with the security lock. Furthermore, without moving and rotating in a mounting process of the security lock, the fixing element holds the hook to steadily engage with the security slot, and thus an overall anti-pulling and anti-pushing performances are enhanced.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first diffusion barrier layer made of a dielectric material including a metal element, nitrogen, and oxygen and a first protection layer made of a dielectric material including silicon and oxygen and in direct contact with the top surface of the first diffusion barrier layer. The semiconductor device structure also includes a first thickening layer made of a dielectric material including the metal element and oxygen and in direct contact with the top surface of the first protection layer. A maximum metal content in the first thickening layer is greater than that in the first diffusion barrier layer. The semiconductor device structure further includes a conductive feature surrounded by and in direct contact with the first diffusion barrier layer, the first protection layer, and the first thickening layer.

Abstract: The present disclosure generally relates to a dual free layer (DFL) read head and methods of forming thereof. In one embodiment, a method of forming a DFL read head comprises depositing a DFL sensor, defining a stripe height of the DFL sensor, depositing a rear bias (RB) adjacent to the DFL sensor, defining a track width of the DFL sensor and the RB, and depositing synthetic antiferromagnetic (SAF) soft bias (SB) side shields adjacent to the DFL sensor. In another embodiment, a method of forming a DFL read head comprises depositing a DFL sensor, defining a track width of the DFL sensor, depositing SAF SB side shields adjacent to the DFL sensor, defining a stripe height of the DFL sensor and the SAF SB side shield, depositing a RB adjacent to the DFL sensor and the SAF SB side shield, and defining a track width of the RB.

Abstract: Various embodiments of the present disclosure are directed towards a semiconductor processing system including an overlay (OVL) shift measurement device. The OVL shift measurement device is configured to determine an OVL shift between a first wafer and a second wafer, where the second wafer overlies the first wafer. A photolithography device is configured to perform one or more photolithography processes on the second wafer. A controller is configured to perform an alignment process on the photolithography device according to the determined OVL shift. The photolithography device performs the one or more photolithography processes based on the OVL shift.

Abstract: A semiconductor memory device includes a substrate, and a plurality of contact pads and a capacitor array structure disposed on an array region of the substrate. The capacitor array structure includes a plurality of capacitors respectively disposed on the contact pads and a middle supporting layer extending laterally between waist portions of the capacitors to define an upper portion and a lower portion of each of the capacitors. The lower portions of the capacitors near the edge of the array region are tilted. The upper portions of the capacitors near the edge of the array region have misalignments to the contact pads. The stress in the capacitor array structure of the semiconductor memory device may be reduced.

Abstract: In an embodiment, a method includes forming a first conductive feature in a first inter-metal dielectric (IMD) layer; depositing a blocking film over and physically contacting the first conductive feature; depositing a first dielectric layer over and physically contacting the first IMD layer; depositing a second dielectric layer over and physically contacting the first dielectric layer; removing the blocking film; depositing an etch stop layer over any physically contacting the first conductive feature and the second dielectric layer; forming a second IMD layer over the etch stop layer; etching an opening in the second IMD layer and the etch stop layer to expose the first conductive feature; and forming a second conductive feature in the opening.

Abstract: A recess etching solution for recess etching a metal wiring in a semiconductor substrate manufacturing process; and a recess etching method employing the same. The recess etching solution is for applying recess etching to a surface of a cobalt-containing metal layer embedded in a via or a trench formed in a semiconductor substrate, and contains (A) an organic acid, one of or both of (B) a nitrogen-containing heterocyclic compound and (C) an organic solvent, and (D) water. The recess etching method includes applying recess etching to a surface of a cobalt-containing metal layer by bringing the recess etching solution into contact with the surface of the cobalt-containing metal layer embedded in a via or a trench formed in a semiconductor substrate.

Abstract: A structure for protecting an electronic component from coolant leaking from a liquid cooling system is disclosed. The liquid cooling system has a manifold collecting and supplying coolant to a cold plate via inlet and outlet tubes. The cold plate is mounted over a heat-generating component on a circuit board. The structure includes a drip tray having a top surface and a length approximately the distance between the manifold and the cold plate. The drip tray includes a trough for collection of leaking coolant. The tray is inserted between the circuit board and the inlet and outlet tubes.

Abstract: A performing device of an impulse-like gesture recognition system executes an impulse-like gesture recognition method. A performing procedure of the impulse-like gesture recognition method includes steps of: receiving a sensing signal from a sensing unit; determining a prediction with at least one impulse-like label according to the sensing frames by a deep learning-based model; and classifying at least one gesture event according to the prediction. The gesture event is classified to determine the motion of the user. Since the at least one impulse-like label is used to label at least one detection score of the deep learning-based model, the detection score is non-decreasing, reaction time of the at least one gesture event for an incoming gesture is fast, rapid consecutive gestures are easily decomposed, and an expensive post-processing is not needed.

Abstract: Structures and methods for trench isolation are disclosed. In one example, a silicon-on-insulator (SOI) structure is disclosed. The SOI structure includes: a substrate, a dielectric layer and a polysilicon region. The substrate includes: a handle layer, an insulation layer arranged over the handle layer, a buried layer arranged over the insulation layer, and a trench extending downward from an upper surface of the buried layer and terminating in the handle layer. The dielectric layer is located on a bottom surface of the trench and contacting the handle layer. The polysilicon region is located in the trench and contacting the dielectric layer.

Abstract: One or more computing devices, systems, and/or methods are provided. In an example, a first performance metric score may be determined based upon first content item text. A plurality of similarity scores associated with a plurality of sets of content item text may be determined. One or more sets of content item text may be selected from among the plurality of sets of content item text based upon the plurality of similarity scores and a plurality of performance metric scores associated with the plurality of sets of content item text. The plurality of performance metric scores may comprise one or more performance metric scores associated with the one or more sets of content item text. The one or more performance metric scores may be higher than the first performance metric score. One or more representations of the one or more sets of content item text may be displayed.

Abstract: A loop antenna which has a signal input/output wire, a first conductor, an upper conductor, an upper conductor, a second conductor, a first lower conductor, and a second lower conductor sequentially connected. The loop antenna further has a first grounding via, and a lower end of the first grounding via is connected to a first grounding layer, and an upper end of the first grounding via is disposed between and connecting the first lower conductor and the second lower conductor, wherein a first end of the second lower conductor is connected to the upper end of the first grounding via, and a second end of the second lower conductor is connected to the first conductor. A second grounding layer and the combination of the signal input/output wire, the first lower conductor, and the second lower conductor are disposed on the same layer disconnectedly.

Abstract: A method for extracting heat includes: during a first period: opening a first passage between a first chamber and a third chamber to compress gas in the third chamber; and opening a second passage between a second chamber and a fourth chamber to decompress gas in the fourth chamber. The method further includes during a second period following the first period: closing the first passage and the second passage; enabling a gas flow into the first chamber, the gas flow comprising gas having a first temperature; and outputting gas having a temperature that is lower than the first temperature of the gas in the second chamber.