Patents by Inventor Hung Wang

Hung Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240014290
    Abstract: A semiconductor structure includes a first semiconductor layer having an upper portion over a lower portion, a source/drain feature over the upper portion of the first semiconductor layer, a first contact structure under the lower portion of the first semiconductor layer and electrically connected to the lower portion of the first semiconductor layer. The lower portion is more heavily doped with first dopants than the upper portion. The first dopants are of a first conductivity-type. The source/drain feature includes second dopants of a second conductivity-type opposite to the first conductivity-type.
    Type: Application
    Filed: August 9, 2023
    Publication date: January 11, 2024
    Inventors: Chih Chieh Yeh, Ming-Shuan Li, Chih-Hung Wang, Zi-Ang Su
  • Publication number: 20240009790
    Abstract: A method includes steps of: performing preparation-phase measurements on a spindle of a machine tool to generate normal-condition signals; establishing a reference model based on the normal-condition signals; generating abnormal-condition signals based on the reference model and a preset damage value; utilizing principal components analysis (PCA) to characterize the normal-condition and abnormal-condition signals to obtain normal and abnormal probabilistic models, determining normal-condition and abnormal-condition reference curves based on the normal and abnormal probabilistic models; determining an alert-triggering line based on the abnormal-condition reference curve; determining a permissible range between the alert-triggering line and the normal-condition reference curve; and generating a warning signal when it is determined that a detection value falls outside of the permissible range, wherein the detection value is obtained based on application-phase measurements performed on the spindle.
    Type: Application
    Filed: December 16, 2022
    Publication date: January 11, 2024
    Inventors: TZU-CHI CHAN, JYUN-DE LI, YI-FAN SU, XIAN-YOU SHAO, YI-HAO CHEN, SHINN-LIANG CHANG, I-HUNG WANG, SHAO-CHI WU
  • Patent number: 11853890
    Abstract: Provided is an operation method for a memory device, the memory device being used for implementing an Artificial Neural Network (ANN). The operation method includes: reading from the memory device a weight matrix of a current layer of a plurality of layers of the ANN to extract a plurality of neuro values; determining whether to perform calibration; when it is determined to perform calibration, recalculating and updating a mean value and a variance value of the neuro values; and performing batch normalization based on the mean value and the variance value of the neuro values.
    Type: Grant
    Filed: July 26, 2019
    Date of Patent: December 26, 2023
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Chao-Hung Wang, Yu-Hsuan Lin, Ming-Liang Wei, Dai-Ying Lee
  • Patent number: 11855365
    Abstract: A loop antenna which has a signal input/output wire, a first conductor, an upper conductor, an upper conductor, a second conductor, a first lower conductor, and a second lower conductor sequentially connected. The loop antenna further has a first grounding via, and a lower end of the first grounding via is connected to a first grounding layer, and an upper end of the first grounding via is disposed between and connecting the first lower conductor and the second lower conductor, wherein a first end of the second lower conductor is connected to the upper end of the first grounding via, and a second end of the second lower conductor is connected to the first conductor. A second grounding layer and the combination of the signal input/output wire, the first lower conductor, and the second lower conductor are disposed on the same layer disconnectedly.
    Type: Grant
    Filed: July 13, 2022
    Date of Patent: December 26, 2023
    Assignee: KaiKuTek Inc.
    Inventors: Chih-Feng Chang, Yi-Cheng Lin, Mike Chun-Hung Wang
  • Patent number: 11855073
    Abstract: Electrostatic discharge (ESD) structures are provided. An ESD structure includes a semiconductor substrate, a first epitaxy region with a first type of conductivity over the semiconductor substrate, a second epitaxy region with a second type of conductivity over the semiconductor substrate, and a plurality of first semiconductor layers and a plurality of second semiconductor layers. The first and second semiconductor layers are alternatingly stacked over the semiconductor substrate and between the first and second epitaxy regions. A first conductive feature is formed over the first epitaxy region and outside an oxide diffusion region. A second conductive feature is formed over the second epitaxy region and outside the oxide diffusion region. The oxide diffusion region is disposed between the first and second conductive features.
    Type: Grant
    Filed: September 30, 2022
    Date of Patent: December 26, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chun-Chia Hsu, Tung-Heng Hsieh, Yung-Feng Chang, Bao-Ru Young, Jam-Wem Lee, Chih-Hung Wang
  • Patent number: 11848231
    Abstract: A method for forming a semiconductor device structure is provided. The method includes successively forming a first multi-layer etch stop structure and an insulating layer over a first conductive feature. The insulating layer and the first multi-layer etch stop structure are successively etched to form an opening substantially aligned to the first conductive feature. A second conductive feature is formed in the opening. The formation of the first multi-layer etch stop structure and the second multi-layer etch stop structure includes forming a first metal-containing dielectric layer, forming a silicon-containing dielectric layer over the first metal-containing dielectric layer, and forming a second metal-containing dielectric layer over the silicon-containing dielectric layer. The second metal-containing dielectric layer has a material that is different from the material of the first metal-containing dielectric layer.
    Type: Grant
    Filed: March 16, 2022
    Date of Patent: December 19, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Po-Cheng Shih, Tze-Liang Lee, Jen-Hung Wang, Yu-Kai Lin, Su-Jen Sung
  • Patent number: 11837459
    Abstract: A method includes providing a first semiconductor layer at a frontside of a structure; implanting first dopants of a first conductivity-type into the first semiconductor layer, resulting in a doped layer in the first semiconductor layer; forming a stack of semiconductor layers over the first semiconductor layer; patterning the stack of semiconductor layers and the first semiconductor layer into fins; forming an isolation structure adjacent to a lower portion of the fins; etching the stack of semiconductor layers to form a source/drain trench over the first semiconductor layer; forming a source/drain feature in the source/drain trench, wherein the source/drain feature is doped with second dopants of a second conductivity-type opposite to the first conductivity-type; forming a contact hole at a backside of the structure, wherein the contact hole exposes the doped layer in the first semiconductor layer; and forming a first contact structure in the contact hole.
    Type: Grant
    Filed: August 31, 2021
    Date of Patent: December 5, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih Chieh Yeh, Ming-Shuan Li, Chih-Hung Wang, Zi-Ang Su
  • Publication number: 20230377966
    Abstract: In an embodiment, a method includes forming a first conductive feature in a first inter-metal dielectric (IMD) layer; depositing a blocking film over and physically contacting the first conductive feature; depositing a first dielectric layer over and physically contacting the first IMD layer; depositing a second dielectric layer over and physically contacting the first dielectric layer; removing the blocking film; depositing an etch stop layer over any physically contacting the first conductive feature and the second dielectric layer; forming a second IMD layer over the etch stop layer; etching an opening in the second IMD layer and the etch stop layer to expose the first conductive feature; and forming a second conductive feature in the opening.
    Type: Application
    Filed: August 4, 2023
    Publication date: November 23, 2023
    Inventors: Cai-Ling Wu, Hsiu-Wen Hsueh, Wei-Ren Wang, Po-Hsiang Huang, Chii-Ping Chen, Jen Hung Wang
  • Publication number: 20230378125
    Abstract: A bag is filled with liquid, instead of an airbag filled with gas, to deform a bottom wafer toward a top wafer during a wafer bonding process. As a result, the liquid is less susceptible to temperature changes, which reduces run-out variation across wafer bonding processes. Reducing run-out variation conserves wasted wafers by increasing yield and reducing a quantity of non-functioning devices that are produced. Additionally, in some implementations, the liquid may be pre-heated before the bag is filled with the liquid. As a result, the bottom wafer (and, to some extent, the top wafer) experiences some thermal deformation and less mechanical deformation, which further increases yield and reduces a quantity of non-functioning devices that are produced.
    Type: Application
    Filed: May 19, 2022
    Publication date: November 23, 2023
    Inventors: Tzu-Wei YU, Ching-Hung WANG, Yeong-Jyh LIN, Ching I LI
  • Publication number: 20230359280
    Abstract: A method of customizing a hand gesture provides a touch screen, a computing unit connected with the touch screen, and a hand gesture database connected with the computing unit, and the method includes the following steps: recording a hand gesture trajectory data input of an input hand gesture on the touch screen; converting the hand gesture trajectory data input into a 2D trajectory graph of the input hand gesture; the computing unit sequentially reads a 2D hand gesture reference graph from the hand gesture database, and correspondingly generates a 2D hand gesture reference graph set for the 2D hand gesture reference graph read, and then the computing unit compares the similarity between the 2D trajectory graph of the input hand gesture and each reference graph in the 2D hand gesture reference graph set to determine whether the input hand gesture is already in the hand gesture database.
    Type: Application
    Filed: May 9, 2022
    Publication date: November 9, 2023
    Inventors: MIKE CHUN-HUNG WANG, GUAN-SIAN WU, CHIEH WU, YU-FENG WU, WEI-CHI LI, TSUNG-MING TAI, WEN-JYI HWANG, SIMON ANDREAS, DELLA FITRAYANI BUDIONO, FANG LI, CHING-CHIN KUO
  • Patent number: 11804077
    Abstract: A generic gesture detecting method executed by a generic gesture detecting device includes steps of: receiving a current sensing signal from a sensing unit; generating a current image according to the current sensing signal; determining whether the current image is similar with a stored image stored in a memory unit; when the current image is similar with the stored image, detecting the current image and the stored image to be a gesture signal; when the current image is different from the stored image, storing the current image into the memory unit, and returning to the step of receiving a current sensing signal. Since the generic gesture detecting device can automatically detect the gesture signal, the user may not need to enable a detecting time period before implementing a command motion. Therefore, the user can make the command motion without enabling the detecting time period, and the convenience can be increased.
    Type: Grant
    Filed: April 1, 2021
    Date of Patent: October 31, 2023
    Assignee: KaiKuTek Inc.
    Inventors: Yu Feng Wu, Chieh Wu, Ling Ya Huang, Fang Li, Guan-Sian Wu, Wen-Yen Chou, Wen-Jyi Hwang, Chun-Hsuan Kuo, Mike Chun-Hung Wang
  • Publication number: 20230339027
    Abstract: A mini cutting bit includes a shank, a cutting part and a bit tip, wherein the cutting part has opposite ends connected to the shank and the bit tip. The bit tip and the cutting part are made of different materials, and the bit tip is harder than the cutting part.
    Type: Application
    Filed: March 30, 2023
    Publication date: October 26, 2023
    Inventors: SHINN LIANG CHANG, TZU CHI CHAN, MENG HUA LI, I HUNG WANG
  • Publication number: 20230339028
    Abstract: A mini cutting bit includes a shank and a cutting part. The cutting part has a first spiral portion and a second spiral portion parallelly and twistedly formed thereon. The cutting part further has two chip removal flutes between the first and the second spiral portions. The first spiral portion has a first chip breaking flute on a top thereof while the second spiral portion has a second chip breaking flute. Widths of the first and the second chip breaking flutes are smaller than that of the tops of the first and the second spiral portions respectively.
    Type: Application
    Filed: March 30, 2023
    Publication date: October 26, 2023
    Inventors: SHINN LIANG CHANG, TZU CHI CHAN, MENG HUA LI, I HUNG WANG
  • Publication number: 20230335436
    Abstract: A semiconductor device includes a first conductive feature, a first dielectric layer over the first conductive feature, a second conductive feature extending through the first dielectric layer, an air gap between the first dielectric layer and the second conductive feature, and an etch stop layer over the second conductive feature and the first dielectric layer. The etch stop layer covers the air gap, and the air gap extends above a bottommost surface of the etch stop layer.
    Type: Application
    Filed: April 14, 2022
    Publication date: October 19, 2023
    Inventors: Wei-Ren Wang, Jen Hung Wang, Tze-Liang Lee
  • Patent number: 11792565
    Abstract: An electronic module is provided. The electronic module includes a first transducer and a second transducer. The first transducer is configured to radiate a first ultrasonic wave. The second transducer is configured to radiate a second ultrasonic wave. A location of the first transducer is configured to be adjustable with respect to the second transducer.
    Type: Grant
    Filed: April 27, 2021
    Date of Patent: October 17, 2023
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chih Lung Lin, Kuei-Hao Tseng, Kai Hung Wang
  • Publication number: 20230328349
    Abstract: There is provided a bottom cover for being covered on an optical system. The bottom cover is attached in front of the optical engine. The bottom cover has a bottom surface for facing a working surface when the optical system is moving on the working surface, a first opening for emission light of the optical engine to go through and a second opening for reflected light from the working surface to go through. The bottom cover is further formed with guiding protrusions protruded out from the bottom surface toward the working surface and surrounding at least the second opening to guide soft materials on the working surface to away from the second opening.
    Type: Application
    Filed: June 16, 2023
    Publication date: October 12, 2023
    Inventors: Hung-Yu LAI, Yen-Hung WANG, Wen-Yen SU, Hui-Hsuan CHEN
  • Publication number: 20230324998
    Abstract: A temporal sequence alignment method includes the following steps: receiving gesture training data and gesture sample data; wherein the gesture training data includes multiple training frames and multiple training soft labels, and the gesture sample data includes multiple sample frames and multiple sample soft labels; compressing the training frames to generate a compressed training frame; compressing the sample frames to generate a compressed sample frame; calculating an alignment model of the compressed training frame and the compressed sample frame; aligning the sample soft labels to multiple aligned soft labels according to the alignment model; generating an aligned training data according to the gesture sample data and the aligned soft labels. The present invention uses the aforementioned steps to calibrate the sample soft labels of the gesture sample data, allowing a gesture recognition system to minimize time discrepancy for recognizing a gesture.
    Type: Application
    Filed: April 11, 2022
    Publication date: October 12, 2023
    Applicant: KaiKuTek Inc.
    Inventors: Hung-Ju WANG, Tsung-Ming TAI, Wen-Jyi HWANG, Chun-Hsuan KUO, Mike Chun-Hung WANG
  • Publication number: 20230311189
    Abstract: A method for chamfering the installation position of a water control valve of a faucet body, mainly using a punching machine to drive a processing punch to punch a first end or second end, where the processing punch is provided with a fillet corresponding to the hole of the first end or second end, which squeezes the burrs through the driving of the punching machine, allowing the surface of installation position of the water control valve to be even and smooth, achieving smooth rotation of the water control valve, and preventing the water stop rubber to be scratched by the burrs or sharp corners.
    Type: Application
    Filed: March 30, 2022
    Publication date: October 5, 2023
    Inventor: Hsiang-Hung WANG
  • Publication number: 20230306178
    Abstract: A routing method of a printed circuit board and an electronic device are disclosed. The routing method includes: obtaining design information which includes a plurality of element pins of at least one circuit element and a plurality of electrical pins on the printed circuit board; arranging a plurality of bus paths according to the design information, wherein each of the bus paths is adapted for arranging a plurality of wirings to connect the element pins and corresponding electrical pins; calculating a plurality of bus spacings, wherein each of the bus spacings is between one of the bus paths and adjacent one of the bus paths; adjusting the bus paths according to the bus spacings and a preset distance; and arranging the wirings in each of the adjusted bus paths according to the design information.
    Type: Application
    Filed: February 6, 2023
    Publication date: September 28, 2023
    Applicant: PEGATRON CORPORATION
    Inventors: Yung-Lin Hsieh, Chih-Hung Wang, Yi-Fang Kao
  • Patent number: 11769693
    Abstract: A semiconductor structure includes a conductive feature, a first metal-based etch-stop layer over the underlying structure, a metal-free etch-stop layer over the first metal-based etch-stop layer, a second metal-based etch-stop layer over the metal-free etch-stop layer, an interlayer dielectric layer over the second metal-based etch-stop layer, and an interconnect structure extending through the first metal-based etch-stop layer, metal-free etch-stop layer, and the second metal-based etch-stop layer, wherein a bottom portion of the conductive interconnect structure directly contacts the conductive feature. The first metal-based etch-stop layer may include a first metallic component having one of aluminum, tantalum, titanium, or hafnium, and the second metal-based etch-stop layer may include a second metallic component the same as or different from the first metallic component. The first metal-based etch-stop layer and the second metal-based etch-stop layer may both be free of silicon.
    Type: Grant
    Filed: May 10, 2021
    Date of Patent: September 26, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Szu-Ping Tung, Yu-Kai Lin, Jen Hung Wang, Shing-Chyang Pan