Patents by Inventor Hung-Wen Su

Hung-Wen Su has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method of forming self-alignment contact
    Patent number: 10163719
    Abstract: A method of fabricating a semiconductor device is disclosed. The method includes forming a first gate stack over a substrate. The first gate stack includes a gate electrode, a first hard mask (HM) disposed over the gate electrode, and sidewall spacers along sidewalls of the first gate stack. The method also includes forming a first dielectric layer over the first gate stack, forming a second HM over the first HM and top surfaces of sidewall spacers, forming a second dielectric layer over the second HM and the first dielectric layer and removing the second and first dielectric layers to form a trench to expose a portion of the substrate while the second HM is disposed over the first gate stack.
    Type: Grant
    Filed: December 15, 2015
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsiao-Ping Liu, Hung-Chang Hsu, Hung-Wen Su, Ming-Hsing Tsai, Rueijer Lin, Sheng-Hsuan Lin, Syun-Ming Jang, Ya-Lien Lee, Yen-Shou Kao
  • Multi-Layer Film Device and Method
    Publication number: 20180350993
    Abstract: A device, structure, and method are provided whereby an insert layer is utilized to provide additional support for weaker and softer dielectric layer. The insert layer may be applied between two weaker dielectric layers or the insert layer may be used with a single layer of dielectric material. Once formed, trenches and vias are formed within the composite layers, and the insert layer will help to provide support that will limit or eliminate undesired bending or other structural motions that could hamper subsequent process steps, such as filling the trenches and vias with conductive material.
    Type: Application
    Filed: July 27, 2018
    Publication date: December 6, 2018
    Inventors: Yao-Jen Chang, Chih-Chien Chi, Chen-Yuan Kao, Hung-Wen Su, Kai-Shiang Kuo, Po-Cheng Shih, Jun-Yi Ruan
  • Interconnect Structure and Method of Forming the Same
    Publication number: 20180337056
    Abstract: An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a conductive plug over a substrate; a conductive feature over the conductive plug, wherein the conductive feature has a first sidewall, a second sidewall facing the first sidewall, and a bottom surface; and a carbon-containing barrier layer having a first portion along the first sidewall of the conductive feature, a second portion along the second sidewall of the conductive feature, and a third portion along the bottom surface of the conductive feature.
    Type: Application
    Filed: July 31, 2018
    Publication date: November 22, 2018
    Inventors: Rueijer Lin, Ya-Lien Lee, Chun-Chieh Lin, Hung-Wen Su
  • Semiconductor device structure and method for forming the same
    Patent number: 10050116
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a gate stack, a spacer layer, and a dielectric layer over a substrate. The method includes removing a first portion of the dielectric layer to form a first hole in the dielectric layer. A second portion of the dielectric layer is under the first hole. The method includes forming a first protection layer over the gate stack and the spacer layer. The method includes forming a second protection layer over the first protection layer. The second protection layer includes a metal compound material, and the first protection layer and the second protection layer includes a same metal element. The method includes removing the second portion of the dielectric layer to form a through hole. The method includes forming a conductive contact structure in the through hole.
    Type: Grant
    Filed: October 17, 2017
    Date of Patent: August 14, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsiao-Ping Liu, Hung-Chang Hsu, Hung-Wen Su, Ming-Hsing Tsai, Rueijer Lin, Sheng-Hsuan Lin, Ya-Lien Lee, Yen-Shou Kao
  • Method of Forming an Interconnect Structure Having an Air Gap and Structure Thereof
    Publication number: 20180204801
    Abstract: A semiconductor device and method of manufacture are provided which utilize an air gap to help isolate conductive structures within a dielectric layer. A first etch stop layer is deposited over the conductive structures, and the first etch stop layer is patterned to expose corner portions of the conductive structures. A portion of the dielectric layer is removed to form an opening. A second etch stop layer is deposited to line the opening, wherein the second etch stop layer forms a stepped structure over the corner portions of the conductive structures. Dielectric material is then deposited into the opening such that an air gap is formed to isolate the conductive structures.
    Type: Application
    Filed: March 12, 2018
    Publication date: July 19, 2018
    Inventors: Szu-Ping Tung, Chih-Chien Chi, Hung-Wen Su
  • Device and Method for Reducing Contact Resistance of a Metal
    Publication number: 20180174898
    Abstract: A device comprises a semiconductor substrate; a dielectric layer deposited over the semiconductor substrate, the dielectric layer including a trench; and a structure in the trench. The structure includes a chemical vapor deposition (CVD) TaN layer formed on a side wall of the trench; a physical vapor deposition (PVD) Ta layer formed over the CVD TaN layer; and a metal-containing layer formed over the PVD Ta layer.
    Type: Application
    Filed: February 12, 2018
    Publication date: June 21, 2018
    Inventors: Ya-Lien Lee, Hung-Wen Su, Kuei-Pin Lee, Yu-Hung Lin, Yu-Min Chang
  • Semiconductor device
    Patent number: 9978681
    Abstract: Semiconductor devices and methods for forming the same in which damages to a low-k dielectric layer therein can be reduced or even prevented are provided. A semiconductor device is provided, comprising a substrate. A dielectric layer with at least one conductive feature therein overlies the substrate. An insulating cap layer overlies the top surface of the low-k dielectric layer adjacent to the conductive feature, wherein the insulating cap layer includes metal ions.
    Type: Grant
    Filed: August 27, 2015
    Date of Patent: May 22, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Hung-Wen Su, Shih-Wei Chou, Ming-Hsing Tsai
  • Mechanisms of forming damascene interconnect structures
    Patent number: 9953868
    Abstract: A method of forming a conductive structure includes forming a first opening and a second opening in a dielectric layer on a substrate, wherein the first opening is narrower than the second opening. The method further includes depositing a diffusion barrier layer to line the first opening and the second opening. The method further includes forming a metal layer over the diffusion barrier layer to fill at least portions of the first opening and the second opening, wherein a maximum thickness of the metal layer in the first opening is greater than a maximum thickness of the metal layer in the second opening.
    Type: Grant
    Filed: January 5, 2016
    Date of Patent: April 24, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chien-An Chen, Wen-Jiun Liu, Chun-Chieh Lin, Hung-Wen Su, Ming Hsing Tsai, Syun-Ming Jang
  • Method of forming an interconnect structure having an air gap and structure thereof
    Patent number: 9917058
    Abstract: A semiconductor device and method of manufacture are provided which utilize an air gap to help isolate conductive structures within a dielectric layer. A first etch stop layer is deposited over the conductive structures, and the first etch stop layer is patterned to expose corner portions of the conductive structures. A portion of the dielectric layer is removed to form an opening. A second etch stop layer is deposited to line the opening, wherein the second etch stop layer forms a stepped structure over the corner portions of the conductive structures. Dielectric material is then deposited into the opening such that an air gap is formed to isolate the conductive structures.
    Type: Grant
    Filed: November 14, 2016
    Date of Patent: March 13, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Szu-Ping Tung, Chih-Chien Chi, Hung-Wen Su
  • Device and method for reducing contact resistance of a metal
    Patent number: 9892963
    Abstract: A method of fabricating an integrated circuit includes depositing a cap layer on a substrate; depositing a dielectric layer on the cap layer; and forming a trench in the dielectric layer. The method further includes depositing a tantalum nitride (TaN) layer on a sidewall of the trench such that the TaN layer has a greater concentration of nitrogen than tantalum. The method further includes depositing a tantalum (Ta) layer on the TaN layer using physical vapor deposition (PVD); and depositing a metal layer over the Ta layer.
    Type: Grant
    Filed: October 9, 2015
    Date of Patent: February 13, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ya-Lien Lee, Hung-Wen Su, Kuei-Pin Lee, Yu-Hung Lin, Yu-Min Chang
  • Multi-Layer Film Device and Method
    Publication number: 20180040732
    Abstract: A device, structure, and method are provided whereby an insert layer is utilized to provide additional support for weaker and softer dielectric layer. The insert layer may be applied between two weaker dielectric layers or the insert layer may be used with a single layer of dielectric material. Once formed, trenches and vias are formed within the composite layers, and the insert layer will help to provide support that will limit or eliminate undesired bending or other structural motions that could hamper subsequent process steps, such as filling the trenches and vias with conductive material.
    Type: Application
    Filed: August 2, 2016
    Publication date: February 8, 2018
    Inventors: Yao-Jen Chang, Chih-Chien Chi, Chen-Yuan Kao, Hung-Wen Su, Kai-Shiang Kuo, Po-Cheng Shih, Jun-Yi Ruan
  • Semiconductor Device Structure and Method for Forming the Same
    Publication number: 20180040705
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a gate stack, a spacer layer, and a dielectric layer over a substrate. The method includes removing a first portion of the dielectric layer to form a first hole in the dielectric layer. A second portion of the dielectric layer is under the first hole. The method includes forming a first protection layer over the gate stack and the spacer layer. The method includes forming a second protection layer over the first protection layer. The second protection layer includes a metal compound material, and the first protection layer and the second protection layer includes a same metal element. The method includes removing the second portion of the dielectric layer to form a through hole. The method includes forming a conductive contact structure in the through hole.
    Type: Application
    Filed: October 17, 2017
    Publication date: February 8, 2018
    Inventors: Hsiao-Ping Liu, Hung-Chang Hsu, Hung-Wen Su, Ming-Hsing Tsai, Rueijer Lin, Sheng-Hsuan Lin, Ya-Lien Lee, Yen-Shou Kao
  • Physical vapor deposition system and physical vapor depositing method using the same
    Patent number: 9887073
    Abstract: A physical vapor deposition system includes a chamber, a cover plate, a pedestal, and a collimator. The cover plate is disposed on the chamber for holding a target. The pedestal is disposed in the chamber for supporting a wafer. The collimator is mounted between the cover plate and the pedestal. The collimator includes a plurality of sidewall sheets together forming a plurality of passages. At least one of the passages has an entrance and an exit opposite to the entrance. The entrance faces the cover plate, and the exit faces the pedestal. A thickness of one of the sidewall sheets at the entrance is thinner than a thickness of the sidewall sheet at the exit.
    Type: Grant
    Filed: February 13, 2015
    Date of Patent: February 6, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Chien Chi, Hung-Wen Su, Pei-Hsuan Lee
  • Semiconductor device structure and method for forming the same
    Patent number: 9818834
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a gate stack, a spacer layer, and a dielectric layer over a substrate. The method includes removing a first portion of the dielectric layer to form a first hole in the dielectric layer. A second portion of the dielectric layer is under the first hole. The method includes forming a first protection layer over the gate stack and the spacer layer. The method includes forming a second protection layer over the first protection layer. The second protection layer includes a metal compound material, and the first protection layer and the second protection layer includes a same metal element. The method includes removing the second portion of the dielectric layer to form a through hole. The method includes forming a conductive contact structure in the through hole.
    Type: Grant
    Filed: January 7, 2016
    Date of Patent: November 14, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsiao-Ping Liu, Hung-Chang Hsu, Hung-Wen Su, Ming-Hsing Tsai, Rueijer Lin, Sheng-Hsuan Lin, Ya-Lien Lee, Yen-Shou Kao
  • Method of forming hybrid diffusion barrier layer and semiconductor device thereof
    Patent number: 9812397
    Abstract: In a method of fabricating a semiconductor device, an opening is formed inside a dielectric layer above a semiconductor substrate. The opening has a wall. At least one diffusion barrier material is then formed over the wall of the opening by at least two alternating steps, which are selected from the group consisting of a process of physical vapor deposition (PVD) and a process of atomic layer deposition (ALD). A liner layer is formed over the at least one diffusion barrier material.
    Type: Grant
    Filed: December 31, 2014
    Date of Patent: November 7, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kai-Shiang Kuo, Ken-Yu Chang, Ya-Lien Lee, Hung-Wen Su
  • Method of integration process for metal CMP
    Patent number: 9805951
    Abstract: A method of fabricating a semiconductor device is disclosed. The method includes forming a dielectric layer over a substrate. The substrate has an edge region and a center region. The method also includes forming a dielectric ring in the edge region, forming a metal layer over the center region of the substrate and over the dielectric ring in the edge region of the substrate and polishing the metal layer in the center region and the edge region to expose the dielectric ring in the edge region of the substrate.
    Type: Grant
    Filed: April 15, 2016
    Date of Patent: October 31, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Chien Chi, Pei-Hsuan Lee, Hung-Wen Su
  • Method of Integration Process for Metal CMP
    Publication number: 20170301557
    Abstract: A method of fabricating a semiconductor device is disclosed. The method includes forming a dielectric layer over a substrate. The substrate has an edge region and a center region. The method also includes forming a dielectric ring in the edge region, forming a metal layer over the center region of the substrate and over the dielectric ring in the edge region of the substrate and polishing the metal layer in the center region and the edge region to expose the dielectric ring in the edge region of the substrate.
    Type: Application
    Filed: April 15, 2016
    Publication date: October 19, 2017
    Inventors: Chih-Chien Chi, Pei-Hsuan Lee, Hung-Wen Su
  • Metal cap apparatus and method
    Patent number: 9786604
    Abstract: A method of forming a metal layer may include forming an opening in a substrate; forming a liner over sidewalls of the opening; filling the opening with a first metal; etching a top surface of the first metal to form a recessed top surface below a top surface of the substrate; and exposing the recessed top surface of the first metal to a solution, the solution containing a second metal different from the first metal, the exposing causing the recessed top surface of the first metal to attract the second metal to form a cap layer over the recessed top surface of the first metal.
    Type: Grant
    Filed: November 10, 2015
    Date of Patent: October 10, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Yuan Kao, Hung-Wen Su, Chih-Yi Chang, Liang-Yueh Ou Yang
  • Interconnect structure having air gap and method of forming the same
    Patent number: 9754882
    Abstract: A representative semiconductor device includes a first dielectric layer overlying a substrate, at least a first opening in the first dielectric layer, a conformal dense layer lining the at least first opening in the first dielectric layer, a barrier layer overlying the conformal dense layer, a conductive feature in the at least first opening, where a portion of the first dielectric layer between any two adjacent conductive features is removed to form a second opening, the second opening exposing the conformal dense layer between the two adjacent conductive features, and a second dielectric layer having an air gap formed therein, the second dielectric layer disposed between the two adjacent conductive features.
    Type: Grant
    Filed: May 17, 2016
    Date of Patent: September 5, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Chien Chi, Hung-Wen Su
  • SEMICONDUCTOR DEVICE STRUCTURE AND METHOD FOR FORMING THE SAME
    Publication number: 20170200800
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a gate stack, a spacer layer, and a dielectric layer over a substrate. The method includes removing a first portion of the dielectric layer to form a first hole in the dielectric layer. A second portion of the dielectric layer is under the first hole. The method includes forming a first protection layer over the gate stack and the spacer layer. The method includes forming a second protection layer over the first protection layer. The second protection layer includes a metal compound material, and the first protection layer and the second protection layer includes a same metal element. The method includes removing the second portion of the dielectric layer to form a through hole. The method includes forming a conductive contact structure in the through hole.
    Type: Application
    Filed: January 7, 2016
    Publication date: July 13, 2017
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsiao-Ping LIU, Hung-Chang HSU, Hung-Wen SU, Ming-Hsing TSAI, Rueijer LIN, Sheng-Hsuan LIN, Ya-Lien LEE, Yen-Shou KAO