Abstract: A hot spot defect detecting method and a hot spot defect detecting system are provided. In the method, hot spots are extracted from a design of a semiconductor product to define a hot spot map comprising hot spot groups, wherein local patterns in a same context of the design yielding a same image content are defined as a same hot spot group. During runtime, defect images obtained by an inspection tool performing hot scans on a wafer manufactured with the design are acquired and the hot spot map is aligned to each defect image to locate the hot spot groups. The hot spot defects in each defect image are detected by dynamically mapping the hot spot groups located in each defect image to a plurality of threshold regions and respectively performing automatic thresholding on pixel values of the hot spots of each hot spot group in the corresponding threshold region.

Abstract: A microelectromechanical system (MEMS) structure and method of forming the MEMS device, including forming a first metallization structure over a complementary metal-oxide-semiconductor (CMOS) wafer, where the first metallization structure includes a first sacrificial oxide layer and a first metal contact pad. A second metallization structure is formed over a MEMS wafer, where the second metallization structure includes a second sacrificial oxide layer and a second metal contact pad. The first metallization structure and second metallization structure are then bonded together. After the first metallization structure and second metallization structure are bonded together, patterning and etching the MEMS wafer to form a MEMS element over the second sacrificial oxide layer. After the MEMS element is formed, removing the first sacrificial oxide layer and second sacrificial oxide layer to allow the MEMS element to move freely about an axis.

Abstract: Provided herein are methods, systems, kits, and compositions useful for determining small molecule-protein interactions and protein-protein interactions. The photo-click tags provided herein can be conjugated to a small molecule or amino acid analog to provide compounds that can be integrated into a protein through photo-conjugation, allowing for identification of a small molecule-protein interaction or protein-protein interaction to elucidate the small molecules mechanism of action or the protein targeted by the small molecule. In some embodiments, the photo-click tags comprise a photo-conjugation moiety and a click chemistry handle, allowing for the attachment of various functional groups (e.g., affinity tags) to the small molecule or amino acid analog.

Abstract: A method for fabricating a semiconductor device includes the steps of forming a magnetic tunneling junction (MTJ) on a substrate, forming a spin orbit torque (SOT) layer on the MTJ, forming an inter-metal dielectric (IMD) layer around the MTJ and the SOT layer, forming a first hard mask on the IMD layer, forming a semiconductor layer on the first hard mask, and then patterning the first hard mask.

Abstract: A method to design and assemble a connector for the transition between a coaxial cable and a microstrip line involves in connecting a coaxial connector in series with a metallic ring to form a new coaxial connector, wherein the thickness of the metallic ring and the diameter of its through hole are important design parameters to determine the frequency response of the transition. By properly selecting their values and connecting the new coaxial connector to the microstrip line, a resonant response caused by the excitation of the first higher-order mode of the original coaxial connector is attenuated or eliminated from the frequency response.

Abstract: Provided herein are methods, systems, kits, and compositions useful for determining small molecule-protein interactions and protein-protein interactions. The photo-click tags provided herein can be conjugated to a small molecule or amino acid analog to provide compounds that can be integrated into a protein through photo-conjugation, allowing for identification of a small molecule-protein interaction or protein-protein interaction to elucidate the small molecules mechanism of action or the protein targeted by the small molecule. In some embodiments, the photo-click tags comprise a photo-conjugation moiety and a click chemistry handle, allowing for the attachment of various functional groups (e.g., affinity tags) to the small molecule or amino acid analog.

Abstract: A semiconductor structure having a metal gate includes a dielectric layer. The dielectric layer having a recess is disposed on a substrate, wherein the dielectric layer has a top part and a bottom part, and the tensile stress of the top part is larger than the tensile stress of the bottom part, thereby the recess having a sidewall profile tapering from bottom to top. The present invention also provides a method of forming said semiconductor structure.

Abstract: A method to design and assemble a connector for the transition between a coaxial cable and a microstrip line involves in connecting a coaxial connector in series with a metallic ring to form a new coaxial connector, wherein the thickness of the metallic ring and the diameter of its through hole are important design parameters to determine the frequency response of the transition. By properly selecting their values and connecting the new coaxial connector to the microstrip line, a resonant response caused by the excitation of the first higher-order mode of the original coaxial connector can be attenuated or even eliminated from the frequency response. Thus, the method improves the insertion loss of the transition at high frequencies, and increases its 1-dB passband. Note that the signal line of the microstrip line is not inserted into the through hole of the metallic ring in the final assembly of the transition.

Abstract: A metal gate transistor includes a substrate, a metal gate on the substrate, and a source/drain region in the substrate adjacent to the metal gate. The metal gate includes a high-k dielectric layer, a bottom barrier metal (BBM) layer comprising TiSiN on the high-k dielectric layer, a TiN layer on the BBM layer, a TiAl layer between the BBM layer and the TiN layer, and a low resistance metal layer on the TiN layer.

Abstract: A metal gate transistor includes a substrate, a metal gate on the substrate, and a source/drain region in the substrate adjacent to the metal gate. The metal gate includes a high-k dielectric layer, a bottom barrier metal (BBM) layer comprising TiSiN on the high-k dielectric layer, a TiN layer on the BBM layer, a TiAl layer between the BBM layer and the TiN layer, and a low resistance metal layer on the TiN layer.

Abstract: A power system is disclosure. The power system includes a processor, a power supply device, and a power-managing module. The power supply device includes a converter and a controller, the converter has a main power output for outputting a main voltage and a standby power output for outputting a standby voltage, and the controller is electrically connected to the converter. The power-managing module is communicating with the electronic device and the power supply device and includes a switch and a power manager, the switch is electrically connected to the main power output and the electronic device, and the power manager is electrically connected to the electronic device, the switch, and the controller. When the electronic device is in a standby operation mode, the power manager makes the switch turn off to prevent to main voltage from conducting to the electronic device.

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having an interlayer dielectric (ILD) layer thereon; forming a first recess, a second recess, and a third recess in the ILD layer; forming a material layer on the ILD layer and in the first recess, the second recess, and the third recess; performing a first treatment on the material layer in the first recess; and performing a second treatment on the material layer in the first recess and second recess.

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having an interlayer dielectric (ILD) layer thereon; forming a first recess, a second recess, and a third recess in the ILD layer; forming a material layer on the ILD layer and in the first recess, the second recess, and the third recess; performing a first treatment on the material layer in the first recess; and performing a second treatment on the material layer in the first recess and second recess.

Abstract: A power system is disclosure. The power system includes a processor, a power supply device, and a power-managing module. The power supply device includes a converter and a controller, the converter has a main power output for outputting a main voltage and a standby power output for outputting a standby voltage, and the controller is electrically connected to the converter. The power-managing module is communicating with the electronic device and the power supply device and includes a switch and a power manager, the switch is electrically connected to the main power output and the electronic device, and the power manager is electrically connected to the electronic device, the switch, and the controller. When the electronic device is in a standby operation mode, the power manager makes the switch turn off to prevent to main voltage from conducting to the electronic device.

Abstract: A method for fabricating metal gate transistor is disclosed. The method includes the steps of: providing a substrate having a NMOS region and a PMOS region; forming a dummy gate on each of the NMOS region and the PMOS region respectively; removing the dummy gates from each of the NMOS region and the PMOS region; forming a n-type work function layer on the NMOS region and the PMOS region; removing the n-type work function layer in the PMOS region; forming a p-type work function layer on the NMOS region and the PMOS region; and depositing a low resistance metal layer on the p-type work function layer of the NMOS region and the PMOS region.

Abstract: A power supplying device is electrically connected to an alternating current (AC) power supplier and an electronic system. The power supplying device includes a rectifier, a power converter, a controller, a power manager, and a switch component. The power converter is electrically connected to the rectifier and includes a first electric power outputting terminal and a standby electric power outputting terminal. The standby electric power outputting terminal is electrically connected to the electronic system. The controller is electrically connected to the power converter. The power manager is electrically connected to the controller and the electronic system. The switch component is electrically connected to the first electric power outputting terminal, the power manager, and the electronic system. The switch component conducts or cuts-off an electric power outputted form the first electric power outputting terminal and transmitting to the electronic system according to controls of the power manager.

Abstract: A semiconductor structure and a manufacturing method thereof are disclosed. The semiconductor structure includes an isolation layer, a gate dielectric layer, a first work function metal, a first bottom barrier layer, a second work function metal, and a first top barrier layer. The isolation layer is formed on a substrate and has a first gate trench. The gate dielectric layer is formed in the first gate trench. The first work function metal is formed on the gate dielectric layer in the first gate trench. The first bottom barrier layer is formed on the first work function metal. The second work function metal is formed on the first bottom barrier layer. The first top barrier layer is formed on the second work function metal.

Abstract: A metal gate transistor is disclosed. The metal gate transistor includes a substrate, a metal gate on the substrate, and a source/drain region in the substrate. The metal gate further includes a high-k dielectric layer, a bottom barrier metal (BBM) layer on the high-k dielectric layer, a first work function layer on the BBM layer, a second work function layer between the BBM layer and the first work function layer, and a low resistance metal layer on the first work function layer. Preferably, the first work function layer includes a p-type work function layer and the second work function layer includes a n-type work function layer.

Abstract: A semiconductor structure and a manufacturing method thereof are disclosed. The semiconductor structure includes an isolation layer, a gate dielectric layer, a first work function metal, a first bottom barrier layer, a second work function metal, and a first top barrier layer. The isolation layer is formed on a substrate and has a first gate trench. The gate dielectric layer is formed in the first gate trench. The first work function metal is formed on the gate dielectric layer in the first gate trench. The first bottom barrier layer is formed on the first work function metal. The second work function metal is formed on the first bottom barrier layer. The first top barrier layer is formed on the second work function metal.

Abstract: An apparatus includes a server cabinet configured to receive a plurality of servers therein, and a single heat dissipation device mounted on the server cabinet and positioned outside of the plurality of servers. The heat dissipation device includes a plurality of fans, and each of the plurality of fans is configured to dissipate heat generated in the overall server cabinet.