Patents by Inventor Hung-Yi Wu

Hung-Yi Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210159611
    Abstract: An antenna structure including a first radiator and a second radiator is provided. The first radiator includes a first segment, a second segment, a third segment, and a fourth segment all bent to be connected in sequence, in which the first segment includes a feed-in terminal. The second radiator includes a fifth segment, and a sixth segment, a seventh segment, an eighth segment, and a ninth segment which are connected respectively to the fifth segment, in which the fifth segment is located beside the first radiator while a first slit is formed between the first radiator and the fifth segment of the second radiator, the sixth segment includes a ground terminal, and the first radiator and the second radiator are adapted to couple to form a first frequency band, a second frequency band, a third frequency band, and a fourth frequency band.
    Type: Application
    Filed: November 12, 2020
    Publication date: May 27, 2021
    Applicant: PEGATRON CORPORATION
    Inventors: Chien-Yi Wu, Hau Yuen Tan, I-Shu Lee, Hung-Ming Yu
  • Publication number: 20210118125
    Abstract: A hot spot defect detecting method and a hot spot defect detecting system are provided. In the method, hot spots are extracted from a design of a semiconductor product to define a hot spot map comprising hot spot groups, wherein local patterns in a same context of the design yielding a same image content are defined as a same hot spot group. During runtime, defect images obtained by an inspection tool performing hot scans on a wafer manufactured with the design are acquired and the hot spot map is aligned to each defect image to locate the hot spot groups. The hot spot defects in each defect image are detected by dynamically mapping the hot spot groups located in each defect image to a plurality of threshold regions and respectively performing automatic thresholding on pixel values of the hot spots of each hot spot group in the corresponding threshold region.
    Type: Application
    Filed: December 15, 2020
    Publication date: April 22, 2021
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Huei Chen, Pei-Chao Su, Xiaomeng Chen, Chan-Ming Chang, Shih-Yung Chen, Hung-Yi Chung, Kuang-Shing Chen, Li-Jou Lee, Yung-Cheng Lin, Wei-Chen Wu, Shih-Chang Wang, Chien-An Lin
  • Patent number: 10811756
    Abstract: A method to design and assemble a connector for the transition between a coaxial cable and a microstrip line involves in connecting a coaxial connector in series with a metallic ring to form a new coaxial connector, wherein the thickness of the metallic ring and the diameter of its through hole are important design parameters to determine the frequency response of the transition. By properly selecting their values and connecting the new coaxial connector to the microstrip line, a resonant response caused by the excitation of the first higher-order mode of the original coaxial connector is attenuated or eliminated from the frequency response.
    Type: Grant
    Filed: May 10, 2017
    Date of Patent: October 20, 2020
    Assignee: NATIONAL TAIPEI UNIVERSITY OF TECHNOLOGY
    Inventors: Eric S. Li, Hung-Yi Wu, Wen-Shuo Tsai
  • Publication number: 20200140388
    Abstract: Provided herein are methods, systems, kits, and compositions useful for determining small molecule-protein interactions and protein-protein interactions. The photo-click tags provided herein can be conjugated to a small molecule or amino acid analog to provide compounds that can be integrated into a protein through photo-conjugation, allowing for identification of a small molecule-protein interaction or protein-protein interaction to elucidate the small molecules mechanism of action or the protein targeted by the small molecule. In some embodiments, the photo-click tags comprise a photo-conjugation moiety and a click chemistry handle, allowing for the attachment of various functional groups (e.g., affinity tags) to the small molecule or amino acid analog.
    Type: Application
    Filed: June 6, 2018
    Publication date: May 7, 2020
    Applicant: President and Fellows of Harvard College
    Inventors: Christina M. Woo, Jinxu Gao, Yuka Amako, Chia Fu Chang, Zhi Lin, Hung-Yi Wu
  • Publication number: 20190371916
    Abstract: A semiconductor structure having a metal gate includes a dielectric layer. The dielectric layer having a recess is disposed on a substrate, wherein the dielectric layer has a top part and a bottom part, and the tensile stress of the top part is larger than the tensile stress of the bottom part, thereby the recess having a sidewall profile tapering from bottom to top. The present invention also provides a method of forming said semiconductor structure.
    Type: Application
    Filed: June 26, 2018
    Publication date: December 5, 2019
    Inventors: Jing-Yi Lin, Yi-Wen Chen, Hung-Yi Wu, Ping-Wei Huang, Shao-Wei Wang, Yueh-Chi Chuang, Hung-Jen Huang, Hao-Che Feng
  • Publication number: 20170352937
    Abstract: A method to design and assemble a connector for the transition between a coaxial cable and a microstrip line involves in connecting a coaxial connector in series with a metallic ring to form a new coaxial connector, wherein the thickness of the metallic ring and the diameter of its through hole are important design parameters to determine the frequency response of the transition. By properly selecting their values and connecting the new coaxial connector to the microstrip line, a resonant response caused by the excitation of the first higher-order mode of the original coaxial connector can be attenuated or even eliminated from the frequency response. Thus, the method improves the insertion loss of the transition at high frequencies, and increases its 1-dB passband. Note that the signal line of the microstrip line is not inserted into the through hole of the metallic ring in the final assembly of the transition.
    Type: Application
    Filed: May 10, 2017
    Publication date: December 7, 2017
    Applicant: NATIONAL TAIPEI UNIVERSITY OF TECHNOLOGY
    Inventors: Eric S. LI, Hung-Yi WU, Wen-Shuo TSAI
  • Patent number: 9825144
    Abstract: A metal gate transistor includes a substrate, a metal gate on the substrate, and a source/drain region in the substrate adjacent to the metal gate. The metal gate includes a high-k dielectric layer, a bottom barrier metal (BBM) layer comprising TiSiN on the high-k dielectric layer, a TiN layer on the BBM layer, a TiAl layer between the BBM layer and the TiN layer, and a low resistance metal layer on the TiN layer.
    Type: Grant
    Filed: July 10, 2017
    Date of Patent: November 21, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Shih-Fang Tzou, Chien-Ming Lai, Yi-Wen Chen, Hung-Yi Wu, Tong-Jyun Huang, Chien-Ting Lin, Chun-Hsien Lin
  • Publication number: 20170309722
    Abstract: A metal gate transistor includes a substrate, a metal gate on the substrate, and a source/drain region in the substrate adjacent to the metal gate. The metal gate includes a high-k dielectric layer, a bottom barrier metal (BBM) layer comprising TiSiN on the high-k dielectric layer, a TiN layer on the BBM layer, a TiAl layer between the BBM layer and the TiN layer, and a low resistance metal layer on the TiN layer.
    Type: Application
    Filed: July 10, 2017
    Publication date: October 26, 2017
    Inventors: Shih-Fang Tzou, Chien-Ming Lai, Yi-Wen Chen, Hung-Yi Wu, Tong-Jyun Huang, Chien-Ting Lin, Chun-Hsien Lin
  • Patent number: 9531285
    Abstract: A power system is disclosure. The power system includes a processor, a power supply device, and a power-managing module. The power supply device includes a converter and a controller, the converter has a main power output for outputting a main voltage and a standby power output for outputting a standby voltage, and the controller is electrically connected to the converter. The power-managing module is communicating with the electronic device and the power supply device and includes a switch and a power manager, the switch is electrically connected to the main power output and the electronic device, and the power manager is electrically connected to the electronic device, the switch, and the controller. When the electronic device is in a standby operation mode, the power manager makes the switch turn off to prevent to main voltage from conducting to the electronic device.
    Type: Grant
    Filed: December 15, 2015
    Date of Patent: December 27, 2016
    Assignee: CHICONY POWER TECHNOLOGY CO., LTD.
    Inventors: Yung-Hung Hsiao, Hao-Te Hsu, Hung-Yi Wu
  • Patent number: 9349822
    Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having an interlayer dielectric (ILD) layer thereon; forming a first recess, a second recess, and a third recess in the ILD layer; forming a material layer on the ILD layer and in the first recess, the second recess, and the third recess; performing a first treatment on the material layer in the first recess; and performing a second treatment on the material layer in the first recess and second recess.
    Type: Grant
    Filed: November 18, 2014
    Date of Patent: May 24, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Wei Yang, Yu-Feng Liu, Jian-Cun Ke, Chia-Fu Hsu, En-Chiuan Liou, Ssu-I Fu, Chi-Mao Hsu, Nien-Ting Ho, Yu-Ru Yang, Yu-Ping Wang, Chien-Ming Lai, Yi-Wen Chen, Yu-Ting Tseng, Ya-Huei Tsai, Chien-Chung Huang, Tsung-Yin Hsieh, Hung-Yi Wu
  • Publication number: 20160104786
    Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having an interlayer dielectric (ILD) layer thereon; forming a first recess, a second recess, and a third recess in the ILD layer; forming a material layer on the ILD layer and in the first recess, the second recess, and the third recess; performing a first treatment on the material layer in the first recess; and performing a second treatment on the material layer in the first recess and second recess.
    Type: Application
    Filed: November 18, 2014
    Publication date: April 14, 2016
    Inventors: Chih-Wei Yang, Yu-Feng Liu, Jian-Cun Ke, Chia-Fu Hsu, En-Chiuan Liou, Ssu-I Fu, Chi-Mao Hsu, Nien-Ting Ho, Yu-Ru Yang, Yu-Ping Wang, Chien-Ming Lai, Yi-Wen Chen, Yu-Ting Tseng, Ya-Huei Tsai, Chien-Chung Huang, Tsung-Yin Hsieh, Hung-Yi Wu
  • Publication number: 20160099637
    Abstract: A power system is disclosure. The power system includes a processor, a power supply device, and a power-managing module. The power supply device includes a converter and a controller, the converter has a main power output for outputting a main voltage and a standby power output for outputting a standby voltage, and the controller is electrically connected to the converter. The power-managing module is communicating with the electronic device and the power supply device and includes a switch and a power manager, the switch is electrically connected to the main power output and the electronic device, and the power manager is electrically connected to the electronic device, the switch, and the controller. When the electronic device is in a standby operation mode, the power manager makes the switch turn off to prevent to main voltage from conducting to the electronic device.
    Type: Application
    Filed: December 15, 2015
    Publication date: April 7, 2016
    Inventors: Yung-Hung HSIAO, Hao-Te HSU, Hung-Yi WU
  • Publication number: 20160035854
    Abstract: A method for fabricating metal gate transistor is disclosed. The method includes the steps of: providing a substrate having a NMOS region and a PMOS region; forming a dummy gate on each of the NMOS region and the PMOS region respectively; removing the dummy gates from each of the NMOS region and the PMOS region; forming a n-type work function layer on the NMOS region and the PMOS region; removing the n-type work function layer in the PMOS region; forming a p-type work function layer on the NMOS region and the PMOS region; and depositing a low resistance metal layer on the p-type work function layer of the NMOS region and the PMOS region.
    Type: Application
    Filed: October 13, 2015
    Publication date: February 4, 2016
    Inventors: Shih-Fang Tzou, Chien-Ming Lai, Yi-Wen Chen, Hung-Yi Wu, Tong-Jyun Huang, Chien-Ting Lin, Chun-Hsien Lin
  • Patent number: 9246396
    Abstract: A power supplying device is electrically connected to an alternating current (AC) power supplier and an electronic system. The power supplying device includes a rectifier, a power converter, a controller, a power manager, and a switch component. The power converter is electrically connected to the rectifier and includes a first electric power outputting terminal and a standby electric power outputting terminal. The standby electric power outputting terminal is electrically connected to the electronic system. The controller is electrically connected to the power converter. The power manager is electrically connected to the controller and the electronic system. The switch component is electrically connected to the first electric power outputting terminal, the power manager, and the electronic system. The switch component conducts or cuts-off an electric power outputted form the first electric power outputting terminal and transmitting to the electronic system according to controls of the power manager.
    Type: Grant
    Filed: August 6, 2013
    Date of Patent: January 26, 2016
    Assignee: CHICONY POWER TECHNOLOGY CO., LTD.
    Inventors: Yung-Hung Hsiao, Hao-Te Hsu, Hung-Yi Wu
  • Patent number: 9231071
    Abstract: A semiconductor structure and a manufacturing method thereof are disclosed. The semiconductor structure includes an isolation layer, a gate dielectric layer, a first work function metal, a first bottom barrier layer, a second work function metal, and a first top barrier layer. The isolation layer is formed on a substrate and has a first gate trench. The gate dielectric layer is formed in the first gate trench. The first work function metal is formed on the gate dielectric layer in the first gate trench. The first bottom barrier layer is formed on the first work function metal. The second work function metal is formed on the first bottom barrier layer. The first top barrier layer is formed on the second work function metal.
    Type: Grant
    Filed: February 24, 2014
    Date of Patent: January 5, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hung-Yi Wu, Chien-Ming Lai, Yi-Wen Chen
  • Patent number: 9196546
    Abstract: A metal gate transistor is disclosed. The metal gate transistor includes a substrate, a metal gate on the substrate, and a source/drain region in the substrate. The metal gate further includes a high-k dielectric layer, a bottom barrier metal (BBM) layer on the high-k dielectric layer, a first work function layer on the BBM layer, a second work function layer between the BBM layer and the first work function layer, and a low resistance metal layer on the first work function layer. Preferably, the first work function layer includes a p-type work function layer and the second work function layer includes a n-type work function layer.
    Type: Grant
    Filed: September 13, 2013
    Date of Patent: November 24, 2015
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Shih-Fang Tzou, Chien-Ming Lai, Yi-Wen Chen, Hung-Yi Wu, Tong-Jyun Huang, Chien-Ting Lin, Chun-Hsien Lin
  • Publication number: 20150243754
    Abstract: A semiconductor structure and a manufacturing method thereof are disclosed. The semiconductor structure includes an isolation layer, a gate dielectric layer, a first work function metal, a first bottom barrier layer, a second work function metal, and a first top barrier layer. The isolation layer is formed on a substrate and has a first gate trench. The gate dielectric layer is formed in the first gate trench. The first work function metal is formed on the gate dielectric layer in the first gate trench. The first bottom barrier layer is formed on the first work function metal. The second work function metal is formed on the first bottom barrier layer. The first top barrier layer is formed on the second work function metal.
    Type: Application
    Filed: February 24, 2014
    Publication date: August 27, 2015
    Applicant: United Microelectronics Corp.
    Inventors: Hung-Yi Wu, Chien-Ming Lai, Yi-Wen Chen
  • Patent number: 9049802
    Abstract: An apparatus includes a server cabinet configured to receive a plurality of servers therein, and a single heat dissipation device mounted on the server cabinet and positioned outside of the plurality of servers. The heat dissipation device includes a plurality of fans, and each of the plurality of fans is configured to dissipate heat generated in the overall server cabinet.
    Type: Grant
    Filed: November 13, 2012
    Date of Patent: June 2, 2015
    Assignees: HONG FU JIN PRECISION INDUSTRY (ShenZhen) CO., LTD., HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Shu-Ni Yi, Hung-Yi Wu
  • Publication number: 20150093933
    Abstract: A fixing device for fixing two connectors connected to each other includes two holding members and a connecting member connected between the holding members. Each holding member includes a connecting piece and two arms extending down from opposite ends of the connecting piece to sandwich one of the connectors.
    Type: Application
    Filed: October 18, 2013
    Publication date: April 2, 2015
    Applicants: HONG FU JIN PRECISION INDUSTRY (ShenZhen) CO. LTD., HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: AN-GANG LIANG, MING-YU LIU, HUNG-YI WU
  • Publication number: 20150076623
    Abstract: A method for fabricating metal gate transistor is disclosed. The method includes the steps of: providing a substrate having a NMOS region and a PMOS region; forming a dummy gate on each of the NMOS region and the PMOS region respectively; removing the dummy gates from each of the NMOS region and the PMOS region; forming a n-type work function layer on the NMOS region and the PMOS region; removing the n-type work function layer in the PMOS region; forming a p-type work function layer on the NMOS region and the PMOS region; and depositing a low resistance metal layer on the p-type work function layer of the NMOS region and the PMOS region.
    Type: Application
    Filed: September 13, 2013
    Publication date: March 19, 2015
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Shih-Fang Tzou, Chien-Ming Lai, Yi-Wen Chen, Hung-Yi Wu, Tong-Jyun Huang, Chien-Ting Lin, Chun-Hsien Lin