Patents by Inventor Hung Yu

Hung Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230387312
    Abstract: A method is provided for forming a semiconductor device. A fin feature is formed on a semiconductor substrate, and a dummy gate feature is formed over the fin feature. The fin feature includes a sacrificial portion disposed over the semiconductor substrate, and a fin portion disposed over the sacrificial portion. The dummy gate feature is connected to the fin feature and the semiconductor substrate. Then, the sacrificial portion is removed to form a gap between the semiconductor substrate and the fin portion. A dielectric isolation layer is formed to fill the gap for electrically isolating the fin portion from the semiconductor substrate. Subsequently, source/drain features are formed over the dielectric isolation layer, and the dummy gate feature is processed to form a gate electrode feature on the fin portion.
    Type: Application
    Filed: May 25, 2022
    Publication date: November 30, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hung-Yu YEN, Wei-Ting YEH, Ko-Feng CHEN, Keng-Chu LIN
  • Patent number: 11825916
    Abstract: Buffing of a footwear component allows for an alteration of the component surface to achieve an intended surface for aesthetics and/or manufacturing purposes. The buffing is performed in a system having a vision module, a sidewall buffing module, an up surface buffing module, and a down surface buffing module. Each of the buffing modules are adapted for the unique shape and sizes of a footwear component to effectively and automatically buff the footwear component.
    Type: Grant
    Filed: September 15, 2020
    Date of Patent: November 28, 2023
    Assignee: NIKE, Inc.
    Inventors: Chun-Chieh Chen, Yi-Min Chen, Chia-Hung Lin, Hsien-Kuang Wu, Hung-Yu Wu
  • Publication number: 20230378266
    Abstract: A device comprise a first semiconductor channel layer over a substrate, a second semiconductor channel layer over the first semiconductor channel layer, and source/drain epitaxial structures on opposite sides of the first semiconductor channel layer and opposite sides of the second semiconductor channel layer. A compressive strain in the second semiconductor channel layer is greater than a compressive strain in the first semiconductor channel layer. The source/drain epitaxial structures each comprise a first region interfacing the first semiconductor channel layer and a second region interfacing the second semiconductor channel layer, and the first region has a composition different from a composition of the second region.
    Type: Application
    Filed: July 31, 2023
    Publication date: November 23, 2023
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Chung-En TSAI, Chia-Che CHUNG, Chee-Wee LIU, Fang-Liang LU, Yu-Shiang HUANG, Hung-Yu YEH, Chien-Te TU, Yi-Chun LIU
  • Publication number: 20230378017
    Abstract: An embodiment is a device including a package component including an integrated circuit die and conductive connectors connected to the integrated circuit die, the conductive connectors disposed at a first side of the package component. The device also includes a metal layer on a second side of the package component, the second side being opposite the first side. The device also includes a thermal interface material on the metal layer. The device also includes a lid on the thermal interface material. The device also includes a retaining structure on sidewalls of the package component and the thermal interface material. The device also includes a package substrate connected to the conductive connectors, the lid being adhered to the package substrate.
    Type: Application
    Filed: August 19, 2022
    Publication date: November 23, 2023
    Inventors: Ping-Yin Hsieh, Pu Wang, Li-Hui Cheng, Ying-Ching Shih, Hung-Yu Chen
  • Patent number: 11819090
    Abstract: Buffing of a footwear component allows for an alteration of the component surface to achieve an intended surface for aesthetics and/or manufacturing purposes. The buffing is performed in a system having a vision module, a sidewall buffing module, an up surface buffing module, and a down surface buffing module. Each of the buffing modules are adapted for the unique shape and sizes of a footwear component to effectively and automatically buff the footwear component.
    Type: Grant
    Filed: September 15, 2020
    Date of Patent: November 21, 2023
    Assignee: NIKE, Inc.
    Inventors: Chun-Chieh Chen, Yi-Min Chen, Chia-Hung Lin, Hsien-Kuang Wu, Hung-Yu Wu
  • Patent number: 11812822
    Abstract: A size-adjustable sport shoe includes a shoe head, a shoe insole, and an adjusting telescopic device including a gear, a shaft gear, first and second gear racks, and handle. The first and second gear racks are located at two lateral sides of an elongated adjustment groove at the shoe head, wherein the upper surface of the second gear rack is lower than the upper surface of the first gear rack. The gear shaft is coupled between the gear and the handle. When the handle is folded perpendicularly to an axis direction of the gear shaft, the gear meshes with the first gear rack to lock up the shoe head at the shoe insole. When the handle is folded to coincide with the axis direction of the gear shaft, the gear meshes with the second gear rack to allow the shoe head to be slid from the shoe insole.
    Type: Grant
    Filed: January 4, 2021
    Date of Patent: November 14, 2023
    Assignee: TRI GOLD MANUFACTURE CO., LTD.
    Inventors: Ting-Hung Yu, Chuan-Hung Yu
  • Publication number: 20230359232
    Abstract: A multi-loop error amplifier circuit for generating an error amplification signal includes: a first operational transconductance amplifier (OTA) including a first current output stage which generates a first transconductance amplification current in a predetermined current direction according to a first voltage difference between a positive terminal and a negative input terminal of the first OTA; a second OTA including a second current output stage which generates a second transconductance amplification current in the predetermined current direction according to a second voltage difference between a positive terminal and a negative input terminal of the second OTA. The first and the second current output stages are coupled in series to generate a first error output current. The error amplification signal is generated according to the first error output current which is equal to the smaller one of the first and the second transconductance amplification currents.
    Type: Application
    Filed: April 13, 2023
    Publication date: November 9, 2023
    Inventors: Hung-Yu Cheng, Keng-Hong Chu, Li-Chen Cheng, Tsung-Han Yu
  • Patent number: 11812130
    Abstract: There is provided an optical engine for a navigation device including a first light source, a second light source, a lens, a barrier structure and an image sensor. The barrier structure has a first space for containing the first light source, a second space for containing the lens and a third space for containing the second light source and the image sensor. The reflected light associated with the first light source propagates to the image sensor via the lens in the second space. The reflected light associated with the second light source propagates to the image sensor via the third space without passing through the lens in the second space.
    Type: Grant
    Filed: January 18, 2023
    Date of Patent: November 7, 2023
    Assignee: PixArt Imaging Inc.
    Inventor: Hung-Yu Lai
  • Patent number: 11811328
    Abstract: An isolated conversion apparatus with magnetic bias balance control includes an isolated converter, a controller, and a magnetic bias balance circuit. The isolated converter includes a transformer, and a primary side of the transformer includes a primary-side winding and at least one switch bridge arm. The controller is coupled to the at least one switch bridge arm, and provides a pulse width modulation (PWM) signal group to control the at least one switch bridge arm. The magnetic bias balance circuit is coupled to two ends of the primary-side winding and the controller, and provides a compensation voltage to the controller according to an average voltage of a winding voltage across the two ends of the primary-side winding. The controller adjusts a duty cycle of the PWM signal group according to the compensation voltage to correct the magnetic bias.
    Type: Grant
    Filed: January 6, 2022
    Date of Patent: November 7, 2023
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Chih-Hsien Li, Yi-Ping Hsieh, Hung-Chieh Lin, Hung-Yu Huang, Ciao-Yin Pan
  • Patent number: 11801834
    Abstract: A vehicle positioning method via data fusion and a system using the same are disclosed. The method is performed in a processor electrically connected to a self-driving-vehicle controller and multiple electronic systems. The method is to perform a delay correction according to a first real-time coordinate, a second real-time coordinate, real-time lane recognition data, multiple vehicle dynamic parameters, and multiple vehicle information received from the multiple electronic systems with their weigh values, to generate a fusion positioning coordinate, and to determine confidence indexes. Then, the method is to output the first real-time coordinate, the second real-time coordinate, and the real-time lane recognition data that are processed by the delay correction, the fusion positioning coordinate, and the confidence indexes to the self-driving-vehicle controller for a self-driving operation.
    Type: Grant
    Filed: December 21, 2021
    Date of Patent: October 31, 2023
    Assignee: Automotive Research & Testing Center
    Inventors: Tong-Kai Jhang, Jin-Yan Hsu, You-Sian Lin, Ji-Fan Yang, Chien-Hung Yu, Yi-Zhao Chen
  • Publication number: 20230343592
    Abstract: A method of fabricating an amorphous carbon layer (ACL) mask includes forming an ACL on an underlying layer. The ACL includes a soft ACL portion that has a first hardness and a hard ACL portion that has a second hardness. The soft ACL portion underlies the hard ACL portion. The second hardness is greater than the first hardness. The method further includes forming a patterned layer over the ACL and forming an ACL mask by etching through both the soft ACL portion and the hard ACL portion of the ACL to expose the underlying layer using the patterned layer as an etch mask. Forming the ACL may include depositing one or both of the soft ACL portion and the hard ACL portion. Processing conditions may also be varied while forming the ACL to create a hardness gradient that transitions from softer to harder.
    Type: Application
    Filed: April 21, 2022
    Publication date: October 26, 2023
    Inventors: Shihsheng Chang, Andrew Metz, Yun Han, Ya-Ming Chen, Kai-Hung Yu, Eric Chih-Fang Liu
  • Publication number: 20230343598
    Abstract: Various embodiments of stacked structures, process steps and methods are provided herein for etching high aspect ratio features (e.g., contact holes, vias, trenches, etc.) within a stacked structure comprising a hard mask layer, which is formed above and in contact with one or more underlying layers. At least one etch stop layer (ESL) is provided within the hard mask layer to divide the hard mask layer into two or more distinct portions. When the stacked structure is subsequently etched to form high aspect ratio features within the hard mask layer, such as contact holes or vias that extend through the hard mask layer, the ESL(s) included within the hard mask layer improve etch rate and critical dimension (CD) uniformity of the features etched within the hard mask layer.
    Type: Application
    Filed: April 22, 2022
    Publication date: October 26, 2023
    Inventors: Shihsheng Chang, Andrew Metz, Yun Han, Minjoon Park, Kai-Hung Yu, Eric Chih-Fang Liu
  • Publication number: 20230337556
    Abstract: A resistive memory device is provided. The resistive memory device includes a first electrode, a memory structure on the first electrode, and a second electrode on the memory structure. The memory structure includes a tubular element and a pillar element. The tubular element includes oxide. The pillar element includes oxide. The pillar element is surrounded by the tubular element. The tubular element and the pillar element include different materials.
    Type: Application
    Filed: May 18, 2022
    Publication date: October 19, 2023
    Inventors: Shu-Hung YU, Chun-Hung CHENG, Chuan-Fu WANG
  • Publication number: 20230333080
    Abstract: A method of predicting fabric features is disclosed herein, and the method includes following operations. Inputting first fabric information of a first fabric. Generating first fabric feature values of the first fabric. Performing a first calculation on the first fabric information and the first fabric feature values. Generating feature parameters and first predicted feature values of the first fabric by the first calculation. Inputting second fabric information of a second fabric. Generating second fabric feature values of the second fabric according to the second fabric information and the feature parameters. A system of predicting fabric features is also disclosed herein.
    Type: Application
    Filed: April 29, 2022
    Publication date: October 19, 2023
    Inventors: Pei-Te SHEN, Hung-Yu LIN, Chin-Lun CHU, Yu-Sian CIOU, Tzu-Yu CHIU
  • Patent number: 11788661
    Abstract: A quick release coupling includes male and female connector assemblies releasably secured together. The male connector assembly includes two parallel male connectors and the female connector assembly includes two parallel female connectors. A sleeve assembly is releasably connected to one ends of the female connectors. A plunger assembly is provided in each of the sleeve assembly and female connector. A sleeving assembly is provided on each of the female connector and the sleeve assembly. The parallel female connectors can be disconnected from the parallel male connectors or connected together at the same time. After the female connectors have disengaged from the male connectors, leakproof arrangements in the female connector assembly act to prevent water in the female connector assembly from leaking.
    Type: Grant
    Filed: February 24, 2022
    Date of Patent: October 17, 2023
    Inventor: Hung-Yu Hsieh
  • Publication number: 20230328349
    Abstract: There is provided a bottom cover for being covered on an optical system. The bottom cover is attached in front of the optical engine. The bottom cover has a bottom surface for facing a working surface when the optical system is moving on the working surface, a first opening for emission light of the optical engine to go through and a second opening for reflected light from the working surface to go through. The bottom cover is further formed with guiding protrusions protruded out from the bottom surface toward the working surface and surrounding at least the second opening to guide soft materials on the working surface to away from the second opening.
    Type: Application
    Filed: June 16, 2023
    Publication date: October 12, 2023
    Inventors: Hung-Yu LAI, Yen-Hung WANG, Wen-Yen SU, Hui-Hsuan CHEN
  • Publication number: 20230317571
    Abstract: An electronic device with a conductive lead having an internal first section and an external second section extending outside a molded package structure, the first section having an obstruction feature extending vertically from a top or bottom side of the conductive lead and engaging a portion of the package structure to oppose movement of the conductive lead outward from the package structure.
    Type: Application
    Filed: March 30, 2022
    Publication date: October 5, 2023
    Inventors: Hsiang Ming Hsiao, Hung-Yu Chou, Yuh-Harng Chien, Chih-Chien Ho, Che Wei Tu, Bo-Hsun Pan, Megan Chang
  • Publication number: 20230317552
    Abstract: A method of forming a semiconductor structure includes: attaching a semiconductor device to a first surface of a substrate; placing a thermal interface material (TIM) film over a first side of the semiconductor device distal from the substrate, where the TIM film is pre-formed before the placing, where after the placing, a peripheral portion of the TIM film extends laterally beyond sidewalls of the semiconductor device; and attaching a lid to the first surface of the substrate to form an enclosed space between the lid and the substrate, where after attaching the lid, the semiconductor device and the TIM film are disposed in the enclosed space, where a first side of the TIM film distal from the substrate contacts the lid.
    Type: Application
    Filed: June 2, 2023
    Publication date: October 5, 2023
    Inventors: Chih-Hao Chen, Hung-Yu Chen, Pu Wang, Li-Hui Cheng, Szu-Wei Lu
  • Publication number: 20230310194
    Abstract: In one embodiment a knee brace includes a tubular cushioning body; two sheaths disposed at two opposite sides of the tubular cushioning body respectively; and two sets of a plurality of elastic strips inserted into the sheaths respectively. There are further provided two tubes with the sets of the plurality of elastic strips inserted thereinto respectively. The tubes are inserted into the sheaths respectively.
    Type: Application
    Filed: March 14, 2022
    Publication date: October 5, 2023
    Inventor: Hung-Yu HSIEH
  • Patent number: 11776998
    Abstract: A device comprises a plurality of nanosheets, source/drain stressors, and a gate structure wrapping around the nanosheets. The nanosheets extend in a first direction above a semiconductor substrate and are arranged in a second direction substantially perpendicular to the first direction. The source/drain stressors are on either side of the nanosheets. Each of the source/drain stressors comprises a first epitaxial layer and a second epitaxial layer over the first epitaxial layer. The first and second epitaxial layers are made of a Group IV element and a Group V element. An atomic ratio of the Group V element to the Group IV element in the second epitaxial layer is greater than an atomic ratio of the Group V element to the Group IV element in the first epitaxial layer.
    Type: Grant
    Filed: January 24, 2022
    Date of Patent: October 3, 2023
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Chung-En Tsai, Chia-Che Chung, Chee-Wee Liu, Fang-Liang Lu, Yu-Shiang Huang, Hung-Yu Yeh, Chien-Te Tu, Yi-Chun Liu