Abstract: An electronic device may include at least one communication processor and an application processor. The at least one communication processor is configured to: receive first system information including information on whether at least one node supporting first cellular communication supports DC or second system information including information on a node which is adjacent to the at least one node and supports second cellular communication, from the at least one node via the first cellular communication; update, based on the first or second system information, a database which includes information indicating whether the at least one node supports the DC and information indicating whether the node adjacent to the at least one node supports the second cellular communication; determine, based on the updated database, a searching order of at least one node included in the updated database; and search for a node to be registered, based on the determined searching order.

Abstract: A memory layout structure, which is provided with multiple source lines between active areas, each source line has multiple branches electrically connecting with the active areas at opposite sides in alternating arrangement. Multiple word lines traverse through the active areas to form transistors. Multiple storage units are disposed between the word lines on the active areas in staggered array arrangement, and multiple bit lines electrically connect with all storage units on a corresponding active area, wherein each storage cell includes one of the storage unit, two of the transistors respectively at both sides of the storage unit, and two branches of the source line.

Abstract: A semiconductor device includes a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate and a dummy MTJ between the first MTJ and the second MTJ, in which a bottom surface of the dummy MTJ is not connected to any metal. Preferably, the semiconductor device further includes a first metal interconnection under the first MTJ, a second metal interconnection under the second MTJ, and a first inter-metal dielectric (IMD) layer around the first metal interconnection and the second metal interconnection and directly under the dummy MTJ.

Abstract: A method of fabricating a semiconductor device includes the steps of: providing a semiconductor structure including a memory region and a logic region. The semiconductor structure includes a first interlayer dielectric and at least one magnetoresistive random access memory (MRAM) cell disposed on the first interlayer dielectric, and the MRAM cell is disposed in the memory region; depositing a second interlayer dielectric covering the first interlayer dielectric and the at least one MRAM cell; depositing a mask layer conformally covering the second interlayer dielectric; perform a planarization process to remove the mask layer in the memory region; after the step of performing the planarization process, removing the mask layer in the logic region.

Abstract: A method for fabricating semiconductor device includes the steps of: forming a substrate having a magnetic tunneling junction (MTJ) region and a logic region; forming a MTJ on the MTJ region; forming a top electrode on the MTJ; forming an inter-metal dielectric (IMD) layer around the MTJ; removing the IMD layer directly on the top electrode to form a recess; forming a first hard mask on the IMD layer and into the recess; removing the first hard mask and the IMD layer on the logic region to form a contact hole; and forming a metal layer in the recess and the contact hole to form a connecting structure on the top electrode and a metal interconnection on the logic region.

Abstract: A memory layout structure, which is provided with multiple source lines between active areas, each source line has multiple branches electrically connecting with the active areas at opposite sides in alternating arrangement. Multiple word lines traverse through the active areas to form transistors. Multiple storage units are disposed between the word lines on the active areas in staggered array arrangement, and multiple bit lines electrically connect with all storage units on a corresponding active area, wherein each storage cell includes one of the storage unit, two of the transistors respectively at both sides of the storage unit, and two branches of the source line.

Abstract: A magnetic memory cell includes a substrate, a transistor, a first dielectric layer disposed on the substrate, a landing pad in the first dielectric layer, a second dielectric layer covering the first dielectric layer and the landing pad, a memory stack in the second dielectric layer, and a source line in the first dielectric layer. The first dielectric layer covers the transistor. The landing pad is situated in a first horizontal plane and is coupled to a drain region of the transistor. The memory stack has a bottom electrode connected to the landing pad and a top electrode electrically connected to a bit line. The source line is situated in a second horizontal plane and is connected to a source region of the transistor. The second horizontal plane and the first horizontal plane are not coplanar.

Abstract: A magnetic memory cell includes a substrate, a transistor, a first dielectric layer disposed on the substrate, a landing pad in the first dielectric layer, a second dielectric layer covering the first dielectric layer and the landing pad, a memory stack in the second dielectric layer, and a source line in the first dielectric layer. The first dielectric layer covers the transistor. The landing pad is situated in a first horizontal plane and is coupled to a drain region of the transistor. The memory stack has a bottom electrode connected to the landing pad and a top electrode electrically connected to a bit line. The source line is situated in a second horizontal plane and is connected to a source region of the transistor. The second horizontal plane and the first horizontal plane are not coplanar.

Abstract: The present invention relates to a structure of a memory device. The structure of a memory device includes a substrate, including a bottom electrode layer formed therein. A buffer layer is disposed on the substrate, in contact with the bottom electrode layer. A resistive layer surrounds a whole sidewall of the buffer layer, and extends upward vertically from the substrate. A mask layer is disposed on the buffer layer and the resistive layer. A noble metal layer is over the substrate, and fully covers the resistive layer and the mask layer. A top electrode layer is disposed on the noble metal layer.

Abstract: A semiconductor device includes: a first metal-oxide semiconductor (MOS) transistor and a second MOS transistor on a substrate; a magnetic tunneling junction (MTJ) between the first MOS transistor and the second MOS transistor; a first interlayer dielectric (ILD) layer on one side of the MTJ and above the first MOS transistor; and a second ILD layer on another side of the MTJ and above the second MOS transistor.

Abstract: A magnetoresistive random access memory (MRAM) is provided in the present invention, including a conductive plug with a protruding portion extending outwardly on one side and a notched portion concaving inwardly on the other side of the upper edge of conductive plug, and a memory cell with a bottom electrode electrically connecting with the conductive plug, a magnetic tunnel junction (MTJ) on the bottom electrode, and a top electrode on the magnetic tunnel junction, wherein the bottom surface of memory cell completely overlaps the top surface of conductive plug.

Abstract: A magnetic memory cell includes a substrate having a memory region, a transistor within the memory region, a first dielectric layer disposed on the substrate, a landing pad in the first dielectric layer, a second dielectric layer covering the first dielectric layer and the landing pad, a cylindrical memory stack in the second dielectric layer, and a source line in the first dielectric layer. The first dielectric layer covers the memory region and the transistor. The landing pad is situated in a first horizontal plane and is coupled to a drain region of the transistor. The cylindrical memory stack has a bottom electrode connected to the landing pad and a top electrode electrically connected to a bit line. The source line is situated in a second horizontal plane and is connected to a source region of the transistor. The second horizontal plane is lower than the first horizontal plane.

Abstract: A magnetoresistive random access memory (MRAM) is provided in the present invention, including a conductive plug with a protruding portion extending outwardly on one side and a notched portion concaving inwardly on the other side of the upper edge of conductive plug, and a memory cell with a bottom electrode electrically connecting with the conductive plug, a magnetic tunnel junction (MTJ) on the bottom electrode, and a top electrode on the magnetic tunnel junction, wherein the bottom surface of memory cell completely overlaps the top surface of conductive plug.

Abstract: A semiconductor device includes: a first metal-oxide semiconductor (MOS) transistor and a second MOS transistor on a substrate; a magnetic tunneling junction (MTJ) between the first MOS transistor and the second MOS transistor; a first interlayer dielectric (ILD) layer on one side of the MTJ and above the first MOS transistor; and a second ILD layer on another side of the MTJ and above the second MOS transistor.

Abstract: A magnetoresistive random access memory (MRAM) is provided in the present invention, including a conductive plug with a protruding portion extending outwardly on one side and a notched portion concaving inwardly on the other side of the upper edge of conductive plug, and a memory cell with a bottom electrode electrically connecting with the conductive plug, a magnetic tunnel junction (MTJ) on the bottom electrode, and a top electrode on the magnetic tunnel junction, wherein the bottom surface of memory cell completely overlaps the top surface of conductive plug.

Abstract: A method for monitoring paging messages in a mobile station with a subscriber identity card camping on a cell is provided. A paging message from the cell is monitored at a set of M predetermined time intervals. A first paging message with a first subscriber identity information being successively broadcasted in the paging channel at a Nth predetermined time interval and a (N+i)th predetermined time interval of the set of M predetermined time intervals is determined. A second paging message with a second subscriber identity information being successively broadcasted in the paging channel at the Nth predetermined time interval and a (N+j)th predetermined time interval of the set of M predetermined time intervals is determined, wherein j>i. The paging channel is monitored at a (N+i)th predetermined time interval and a (N+j)th predetermined time interval of following predetermined time intervals subsequent to the M predetermined time intervals.

Abstract: An isolation structure is disposed between fin field effect transistors of a magnetic random access memory (MRAM) device. The isolation structure includes a fin line substrate, having a trench crossing the fin line substrate. An oxide layer is disposed on the fin line substrate other than the trench. A liner layer is disposed on an indent surface of the trench. A nitride layer is disposed on the liner layer, partially filling the trench. An oxide residue is disposed on the nitride layer within the trench at a bottom portion of the trench. A gate-like structure is disposed on the oxide layer and also fully filling the trench.

Abstract: A method for monitoring paging messages in a mobile station with a subscriber identity card camping on a cell is provided. A paging message from the cell is monitored at a set of M predetermined time intervals. A first paging message with a first subscriber identity information being successively broadcasted in the paging channel at a Nth predetermined time interval and a (N+i)th predetermined time interval of the set of M predetermined time intervals is determined. A second paging message with a second subscriber identity information being successively broadcasted in the paging channel at the Nth predetermined time interval and a (N+j)th predetermined time interval of the set of M predetermined time intervals is determined, wherein j>i. The paging channel is monitored at a (N+i)th predetermined time interval and a (N+j)th predetermined time interval of following predetermined time intervals subsequent to the M predetermined time intervals.

Abstract: A paging channel is monitored at a special position of every predetermined time interval subsequent to the last monitored time. It is detected whether a same first identity information is repeatedly broadcasted in the paging channel at special positions of different predetermined time interval. A total number of periodically repeated messages containing the same first identity information is determined. A new time interval is determined by multiplying a time period between two successive repeated paging messages with the total number of periodically repeated paging messages, wherein the new time interval has a monitoring interval (having a plurality of predetermined time intervals) equaling to the length of the time period and a sleep interval. The paging channel is monitored at special positions of the plurality of predetermined time intervals in every new time interval subsequent to the last monitored time so as to receive subsequent paging messages from the cell.

Abstract: A communication apparatus is provided. A processor is coupled to a first radio access technology (RAT) module, a second RAT module and a radio transceiver shared by the first and second RAT modules. The first RAT module camps on a first serving cell belonging to a first wireless network and is in a packet transfer mode to perform data transfer in the first wireless network via the radio transceiver. The second RAT module camps on a second serving cell belonging to a second wireless network. The processor schedules the second RAT module to receive at least one neighbor cell's information in a portion of a plurality of predetermined frames during the data transfer of the first RAT module via the radio transceiver.