Patents by Inventor Hussein S. El-Ghoroury

Hussein S. El-Ghoroury has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20090086170
    Abstract: Emissive quantum photonic imagers comprised of a spatial array of digitally addressable multicolor pixels. Each pixel is a vertical stack of multiple semiconductor laser diodes, each of which can generate laser light of a different color. Within each multicolor pixel, the light generated from the stack of diodes is emitted perpendicular to the plane of the imager device via a plurality of vertical waveguides that are coupled to the optical confinement regions of each of the multiple laser diodes comprising the imager device. Each of the laser diodes comprising a single pixel is individually addressable, enabling each pixel to simultaneously emit any combination of the colors associated with the laser diodes at any required on/off duty cycle for each color. Each individual multicolor pixel can simultaneously emit the required colors and brightness values by controlling the on/off duty cycles of their respective laser diodes.
    Type: Application
    Filed: December 26, 2007
    Publication date: April 2, 2009
    Applicant: OSTENDO TECHNOLOGIES, INC.
    Inventors: Hussein S. El-Ghoroury, Robert G.W. Brown, Dale A. McNeill, Huibert DenBoer, Andrew J. Lanzone
  • Publication number: 20080218853
    Abstract: The viewing angle brightness sensitivity typically encountered in tiled rear projection display systems cannot be solely overcome by edge blending and calibration techniques. The rear projection array display-screen system of this invention, being comprised of a micro-structure array screen combined with a conventional diffusion screen, overcomes this viewing angle brightness sensitivity in both linear as well as matrix tiled rear projection display systems including those that use wide field-of-view projectors. The latter capability enables low form-factor and compact packaging of tiled rear projection display systems.
    Type: Application
    Filed: April 10, 2007
    Publication date: September 11, 2008
    Inventors: Hussein S. El-Ghoroury, Dale A. McNeill, Jingbo Cai
  • Patent number: 7334901
    Abstract: Low-profile, large screen display using a rear projection array system using an array of micro projectors, each comprised of a micro-display device, several optical components, a red/green/blue light emitting diode light source, a light sensor for each color and power driving and interface electronics circuits. The plurality of Micro Projectors are arranged as an array along the vertices of a grid to conjointly project a uniform and seamless image comprised of the collective projected output pixels (sub-image) of the array of Micro Projectors. The Array Controller processes output signals generated by the light sensors embedded in each Micro Projector in the array and generates pixel gray scale input and light source control signals for each of the Micro Projectors in the array to maintain uniform luminance and chromaticity (color-point) across the array. Various features are disclosed. including tapering and diffusion of the sub-image boundaries to form a single large display.
    Type: Grant
    Filed: April 22, 2005
    Date of Patent: February 26, 2008
    Assignee: Ostendo Technologies, Inc.
    Inventor: Hussein S. El-Ghoroury
  • Publication number: 20070263298
    Abstract: The dilemma encountered in most projection systems of having the etendue of the LED-based light source used often being much larger than the etendue of the imager used, causes such systems to have poor throughput efficiency. The etendue folding illumination systems of this invention being comprised of at least one folded collimator/concentrator having coupled into its input aperture an LED-based light source and having an output aperture characteristics that match the target etendue, overcome this dilemma by folding the light source etendue to match the target etendue of the projection system imager while efficiently conserving the flux generated by the light source.
    Type: Application
    Filed: August 9, 2006
    Publication date: November 15, 2007
    Inventors: Hussein S. El-Ghoroury, Dale A. McNeill
  • Patent number: 7295645
    Abstract: The present invention provides for operation of a digital communication receiver having multiple operational modes so that power consumption of the system can be kept at a minimum by using the lowest power operation for the system components performing tasks associated with each of the respective one of the multiple operational modes. An example is the receiver A/D converter operation with the lowest power to provide the desired resolution. Also, the invention provides novel architectures for implementing scalable resolution A/D converters. Furthermore, the invention generally includes a novel architecture for controlling the dynamic range of an A/D converter. In addition, the invention generally involves novel architectures for controlling the dynamic range of an A/D converter to alleviate difficulties associated with AGC control loops. Multiple exemplary embodiments are disclosed.
    Type: Grant
    Filed: January 29, 2003
    Date of Patent: November 13, 2007
    Assignee: Ellipsis Digital Systems, Inc.
    Inventors: Hussein S. El-Ghoroury, Murat F. Karsi
  • Patent number: 7266487
    Abstract: This invention relates to matched instruction set processor systems and method, system, and apparatus to efficiently compile hardware and software designs. A method to efficiently design and implement a matched instruction set processor system includes analyzing and mapping design specifications of the matched instruction set processor into application components, wherein each application component represents a reusable function commonly used in digital communication systems. The method further includes decomposing the matched instruction set processor system into interconnected design vectors. The method also includes examining fields of the interconnected design factors and mapping the interconnected design vectors into specific hardware and software elements.
    Type: Grant
    Filed: May 28, 2002
    Date of Patent: September 4, 2007
    Assignee: Ellipsis Digital Systems, Inc.
    Inventor: Hussein S. El-Ghoroury
  • Patent number: 7055019
    Abstract: This invention relates to matched instruction set processor systems and a method, system, and apparatus to efficiently design and implement matched instruction set processor systems by mapping system designs to re-configurable hardware platforms. The method includes decomposing the matched instruction set processor system into interconnected design vectors, each of the interconnected design vectors including a binding header method, a run method, a conjugate virtual machine (CVM), a binding trailer method, and an invocation method. The method also includes analyzing and mapping the interconnected design vectors into a re-configurable platform.
    Type: Grant
    Filed: February 11, 2002
    Date of Patent: May 30, 2006
    Assignee: Ellipsis Digital Systems, Inc.
    Inventor: Hussein S. El-Ghoroury
  • Patent number: 6724331
    Abstract: According to one aspect of the invention, an apparatus is provided which includes one or more analog components, an analog to digital (A/D) converter, and a spectral compensator. The operational characteristics of the one or more analog components have variations based on input signal frequency. The one or more analog components perform their corresponding operations with respect to an input analog signal to generate an output analog signal. The analog to digital (A/D) converter is coupled to receive the output analog signal from the one or more analog components and to convert the output analog signal to a digital signal. The spectral compensator is coupled to receive the digital signal generated by the A/D converter and to compensate spectral characteristics of the digital signal based on variations in the operational characteristics of the one or more analog components.
    Type: Grant
    Filed: November 26, 2002
    Date of Patent: April 20, 2004
    Assignee: Ellipsis Digital Systems, Inc.
    Inventors: Hussein S. El-Ghoroury, Murat F. Karsi
  • Patent number: 6456950
    Abstract: The present invention is a method and apparatus to detect an instantaneous frequency of an input signal. A sampler samples the input signal to generate a sampled signal. A metric generator is coupled to the sampler to generate a metric signal based on the sampled signal. The metric signal has a magnitude proportional to the instantaneous frequency of the input signal. In another embodiment, the apparatus comprises a feedback circuit and a decimator. The feedback circuit generates a sequence signal from the input signal. The sequence signal represents a change of the instantaneous frequency of the input signal. The decimator is coupled to the feedback circuit to decimate the sequence signal to generate a frequency signal. The frequency signal providing the instantaneous frequency of the input signal.
    Type: Grant
    Filed: May 19, 1999
    Date of Patent: September 24, 2002
    Assignee: International Business Machines Corporation
    Inventors: Hussein S. El-Ghoroury, Murat F. Karsi, Steven Deane Hall
  • Publication number: 20020116166
    Abstract: This invention relates to matched instruction set processor systems and a method, system, and apparatus to efficiently design and implement matched instruction set process systems using interconnected design components. The method includes decomposing the matched instruction set processor system into interconnected design vectors. The method further includes analyzing and mapping the interconnected design vectors into specific hardware and software elements.
    Type: Application
    Filed: February 11, 2002
    Publication date: August 22, 2002
    Inventor: Hussein S. El-Ghoroury
  • Publication number: 20020116164
    Abstract: This invention relates to matched instruction set processor systems and methods to efficiently design and implement the matched instruction set processor systems. A method to efficiently design and implement a matched instruction set processor system includes analyzing and mapping design specifications of the matched instruction set processor into application components, wherein each application component represents a reusable function commonly used in digital communication systems. The method further includes decomposing the matched instruction set processor system into interconnected design vectors, wherein the design vectors are presented in the Java programming language. The method also includes analyzing and mapping the interconnected design vectors into specific hardware and software elements.
    Type: Application
    Filed: January 18, 2002
    Publication date: August 22, 2002
    Inventor: Hussein S. El-Ghoroury
  • Publication number: 20020116165
    Abstract: This invention relates to matched instruction set processor systems and a method, system, and apparatus to efficiently design and implement matched instruction set processor systems by mapping system designs to re-configurable hardware platforms. The method includes decomposing the matched instruction set processor system into interconnected design vectors, each of the interconnected design vectors including a binding header method, a run method, a conjugate virtual machine (CVM), a binding trailer method, and an invocation method. The method also includes analyzing and mapping the interconnected design vectors into a re-configurable platform.
    Type: Application
    Filed: February 11, 2002
    Publication date: August 22, 2002
    Inventor: Hussein S. El-Ghoroury
  • Publication number: 20020112219
    Abstract: This invention relates to matched instruction set processor systems and methods to efficiently design and implement the matched instruction set processor systems. A method to efficiently design and implement a matched instruction set processor system includes analyzing and mapping design specifications of the matched instruction set processor into application components, wherein each application component represents a reusable function commonly used in digital communication systems. The method further includes decomposing the matched instruction set processor system into interconnected design vectors. The method also includes analyzing and mapping the interconnected design vectors into specific hardware and software elements.
    Type: Application
    Filed: January 18, 2002
    Publication date: August 15, 2002
    Inventor: Hussein S. El-Ghoroury
  • Patent number: 6002352
    Abstract: A simple down converting A/D converter utilizing predictive coding principles. By placing the sampler inside the predictive loop, the predictive loop filter can be implemented using DSP techniques, thus eliminating the complexities introduced by use of discrete-time analog circuitry. Then, by re-mapping the output of the predictive loop filter into the analog domain using a D/A converter, the predictive filter output signal is subtracted from the input analog signal to generate the prediction error signal. Therefore, through directly sampling the prediction error signal and converting the output of the predictive loop filter into analog representation using a low-cost multiple bit D/A, the use of discrete-time analog circuitry is eliminated and the complexity of the converter design is greatly reduced. Various features of the invention are disclosed.
    Type: Grant
    Filed: June 24, 1997
    Date of Patent: December 14, 1999
    Assignee: International Business Machines Corporation
    Inventors: Hussein S. El-Ghoroury, Steven D. Hall, Matthew Millward
  • Patent number: 5697082
    Abstract: A system for self-calibrating a clock of a communication terminal for use with communication systems in which a central communication node generates time base correction signals for the terminal clock includes a terminal oscillator which generates an oscillator frequency that includes an error amount. An oscillator calibration filter generates a frequency error estimate amount. Circuitry is provided for subtracting the frequency error estimate amount generated by the calibration filter from the oscillator frequency error amount. Circuitry is provided for applying the time base correction signals to the calibration filter to thereby modify the frequency error estimate amount generated by the calibration filter based upon the time base correction signals generated by the communication central node.
    Type: Grant
    Filed: September 8, 1995
    Date of Patent: December 9, 1997
    Inventors: Steven Craig Greer, Hussein S. El-Ghoroury
  • Patent number: 5623684
    Abstract: The architecture and design method of an application specific processor ("ASP") is disclosed. The ASP is designed by integrating selected pre-designed application elements contained in a library. These selected application elements can communicate with each other via a bus. Post-synthesis tailoring of the synthesized ASP is accomplished by using an instruction program which sequences the invocation of each application element and provides reconfiguration and data input/output routing commands thereto. A power management design is incorporated within the application elements allowing the majority of the application elements to be turned on only during periods of invocation.
    Type: Grant
    Filed: May 17, 1994
    Date of Patent: April 22, 1997
    Assignee: Commquest Technologies, Inc.
    Inventors: Hussein S. El-Ghoroury, Dale A. McNeill, Charles A. Krause