Abstract: Emissive quantum photonic imagers comprised of a spatial array of digitally addressable multicolor pixels. Each pixel is a vertical stack of multiple semiconductor laser diodes, each of which can generate laser light of a different color. Within each multicolor pixel, the light generated from the stack of diodes is emitted perpendicular to the plane of the imager device via a plurality of vertical waveguides that are coupled to the optical confinement regions of each of the multiple laser diodes comprising the imager device. Each of the laser diodes comprising a single pixel is individually addressable, enabling each pixel to simultaneously emit any combination of the colors associated with the laser diodes at any required on/off duty cycle for each color. Each individual multicolor pixel can simultaneously emit the required colors and brightness values by controlling the on/off duty cycles of their respective laser diodes.

Abstract: This invention describes an apparatus, methods and a system for high speed hierarchical multiplexing the native color primaries of SSL-based display systems in order to improve color quality and stability as well as brightness and the efficiency of the display system.

Abstract: Emissive quantum photonic imagers comprised of a spatial array of digitally addressable multicolor pixels. Each pixel is a vertical stack of multiple semiconductor laser diodes, each of which can generate laser light of a different color. Within each multicolor pixel, the light generated from the stack of diodes is emitted perpendicular to the plane of the imager device via a plurality of vertical waveguides that are coupled to the optical confinement regions of each of the multiple laser diodes comprising the imager device. Each of the laser diodes comprising a single pixel is individually addressable, enabling each pixel to simultaneously emit any combination of the colors associated with the laser diodes at any required on/off duty cycle for each color. Each individual multicolor pixel can simultaneously emit the required colors and brightness values by controlling the on/off duty cycles of their respective laser diodes.

Abstract: A method of growing planar non-polar m-plane or semi-polar III-Nitride material, such as an m-plane gallium nitride (GaN) epitaxial layer, wherein the III-Nitride material is grown on a suitable substrate, such as an m-plane Sapphire substrate, using hydride vapor phase epitaxy (HVPE). The method includes in-situ pretreatment of the substrate at elevated temperatures in the ambient of ammonia and argon, growing an intermediate layer such as an aluminum nitride (AlN) or aluminum-gallium nitride (AlGaN) on the annealed substrate, and growing the non-polar m-plane III-Nitride epitaxial layer on the intermediate layer using HVPE.

Abstract: Emissive quantum photonic imagers comprised of a spatial array of digitally addressable multicolor pixels. Each pixel is a vertical stack of multiple semiconductor laser diodes, each of which can generate laser light of a different color. Within each multicolor pixel, the light generated from the stack of diodes is emitted perpendicular to the plane of the imager device via a plurality of vertical waveguides that are coupled to the optical confinement regions of each of the multiple laser diodes comprising the imager device. Each of the laser diodes comprising a single pixel is individually addressable, enabling each pixel to simultaneously emit any combination of the colors associated with the laser diodes at any required on/off duty cycle for each color. Each individual multicolor pixel can simultaneously emit the required colors and brightness values by controlling the on/off duty cycles of their respective laser diodes.

Abstract: Emissive quantum photonic imagers comprised of a spatial array of digitally addressable multicolor pixels. Each pixel is a vertical stack of multiple semiconductor laser diodes, each of which can generate laser light of a different color. Within each multicolor pixel, the light generated from the stack of diodes is emitted perpendicular to the plane of the imager device via a plurality of vertical waveguides that are coupled to the optical confinement regions of each of the multiple laser diodes comprising the imager device. Each of the laser diodes comprising a single pixel is individually addressable, enabling each pixel to simultaneously emit any combination of the colors associated with the laser diodes at any required on/off duty cycle for each color. Each individual multicolor pixel can simultaneously emit the required colors and brightness values by controlling the on/off duty cycles of their respective laser diodes.

Abstract: Emissive quantum photonic imagers comprised of a spatial array of digitally addressable multicolor pixels. Each pixel is a vertical stack of multiple semiconductor laser diodes, each of which can generate laser light of a different color. Within each multicolor pixel, the light generated from the stack of diodes is emitted perpendicular to the plane of the imager device via a plurality of vertical waveguides that are coupled to the optical confinement regions of each of the multiple laser diodes comprising the imager device. Each of the laser diodes comprising a single pixel is individually addressable, enabling each pixel to simultaneously emit any combination of the colors associated with the laser diodes at any required on/off duty cycle for each color. Each individual multicolor pixel can simultaneously emit the required colors and brightness values by controlling the on/off duty cycles of their respective laser diodes.

Abstract: Emissive quantum photonic imagers comprised of a spatial array of digitally addressable multicolor pixels. Each pixel is a vertical stack of multiple semiconductor laser diodes, each of which can generate laser light of a different color. Within each multicolor pixel, the light generated from the stack of diodes is emitted perpendicular to the plane of the imager device via a plurality of vertical waveguides that are coupled to the optical confinement regions of each of the multiple laser diodes comprising the imager device. Each of the laser diodes comprising a single pixel is individually addressable, enabling each pixel to simultaneously emit any combination of the colors associated with the laser diodes at any required on/off duty cycle for each color. Each individual multicolor pixel can simultaneously emit the required colors and brightness values by controlling the on/off duty cycles of their respective laser diodes.

Abstract: The viewing angle brightness sensitivity typically encountered in tiled rear projection display systems cannot be solely overcome by edge blending and calibration techniques. The rear projection array display-screen system of this invention, being comprised of a micro-structure array screen combined with a conventional diffusion screen, overcomes this viewing angle brightness sensitivity in both linear as well as matrix tiled rear projection display systems including those that use wide field-of-view projectors. The latter capability enables low form-factor and compact packaging of tiled rear projection display systems.

Abstract: Low-profile, large screen display using a rear projection array system using an array of micro projectors, each comprised of a micro-display device, several optical components, a red/green/blue light emitting diode light source, a light sensor for each color and power driving and interface electronics circuits. The plurality of Micro Projectors are arranged as an array along the vertices of a grid to conjointly project a uniform and seamless image comprised of the collective projected output pixels (sub-image) of the array of Micro Projectors. The Array Controller processes output signals generated by the light sensors embedded in each Micro Projector in the array and generates pixel gray scale input and light source control signals for each of the Micro Projectors in the array to maintain uniform luminance and chromaticity (color-point) across the array. Various features are disclosed. including tapering and diffusion of the sub-image boundaries to form a single large display.

Abstract: The dilemma encountered in most projection systems of having the etendue of the LED-based light source used often being much larger than the etendue of the imager used, causes such systems to have poor throughput efficiency. The etendue folding illumination systems of this invention being comprised of at least one folded collimator/concentrator having coupled into its input aperture an LED-based light source and having an output aperture characteristics that match the target etendue, overcome this dilemma by folding the light source etendue to match the target etendue of the projection system imager while efficiently conserving the flux generated by the light source.

Abstract: The present invention provides for operation of a digital communication receiver having multiple operational modes so that power consumption of the system can be kept at a minimum by using the lowest power operation for the system components performing tasks associated with each of the respective one of the multiple operational modes. An example is the receiver A/D converter operation with the lowest power to provide the desired resolution. Also, the invention provides novel architectures for implementing scalable resolution A/D converters. Furthermore, the invention generally includes a novel architecture for controlling the dynamic range of an A/D converter. In addition, the invention generally involves novel architectures for controlling the dynamic range of an A/D converter to alleviate difficulties associated with AGC control loops. Multiple exemplary embodiments are disclosed.

Abstract: This invention relates to matched instruction set processor systems and method, system, and apparatus to efficiently compile hardware and software designs. A method to efficiently design and implement a matched instruction set processor system includes analyzing and mapping design specifications of the matched instruction set processor into application components, wherein each application component represents a reusable function commonly used in digital communication systems. The method further includes decomposing the matched instruction set processor system into interconnected design vectors. The method also includes examining fields of the interconnected design factors and mapping the interconnected design vectors into specific hardware and software elements.

Abstract: This invention relates to matched instruction set processor systems and a method, system, and apparatus to efficiently design and implement matched instruction set processor systems by mapping system designs to re-configurable hardware platforms. The method includes decomposing the matched instruction set processor system into interconnected design vectors, each of the interconnected design vectors including a binding header method, a run method, a conjugate virtual machine (CVM), a binding trailer method, and an invocation method. The method also includes analyzing and mapping the interconnected design vectors into a re-configurable platform.

Abstract: According to one aspect of the invention, an apparatus is provided which includes one or more analog components, an analog to digital (A/D) converter, and a spectral compensator. The operational characteristics of the one or more analog components have variations based on input signal frequency. The one or more analog components perform their corresponding operations with respect to an input analog signal to generate an output analog signal. The analog to digital (A/D) converter is coupled to receive the output analog signal from the one or more analog components and to convert the output analog signal to a digital signal. The spectral compensator is coupled to receive the digital signal generated by the A/D converter and to compensate spectral characteristics of the digital signal based on variations in the operational characteristics of the one or more analog components.

Abstract: The present invention is a method and apparatus to detect an instantaneous frequency of an input signal. A sampler samples the input signal to generate a sampled signal. A metric generator is coupled to the sampler to generate a metric signal based on the sampled signal. The metric signal has a magnitude proportional to the instantaneous frequency of the input signal. In another embodiment, the apparatus comprises a feedback circuit and a decimator. The feedback circuit generates a sequence signal from the input signal. The sequence signal represents a change of the instantaneous frequency of the input signal. The decimator is coupled to the feedback circuit to decimate the sequence signal to generate a frequency signal. The frequency signal providing the instantaneous frequency of the input signal.

Abstract: This invention relates to matched instruction set processor systems and a method, system, and apparatus to efficiently design and implement matched instruction set process systems using interconnected design components. The method includes decomposing the matched instruction set processor system into interconnected design vectors. The method further includes analyzing and mapping the interconnected design vectors into specific hardware and software elements.

Abstract: This invention relates to matched instruction set processor systems and a method, system, and apparatus to efficiently design and implement matched instruction set processor systems by mapping system designs to re-configurable hardware platforms. The method includes decomposing the matched instruction set processor system into interconnected design vectors, each of the interconnected design vectors including a binding header method, a run method, a conjugate virtual machine (CVM), a binding trailer method, and an invocation method. The method also includes analyzing and mapping the interconnected design vectors into a re-configurable platform.

Abstract: This invention relates to matched instruction set processor systems and methods to efficiently design and implement the matched instruction set processor systems. A method to efficiently design and implement a matched instruction set processor system includes analyzing and mapping design specifications of the matched instruction set processor into application components, wherein each application component represents a reusable function commonly used in digital communication systems. The method further includes decomposing the matched instruction set processor system into interconnected design vectors, wherein the design vectors are presented in the Java programming language. The method also includes analyzing and mapping the interconnected design vectors into specific hardware and software elements.

Abstract: This invention relates to matched instruction set processor systems and methods to efficiently design and implement the matched instruction set processor systems. A method to efficiently design and implement a matched instruction set processor system includes analyzing and mapping design specifications of the matched instruction set processor into application components, wherein each application component represents a reusable function commonly used in digital communication systems. The method further includes decomposing the matched instruction set processor system into interconnected design vectors. The method also includes analyzing and mapping the interconnected design vectors into specific hardware and software elements.